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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s3 4# This example is actually equivalent as there's a sub in the loop, which is5# then used by the add in the exit - making the vctp operands equivalent.6 7--- |8 define dso_local i32 @wrong_vctp_liveout(ptr nocapture readonly %a, ptr nocapture readonly %b, i32 %N) local_unnamed_addr #0 {9 entry:10 %cmp9 = icmp eq i32 %N, 011 %0 = add i32 %N, 312 %1 = lshr i32 %0, 213 %2 = shl nuw i32 %1, 214 %3 = add i32 %2, -415 %4 = lshr i32 %3, 216 %5 = add nuw nsw i32 %4, 117 br i1 %cmp9, label %for.cond.cleanup, label %vector.ph18 19 vector.ph: ; preds = %entry20 %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)21 br label %vector.body22 23 vector.body: ; preds = %vector.body, %vector.ph24 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ]25 %lsr.iv18 = phi ptr [ %scevgep19, %vector.body ], [ %b, %vector.ph ]26 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]27 %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %12, %vector.body ]28 %6 = phi i32 [ %N, %vector.ph ], [ %8, %vector.body ]29 %lsr.iv17 = bitcast ptr %lsr.iv to ptr30 %lsr.iv1820 = bitcast ptr %lsr.iv18 to ptr31 %7 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %6)32 %8 = sub i32 %6, 433 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv17, i32 2, <4 x i1> %7, <4 x i16> undef)34 %9 = sext <4 x i16> %wide.masked.load to <4 x i32>35 %wide.masked.load14 = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv1820, i32 2, <4 x i1> %7, <4 x i16> undef)36 %10 = sext <4 x i16> %wide.masked.load14 to <4 x i32>37 %11 = mul nsw <4 x i32> %10, %938 %12 = add <4 x i32> %11, %vec.phi39 %scevgep = getelementptr i16, ptr %lsr.iv, i32 440 %scevgep19 = getelementptr i16, ptr %lsr.iv18, i32 441 %13 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1)42 %14 = icmp ne i32 %13, 043 %lsr.iv.next = add nsw i32 %lsr.iv1, -144 br i1 %14, label %vector.body, label %middle.block45 46 middle.block: ; preds = %vector.body47 %15 = add i32 %8, 448 %16 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %15)49 %17 = select <4 x i1> %16, <4 x i32> %12, <4 x i32> %vec.phi50 %18 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %17)51 br label %for.cond.cleanup52 53 for.cond.cleanup: ; preds = %middle.block, %entry54 %res.0.lcssa = phi i32 [ 0, %entry ], [ %18, %middle.block ]55 ret i32 %res.0.lcssa56 }57 declare <4 x i16> @llvm.masked.load.v4i16.p0(ptr, i32 immarg, <4 x i1>, <4 x i16>)58 declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)59 declare i32 @llvm.start.loop.iterations.i32(i32)60 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)61 declare <4 x i1> @llvm.arm.mve.vctp32(i32)62 63...64---65name: wrong_vctp_liveout66alignment: 267exposesReturnsTwice: false68legalized: false69regBankSelected: false70selected: false71failedISel: false72tracksRegLiveness: true73hasWinCFI: false74registers: []75liveins:76 - { reg: '$r0', virtual-reg: '' }77 - { reg: '$r1', virtual-reg: '' }78 - { reg: '$r2', virtual-reg: '' }79frameInfo:80 isFrameAddressTaken: false81 isReturnAddressTaken: false82 hasStackMap: false83 hasPatchPoint: false84 stackSize: 885 offsetAdjustment: 086 maxAlignment: 487 adjustsStack: false88 hasCalls: false89 stackProtector: ''90 maxCallFrameSize: 091 cvBytesOfCalleeSavedRegisters: 092 hasOpaqueSPAdjustment: false93 hasVAStart: false94 hasMustTailInVarArgFunc: false95 localFrameSize: 096 savePoint: []97 restorePoint: []98fixedStack: []99stack:100 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,101 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,102 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }103 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,104 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,105 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }106callSites: []107constants: []108machineFunctionInfo: {}109body: |110 ; CHECK-LABEL: name: wrong_vctp_liveout111 ; CHECK: bb.0.entry:112 ; CHECK-NEXT: successors: %bb.1(0x80000000)113 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7114 ; CHECK-NEXT: {{ $}}115 ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr116 ; CHECK-NEXT: t2IT 0, 4, implicit-def $itstate117 ; CHECK-NEXT: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate118 ; CHECK-NEXT: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate119 ; CHECK-NEXT: {{ $}}120 ; CHECK-NEXT: bb.1.vector.ph:121 ; CHECK-NEXT: successors: %bb.2(0x80000000)122 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7123 ; CHECK-NEXT: {{ $}}124 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp125 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8126 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4127 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8128 ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg129 ; CHECK-NEXT: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1130 ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg131 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg132 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg133 ; CHECK-NEXT: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg134 ; CHECK-NEXT: dead $lr = t2DLS renamable $r12135 ; CHECK-NEXT: $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg136 ; CHECK-NEXT: {{ $}}137 ; CHECK-NEXT: bb.2.vector.body:138 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)139 ; CHECK-NEXT: liveins: $q1, $r0, $r1, $r2, $r3140 ; CHECK-NEXT: {{ $}}141 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg142 ; CHECK-NEXT: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, $noreg, undef $q0143 ; CHECK-NEXT: MVE_VPST 4, implicit $vpr144 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)145 ; CHECK-NEXT: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2)146 ; CHECK-NEXT: $lr = tMOVr $r3, 14 /* CC::al */, $noreg147 ; CHECK-NEXT: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1148 ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg149 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg150 ; CHECK-NEXT: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1151 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2152 ; CHECK-NEXT: {{ $}}153 ; CHECK-NEXT: bb.3.middle.block:154 ; CHECK-NEXT: liveins: $q0, $q1, $r2155 ; CHECK-NEXT: {{ $}}156 ; CHECK-NEXT: renamable $r0, dead $cpsr = tADDi3 killed renamable $r2, 4, 14 /* CC::al */, $noreg157 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 killed renamable $r0, 0, $noreg, $noreg158 ; CHECK-NEXT: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr, $noreg159 ; CHECK-NEXT: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg160 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0161 bb.0.entry:162 successors: %bb.1(0x80000000)163 liveins: $r0, $r1, $r2, $lr, $r7164 165 tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr166 t2IT 0, 4, implicit-def $itstate167 renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate168 tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate169 170 bb.1.vector.ph:171 successors: %bb.2(0x80000000)172 liveins: $r0, $r1, $r2, $lr, $r7173 174 frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp175 frame-setup CFI_INSTRUCTION def_cfa_offset 8176 frame-setup CFI_INSTRUCTION offset $lr, -4177 frame-setup CFI_INSTRUCTION offset $r7, -8178 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg179 renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1180 renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg181 renamable $r12 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg182 renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg183 renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg184 $lr = t2DoLoopStart renamable $r12185 $r3 = tMOVr killed $r12, 14, $noreg186 187 bb.2.vector.body:188 successors: %bb.2(0x7c000000), %bb.3(0x04000000)189 liveins: $q1, $r0, $r1, $r2, $r3190 191 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg192 $q0 = MVE_VORR killed $q1, $q1, 0, $noreg, $noreg, undef $q0193 MVE_VPST 4, implicit $vpr194 renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)195 renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2)196 $lr = tMOVr $r3, 14, $noreg197 renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1198 renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14, $noreg199 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg200 renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1201 renamable $lr = t2LoopDec killed renamable $lr, 1202 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr203 tB %bb.3, 14, $noreg204 205 bb.3.middle.block:206 liveins: $q0, $q1, $r2207 208 renamable $r0, dead $cpsr = tADDi3 killed renamable $r2, 4, 14, $noreg209 renamable $vpr = MVE_VCTP32 killed renamable $r0, 0, $noreg, $noreg210 renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr, $noreg211 renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg212 tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0213 214...215