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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s3--- |4 define dso_local void @test_vldr_p0(ptr noalias nocapture %arg, ptr noalias nocapture readonly %arg1, i32 %arg2, i16 zeroext %mask) local_unnamed_addr #0 {5 bb:6 %tmp = icmp eq i32 %arg2, 07 %tmp1 = add i32 %arg2, 38 %tmp2 = lshr i32 %tmp1, 29 %tmp3 = shl nuw i32 %tmp2, 210 %tmp4 = add i32 %tmp3, -411 %tmp5 = lshr i32 %tmp4, 212 %tmp6 = add nuw nsw i32 %tmp5, 113 %conv.mask = zext i16 %mask to i3214 %invariant.mask = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %conv.mask)15 br i1 %tmp, label %bb27, label %bb316 17 bb3: ; preds = %bb18 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp6)19 br label %bb920 21 bb9: ; preds = %bb9, %bb322 %lsr.iv2 = phi ptr [ %scevgep3, %bb9 ], [ %arg1, %bb3 ]23 %lsr.iv = phi ptr [ %scevgep, %bb9 ], [ %arg, %bb3 ]24 %tmp7 = phi i32 [ %start, %bb3 ], [ %tmp12, %bb9 ]25 %tmp8 = phi i32 [ %arg2, %bb3 ], [ %tmp11, %bb9 ]26 %lsr.iv24 = bitcast ptr %lsr.iv2 to ptr27 %lsr.iv1 = bitcast ptr %lsr.iv to ptr28 %vctp = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp8)29 %and = and <4 x i1> %vctp, %invariant.mask30 %tmp11 = sub i32 %tmp8, 431 %tmp17 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv24, i32 4, <4 x i1> %and, <4 x i32> undef)32 %tmp22 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv1, i32 4, <4 x i1> %and, <4 x i32> undef)33 %tmp23 = mul nsw <4 x i32> %tmp22, %tmp1734 call void @llvm.masked.store.v4i32.p0(<4 x i32> %tmp23, ptr %lsr.iv1, i32 4, <4 x i1> %and)35 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %tmp7, i32 1)36 %tmp13 = icmp ne i32 %tmp12, 037 %scevgep = getelementptr i32, ptr %lsr.iv, i32 438 %scevgep3 = getelementptr i32, ptr %lsr.iv2, i32 439 br i1 %tmp13, label %bb9, label %bb2740 41 bb27: ; preds = %bb9, %bb42 ret void43 }44 45 define dso_local void @test_vstr_p0(ptr noalias nocapture %arg, ptr noalias nocapture readonly %arg1, i32 %arg2, i16 zeroext %mask) {46 bb:47 unreachable48 bb3: ; preds = %bb49 unreachable50 bb9: ; preds = %bb9, %bb351 unreachable52 bb27: ; preds = %bb9, %bb53 ret void54 }55 56 define dso_local void @test_vmsr_p0(ptr noalias nocapture %arg, ptr noalias nocapture readonly %arg1, i32 %arg2, i16 zeroext %mask) {57 bb:58 unreachable59 bb3: ; preds = %bb60 unreachable61 bb9: ; preds = %bb9, %bb362 unreachable63 bb27: ; preds = %bb9, %bb64 ret void65 }66 67 define dso_local void @test_vmrs_p0(ptr noalias nocapture %arg, ptr noalias nocapture readonly %arg1, i32 %arg2, i16 zeroext %mask) {68 bb:69 unreachable70 bb3: ; preds = %bb71 unreachable72 bb9: ; preds = %bb9, %bb373 unreachable74 bb27: ; preds = %bb9, %bb75 ret void76 }77 78 declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>) #179 declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr, i32 immarg, <4 x i1>) #280 declare i32 @llvm.start.loop.iterations.i32(i32) #381 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #382 declare <4 x i1> @llvm.arm.mve.vctp32(i32) #483 declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #484 85...86---87name: test_vldr_p088alignment: 289exposesReturnsTwice: false90legalized: false91regBankSelected: false92selected: false93failedISel: false94tracksRegLiveness: true95hasWinCFI: false96registers: []97liveins:98 - { reg: '$r0', virtual-reg: '' }99 - { reg: '$r1', virtual-reg: '' }100 - { reg: '$r2', virtual-reg: '' }101 - { reg: '$r3', virtual-reg: '' }102frameInfo:103 isFrameAddressTaken: false104 isReturnAddressTaken: false105 hasStackMap: false106 hasPatchPoint: false107 stackSize: 12108 offsetAdjustment: -4109 maxAlignment: 4110 adjustsStack: false111 hasCalls: false112 stackProtector: ''113 maxCallFrameSize: 0114 cvBytesOfCalleeSavedRegisters: 0115 hasOpaqueSPAdjustment: false116 hasVAStart: false117 hasMustTailInVarArgFunc: false118 localFrameSize: 0119 savePoint: []120 restorePoint: []121fixedStack: []122stack:123 - { id: 0, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,124 stack-id: default, callee-saved-register: '', callee-saved-restored: true,125 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }126 - { id: 1, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,127 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,128 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }129 - { id: 2, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,130 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,131 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }132callSites: []133constants: []134machineFunctionInfo: {}135body: |136 ; CHECK-LABEL: name: test_vldr_p0137 ; CHECK: bb.0.bb:138 ; CHECK-NEXT: successors: %bb.3(0x30000000), %bb.1(0x50000000)139 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3140 ; CHECK-NEXT: {{ $}}141 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp142 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8143 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4144 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8145 ; CHECK-NEXT: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg146 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $r7147 ; CHECK-NEXT: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg148 ; CHECK-NEXT: tCBZ $r2, %bb.3149 ; CHECK-NEXT: {{ $}}150 ; CHECK-NEXT: bb.1.bb3:151 ; CHECK-NEXT: successors: %bb.2(0x80000000)152 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3153 ; CHECK-NEXT: {{ $}}154 ; CHECK-NEXT: $vpr = VMSR_P0 killed $r3, 14 /* CC::al */, $noreg155 ; CHECK-NEXT: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0)156 ; CHECK-NEXT: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg157 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r2158 ; CHECK-NEXT: {{ $}}159 ; CHECK-NEXT: bb.2.bb9:160 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)161 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r3162 ; CHECK-NEXT: {{ $}}163 ; CHECK-NEXT: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0)164 ; CHECK-NEXT: MVE_VPST 4, implicit $vpr165 ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv24, align 4)166 ; CHECK-NEXT: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1, align 4)167 ; CHECK-NEXT: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0168 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr169 ; CHECK-NEXT: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1, align 4)170 ; CHECK-NEXT: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg171 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2172 ; CHECK-NEXT: {{ $}}173 ; CHECK-NEXT: bb.3.bb27:174 ; CHECK-NEXT: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg175 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc176 bb.0.bb:177 successors: %bb.3(0x30000000), %bb.1(0x50000000)178 liveins: $r0, $r1, $r2, $r3, $lr179 180 frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp181 frame-setup CFI_INSTRUCTION def_cfa_offset 8182 frame-setup CFI_INSTRUCTION offset $lr, -4183 frame-setup CFI_INSTRUCTION offset $r7, -8184 $r7 = frame-setup tMOVr $sp, 14, $noreg185 frame-setup CFI_INSTRUCTION def_cfa_register $r7186 $sp = frame-setup tSUBspi $sp, 1, 14, $noreg187 tCBZ $r2, %bb.3188 189 bb.1.bb3:190 successors: %bb.2(0x80000000)191 liveins: $r0, $r1, $r2, $r3192 193 renamable $r12 = t2ADDri renamable $r2, 3, 14, $noreg, $noreg194 renamable $lr = t2MOVi 1, 14, $noreg, $noreg195 renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg196 $vpr = VMSR_P0 killed $r3, 14, $noreg197 renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg198 VSTR_P0_off killed renamable $vpr, $sp, 0, 14, $noreg :: (store (s32) into %stack.0)199 $r3 = tMOVr $r0, 14, $noreg200 renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg201 $lr = t2DoLoopStart renamable $lr202 203 bb.2.bb9:204 successors: %bb.2(0x7c000000), %bb.3(0x04000000)205 liveins: $lr, $r0, $r1, $r2, $r3206 207 renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load (s32) from %stack.0)208 MVE_VPST 2, implicit $vpr209 renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg210 renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv24, align 4)211 renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1, align 4)212 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg213 renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0214 MVE_VPST 8, implicit $vpr215 MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1, align 4)216 renamable $lr = t2LoopDec killed renamable $lr, 1217 $r0 = tMOVr $r3, 14, $noreg218 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr219 tB %bb.3, 14, $noreg220 221 bb.3.bb27:222 $sp = tADDspi $sp, 1, 14, $noreg223 tPOP_RET 14, $noreg, def $r7, def $pc224 225...226---227name: test_vstr_p0228alignment: 2229exposesReturnsTwice: false230legalized: false231regBankSelected: false232selected: false233failedISel: false234tracksRegLiveness: true235hasWinCFI: false236registers: []237liveins:238 - { reg: '$r0', virtual-reg: '' }239 - { reg: '$r1', virtual-reg: '' }240 - { reg: '$r2', virtual-reg: '' }241 - { reg: '$r3', virtual-reg: '' }242frameInfo:243 isFrameAddressTaken: false244 isReturnAddressTaken: false245 hasStackMap: false246 hasPatchPoint: false247 stackSize: 12248 offsetAdjustment: -4249 maxAlignment: 4250 adjustsStack: false251 hasCalls: false252 stackProtector: ''253 maxCallFrameSize: 0254 cvBytesOfCalleeSavedRegisters: 0255 hasOpaqueSPAdjustment: false256 hasVAStart: false257 hasMustTailInVarArgFunc: false258 localFrameSize: 0259 savePoint: []260 restorePoint: []261fixedStack: []262stack:263 - { id: 0, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,264 stack-id: default, callee-saved-register: '', callee-saved-restored: true,265 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }266 - { id: 1, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,267 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,268 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }269 - { id: 2, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,270 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,271 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }272callSites: []273constants: []274machineFunctionInfo: {}275body: |276 ; CHECK-LABEL: name: test_vstr_p0277 ; CHECK: bb.0.bb:278 ; CHECK-NEXT: successors: %bb.3(0x30000000), %bb.1(0x50000000)279 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3280 ; CHECK-NEXT: {{ $}}281 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp282 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8283 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4284 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8285 ; CHECK-NEXT: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg286 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $r7287 ; CHECK-NEXT: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg288 ; CHECK-NEXT: tCBZ $r2, %bb.3289 ; CHECK-NEXT: {{ $}}290 ; CHECK-NEXT: bb.1.bb3:291 ; CHECK-NEXT: successors: %bb.2(0x80000000)292 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3293 ; CHECK-NEXT: {{ $}}294 ; CHECK-NEXT: renamable $r12 = t2ADDri renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg295 ; CHECK-NEXT: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg296 ; CHECK-NEXT: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg297 ; CHECK-NEXT: $vpr = VMSR_P0 killed $r3, 14 /* CC::al */, $noreg298 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg299 ; CHECK-NEXT: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0)300 ; CHECK-NEXT: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg301 ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg302 ; CHECK-NEXT: {{ $}}303 ; CHECK-NEXT: bb.2.bb9:304 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)305 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3306 ; CHECK-NEXT: {{ $}}307 ; CHECK-NEXT: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0)308 ; CHECK-NEXT: MVE_VPST 2, implicit $vpr309 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg310 ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg311 ; CHECK-NEXT: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr, $noreg312 ; CHECK-NEXT: VSTR_P0_off renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0)313 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg314 ; CHECK-NEXT: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0315 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr316 ; CHECK-NEXT: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg317 ; CHECK-NEXT: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg318 ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2319 ; CHECK-NEXT: {{ $}}320 ; CHECK-NEXT: bb.3.bb27:321 ; CHECK-NEXT: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg322 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc323 bb.0.bb:324 successors: %bb.3(0x30000000), %bb.1(0x50000000)325 liveins: $r0, $r1, $r2, $r3, $lr326 327 frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp328 frame-setup CFI_INSTRUCTION def_cfa_offset 8329 frame-setup CFI_INSTRUCTION offset $lr, -4330 frame-setup CFI_INSTRUCTION offset $r7, -8331 $r7 = frame-setup tMOVr $sp, 14, $noreg332 frame-setup CFI_INSTRUCTION def_cfa_register $r7333 $sp = frame-setup tSUBspi $sp, 1, 14, $noreg334 tCBZ $r2, %bb.3335 336 bb.1.bb3:337 successors: %bb.2(0x80000000)338 liveins: $r0, $r1, $r2, $r3339 340 renamable $r12 = t2ADDri renamable $r2, 3, 14, $noreg, $noreg341 renamable $lr = t2MOVi 1, 14, $noreg, $noreg342 renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg343 $vpr = VMSR_P0 killed $r3, 14, $noreg344 renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg345 VSTR_P0_off killed renamable $vpr, $sp, 0, 14, $noreg :: (store (s32) into %stack.0)346 $r3 = tMOVr $r0, 14, $noreg347 renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg348 $lr = t2DoLoopStart renamable $lr349 350 bb.2.bb9:351 successors: %bb.2(0x7c000000), %bb.3(0x04000000)352 liveins: $lr, $r0, $r1, $r2, $r3353 354 renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load (s32) from %stack.0)355 MVE_VPST 2, implicit $vpr356 renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg357 renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg358 renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr, $noreg359 VSTR_P0_off renamable $vpr, $sp, 0, 14, $noreg :: (store (s32) into %stack.0)360 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg361 renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0362 MVE_VPST 8, implicit $vpr363 MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg364 renamable $lr = t2LoopDec killed renamable $lr, 1365 $r0 = tMOVr $r3, 14, $noreg366 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr367 tB %bb.3, 14, $noreg368 369 bb.3.bb27:370 $sp = tADDspi $sp, 1, 14, $noreg371 tPOP_RET 14, $noreg, def $r7, def $pc372 373...374---375name: test_vmsr_p0376alignment: 2377exposesReturnsTwice: false378legalized: false379regBankSelected: false380selected: false381failedISel: false382tracksRegLiveness: true383hasWinCFI: false384registers: []385liveins:386 - { reg: '$r0', virtual-reg: '' }387 - { reg: '$r1', virtual-reg: '' }388 - { reg: '$r2', virtual-reg: '' }389 - { reg: '$r3', virtual-reg: '' }390frameInfo:391 isFrameAddressTaken: false392 isReturnAddressTaken: false393 hasStackMap: false394 hasPatchPoint: false395 stackSize: 12396 offsetAdjustment: -4397 maxAlignment: 4398 adjustsStack: false399 hasCalls: false400 stackProtector: ''401 maxCallFrameSize: 0402 cvBytesOfCalleeSavedRegisters: 0403 hasOpaqueSPAdjustment: false404 hasVAStart: false405 hasMustTailInVarArgFunc: false406 localFrameSize: 0407 savePoint: []408 restorePoint: []409fixedStack: []410stack:411 - { id: 0, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,412 stack-id: default, callee-saved-register: '', callee-saved-restored: true,413 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }414 - { id: 1, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,415 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,416 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }417 - { id: 2, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,418 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,419 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }420callSites: []421constants: []422machineFunctionInfo: {}423body: |424 ; CHECK-LABEL: name: test_vmsr_p0425 ; CHECK: bb.0.bb:426 ; CHECK-NEXT: successors: %bb.3(0x30000000), %bb.1(0x50000000)427 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3428 ; CHECK-NEXT: {{ $}}429 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp430 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8431 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4432 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8433 ; CHECK-NEXT: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg434 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $r7435 ; CHECK-NEXT: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg436 ; CHECK-NEXT: tCBZ $r2, %bb.3437 ; CHECK-NEXT: {{ $}}438 ; CHECK-NEXT: bb.1.bb3:439 ; CHECK-NEXT: successors: %bb.2(0x80000000)440 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3441 ; CHECK-NEXT: {{ $}}442 ; CHECK-NEXT: renamable $r12 = t2ADDri renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg443 ; CHECK-NEXT: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg444 ; CHECK-NEXT: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg445 ; CHECK-NEXT: $vpr = VMSR_P0 killed $r3, 14 /* CC::al */, $noreg446 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg447 ; CHECK-NEXT: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0)448 ; CHECK-NEXT: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg449 ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg450 ; CHECK-NEXT: {{ $}}451 ; CHECK-NEXT: bb.2.bb9:452 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)453 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3454 ; CHECK-NEXT: {{ $}}455 ; CHECK-NEXT: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0)456 ; CHECK-NEXT: MVE_VPST 2, implicit $vpr457 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg458 ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg459 ; CHECK-NEXT: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, killed renamable $vpr, $noreg460 ; CHECK-NEXT: $vpr = VMSR_P0 $r3, 14 /* CC::al */, $noreg461 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg462 ; CHECK-NEXT: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0463 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr464 ; CHECK-NEXT: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg465 ; CHECK-NEXT: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg466 ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2467 ; CHECK-NEXT: {{ $}}468 ; CHECK-NEXT: bb.3.bb27:469 ; CHECK-NEXT: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg470 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc471 bb.0.bb:472 successors: %bb.3(0x30000000), %bb.1(0x50000000)473 liveins: $r0, $r1, $r2, $r3, $lr474 475 frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp476 frame-setup CFI_INSTRUCTION def_cfa_offset 8477 frame-setup CFI_INSTRUCTION offset $lr, -4478 frame-setup CFI_INSTRUCTION offset $r7, -8479 $r7 = frame-setup tMOVr $sp, 14, $noreg480 frame-setup CFI_INSTRUCTION def_cfa_register $r7481 $sp = frame-setup tSUBspi $sp, 1, 14, $noreg482 tCBZ $r2, %bb.3483 484 bb.1.bb3:485 successors: %bb.2(0x80000000)486 liveins: $r0, $r1, $r2, $r3487 488 renamable $r12 = t2ADDri renamable $r2, 3, 14, $noreg, $noreg489 renamable $lr = t2MOVi 1, 14, $noreg, $noreg490 renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg491 $vpr = VMSR_P0 killed $r3, 14, $noreg492 renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg493 VSTR_P0_off killed renamable $vpr, $sp, 0, 14, $noreg :: (store (s32) into %stack.0)494 $r3 = tMOVr $r0, 14, $noreg495 renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg496 $lr = t2DoLoopStart renamable $lr497 498 bb.2.bb9:499 successors: %bb.2(0x7c000000), %bb.3(0x04000000)500 liveins: $lr, $r0, $r1, $r2, $r3501 502 renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load (s32) from %stack.0)503 MVE_VPST 2, implicit $vpr504 renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg505 renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg506 renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr, $noreg507 $vpr = VMSR_P0 $r3, 14, $noreg508 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg509 renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0510 MVE_VPST 8, implicit $vpr511 MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg512 renamable $lr = t2LoopDec killed renamable $lr, 1513 $r0 = tMOVr $r3, 14, $noreg514 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr515 tB %bb.3, 14, $noreg516 517 bb.3.bb27:518 $sp = tADDspi $sp, 1, 14, $noreg519 tPOP_RET 14, $noreg, def $r7, def $pc520 521...522---523name: test_vmrs_p0524alignment: 2525exposesReturnsTwice: false526legalized: false527regBankSelected: false528selected: false529failedISel: false530tracksRegLiveness: true531hasWinCFI: false532registers: []533liveins:534 - { reg: '$r0', virtual-reg: '' }535 - { reg: '$r1', virtual-reg: '' }536 - { reg: '$r2', virtual-reg: '' }537 - { reg: '$r3', virtual-reg: '' }538frameInfo:539 isFrameAddressTaken: false540 isReturnAddressTaken: false541 hasStackMap: false542 hasPatchPoint: false543 stackSize: 12544 offsetAdjustment: -4545 maxAlignment: 4546 adjustsStack: false547 hasCalls: false548 stackProtector: ''549 maxCallFrameSize: 0550 cvBytesOfCalleeSavedRegisters: 0551 hasOpaqueSPAdjustment: false552 hasVAStart: false553 hasMustTailInVarArgFunc: false554 localFrameSize: 0555 savePoint: []556 restorePoint: []557fixedStack: []558stack:559 - { id: 0, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,560 stack-id: default, callee-saved-register: '', callee-saved-restored: true,561 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }562 - { id: 1, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,563 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,564 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }565 - { id: 2, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,566 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,567 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }568callSites: []569constants: []570machineFunctionInfo: {}571body: |572 ; CHECK-LABEL: name: test_vmrs_p0573 ; CHECK: bb.0.bb:574 ; CHECK-NEXT: successors: %bb.3(0x30000000), %bb.1(0x50000000)575 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3576 ; CHECK-NEXT: {{ $}}577 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp578 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8579 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4580 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8581 ; CHECK-NEXT: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg582 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $r7583 ; CHECK-NEXT: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg584 ; CHECK-NEXT: tCBZ $r2, %bb.3585 ; CHECK-NEXT: {{ $}}586 ; CHECK-NEXT: bb.1.bb3:587 ; CHECK-NEXT: successors: %bb.2(0x80000000)588 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3589 ; CHECK-NEXT: {{ $}}590 ; CHECK-NEXT: renamable $r12 = t2ADDri renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg591 ; CHECK-NEXT: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg592 ; CHECK-NEXT: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg593 ; CHECK-NEXT: $vpr = VMSR_P0 killed $r3, 14 /* CC::al */, $noreg594 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg595 ; CHECK-NEXT: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0)596 ; CHECK-NEXT: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg597 ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg598 ; CHECK-NEXT: {{ $}}599 ; CHECK-NEXT: bb.2.bb9:600 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)601 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3602 ; CHECK-NEXT: {{ $}}603 ; CHECK-NEXT: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0)604 ; CHECK-NEXT: MVE_VPST 2, implicit $vpr605 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg606 ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg607 ; CHECK-NEXT: dead renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr, $noreg608 ; CHECK-NEXT: $r3 = VMRS_P0 $vpr, 14 /* CC::al */, $noreg609 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg610 ; CHECK-NEXT: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0611 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr612 ; CHECK-NEXT: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg613 ; CHECK-NEXT: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg614 ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2615 ; CHECK-NEXT: {{ $}}616 ; CHECK-NEXT: bb.3.bb27:617 ; CHECK-NEXT: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg618 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc619 bb.0.bb:620 successors: %bb.3(0x30000000), %bb.1(0x50000000)621 liveins: $r0, $r1, $r2, $r3, $lr622 623 frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp624 frame-setup CFI_INSTRUCTION def_cfa_offset 8625 frame-setup CFI_INSTRUCTION offset $lr, -4626 frame-setup CFI_INSTRUCTION offset $r7, -8627 $r7 = frame-setup tMOVr $sp, 14, $noreg628 frame-setup CFI_INSTRUCTION def_cfa_register $r7629 $sp = frame-setup tSUBspi $sp, 1, 14, $noreg630 tCBZ $r2, %bb.3631 632 bb.1.bb3:633 successors: %bb.2(0x80000000)634 liveins: $r0, $r1, $r2, $r3635 636 renamable $r12 = t2ADDri renamable $r2, 3, 14, $noreg, $noreg637 renamable $lr = t2MOVi 1, 14, $noreg, $noreg638 renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg639 $vpr = VMSR_P0 killed $r3, 14, $noreg640 renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg641 VSTR_P0_off killed renamable $vpr, $sp, 0, 14, $noreg :: (store (s32) into %stack.0)642 $r3 = tMOVr $r0, 14, $noreg643 renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg644 $lr = t2DoLoopStart renamable $lr645 646 bb.2.bb9:647 successors: %bb.2(0x7c000000), %bb.3(0x04000000)648 liveins: $lr, $r0, $r1, $r2, $r3649 650 renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load (s32) from %stack.0)651 MVE_VPST 2, implicit $vpr652 renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg653 renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg654 renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr, $noreg655 $r3 = VMRS_P0 $vpr, 14, $noreg656 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg657 renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0658 MVE_VPST 8, implicit $vpr659 MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg660 renamable $lr = t2LoopDec killed renamable $lr, 1661 $r0 = tMOVr $r3, 14, $noreg662 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr663 tB %bb.3, 14, $noreg664 665 bb.3.bb27:666 $sp = tADDspi $sp, 1, 14, $noreg667 tPOP_RET 14, $noreg, def $r7, def $pc668 669...670