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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve,+lob -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s3 4--- |5 define dso_local void @vctp_tsubi3(ptr noalias nocapture %A, ptr noalias nocapture readonly %B, ptr noalias nocapture readonly %C, i32 %N) local_unnamed_addr #0 {6 entry:7 %cmp8 = icmp sgt i32 %N, 08 %0 = add i32 %N, 39 %1 = lshr i32 %0, 210 %2 = shl nuw i32 %1, 211 %3 = add i32 %2, -412 %4 = lshr i32 %3, 213 %5 = add nuw nsw i32 %4, 114 br i1 %cmp8, label %vector.ph, label %for.cond.cleanup15 16 vector.ph: ; preds = %entry17 %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)18 br label %vector.body19 20 vector.body: ; preds = %vector.body, %vector.ph21 %lsr.iv17 = phi ptr [ %scevgep18, %vector.body ], [ %A, %vector.ph ]22 %lsr.iv14 = phi ptr [ %scevgep15, %vector.body ], [ %C, %vector.ph ]23 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %B, %vector.ph ]24 %6 = phi i32 [ %start, %vector.ph ], [ %11, %vector.body ]25 %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ]26 %lsr.iv13 = bitcast ptr %lsr.iv to ptr27 %lsr.iv1416 = bitcast ptr %lsr.iv14 to ptr28 %lsr.iv1719 = bitcast ptr %lsr.iv17 to ptr29 %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7)30 %9 = sub i32 %7, 531 %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv13, i32 4, <4 x i1> %8, <4 x i32> undef)32 %wide.masked.load12 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv1416, i32 4, <4 x i1> %8, <4 x i32> undef)33 %10 = add nsw <4 x i32> %wide.masked.load12, %wide.masked.load34 call void @llvm.masked.store.v4i32.p0(<4 x i32> %10, ptr %lsr.iv1719, i32 4, <4 x i1> %8)35 %scevgep = getelementptr i32, ptr %lsr.iv, i32 436 %scevgep15 = getelementptr i32, ptr %lsr.iv14, i32 437 %scevgep18 = getelementptr i32, ptr %lsr.iv17, i32 438 %11 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %6, i32 1)39 %12 = icmp ne i32 %11, 040 br i1 %12, label %vector.body, label %for.cond.cleanup41 42 for.cond.cleanup: ; preds = %vector.body, %entry43 ret void44 }45 declare i32 @llvm.start.loop.iterations.i32(i32)46 declare <4 x i1> @llvm.arm.mve.vctp32(i32)47 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)48 declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>)49 declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr, i32 immarg, <4 x i1>)50 51...52---53name: vctp_tsubi354alignment: 255exposesReturnsTwice: false56legalized: false57regBankSelected: false58selected: false59failedISel: false60tracksRegLiveness: true61hasWinCFI: false62registers: []63liveins:64 - { reg: '$r0', virtual-reg: '' }65 - { reg: '$r1', virtual-reg: '' }66 - { reg: '$r2', virtual-reg: '' }67 - { reg: '$r3', virtual-reg: '' }68frameInfo:69 isFrameAddressTaken: false70 isReturnAddressTaken: false71 hasStackMap: false72 hasPatchPoint: false73 stackSize: 874 offsetAdjustment: 075 maxAlignment: 476 adjustsStack: false77 hasCalls: false78 stackProtector: ''79 maxCallFrameSize: 080 cvBytesOfCalleeSavedRegisters: 081 hasOpaqueSPAdjustment: false82 hasVAStart: false83 hasMustTailInVarArgFunc: false84 localFrameSize: 085 savePoint: []86 restorePoint: []87fixedStack: []88stack:89 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,90 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,91 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }92 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,93 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,94 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }95callSites: []96constants: []97machineFunctionInfo: {}98body: |99 ; CHECK-LABEL: name: vctp_tsubi3100 ; CHECK: bb.0.entry:101 ; CHECK-NEXT: successors: %bb.1(0x80000000)102 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r7103 ; CHECK-NEXT: {{ $}}104 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp105 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8106 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4107 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8108 ; CHECK-NEXT: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr109 ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate110 ; CHECK-NEXT: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate111 ; CHECK-NEXT: {{ $}}112 ; CHECK-NEXT: bb.1.vector.ph:113 ; CHECK-NEXT: successors: %bb.2(0x80000000)114 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3115 ; CHECK-NEXT: {{ $}}116 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r3117 ; CHECK-NEXT: {{ $}}118 ; CHECK-NEXT: bb.2.vector.body:119 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)120 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2121 ; CHECK-NEXT: {{ $}}122 ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv13, align 4)123 ; CHECK-NEXT: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4)124 ; CHECK-NEXT: renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0125 ; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv1719, align 4)126 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2127 ; CHECK-NEXT: {{ $}}128 ; CHECK-NEXT: bb.3.for.cond.cleanup:129 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc130 bb.0.entry:131 successors: %bb.1(0x80000000)132 liveins: $r0, $r1, $r2, $r3, $r7, $lr133 134 frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp135 frame-setup CFI_INSTRUCTION def_cfa_offset 8136 frame-setup CFI_INSTRUCTION offset $lr, -4137 frame-setup CFI_INSTRUCTION offset $r7, -8138 tCMPi8 renamable $r3, 1, 14, $noreg, implicit-def $cpsr139 t2IT 11, 8, implicit-def $itstate140 tPOP_RET 11, killed $cpsr, def $r7, def $pc, implicit killed $itstate141 142 bb.1.vector.ph:143 successors: %bb.2(0x80000000)144 liveins: $r0, $r1, $r2, $r3, $r7, $lr145 146 renamable $r12 = t2ADDri renamable $r3, 3, 14, $noreg, $noreg147 renamable $lr = t2MOVi 1, 14, $noreg, $noreg148 renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg149 renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg150 renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg151 $lr = t2DoLoopStart renamable $lr152 153 bb.2.vector.body:154 successors: %bb.2(0x7c000000), %bb.3(0x04000000)155 liveins: $lr, $r0, $r1, $r2, $r3156 157 renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg158 MVE_VPST 4, implicit $vpr159 renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv13, align 4)160 renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4)161 renamable $r3 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg162 renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0163 MVE_VPST 8, implicit $vpr164 renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1719, align 4)165 renamable $lr = t2LoopDec killed renamable $lr, 1166 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr167 tB %bb.3, 14, $noreg168 169 bb.3.for.cond.cleanup:170 tPOP_RET 14, $noreg, def $r7, def $pc171 172...173