92 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 62 3; RUN: opt -mtriple=thumbv8.1m.main -mve-tail-predication -tail-predication=enabled -mattr=+mve %s -S -o - | FileCheck %s4 5define i32 @vec_mul_reduce_add(ptr noalias nocapture readonly %a, ptr noalias nocapture readonly %b, i32 %N) {6; CHECK-LABEL: define i32 @vec_mul_reduce_add(7; CHECK-SAME: ptr noalias readonly captures(none) [[A:%.*]], ptr noalias readonly captures(none) [[B:%.*]], i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {8; CHECK-NEXT: [[ENTRY:.*]]:9; CHECK-NEXT: [[CMP8:%.*]] = icmp eq i32 [[N]], 010; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], 311; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[TMP0]], 212; CHECK-NEXT: [[TMP2:%.*]] = shl nuw i32 [[TMP1]], 213; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[TMP2]], -414; CHECK-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 215; CHECK-NEXT: [[TMP5:%.*]] = add nuw nsw i32 [[TMP4]], 116; CHECK-NEXT: br i1 [[CMP8]], label %[[FOR_COND_CLEANUP:.*]], label %[[VECTOR_PH:.*]]17; CHECK: [[VECTOR_PH]]:18; CHECK-NEXT: [[START:%.*]] = call i32 @llvm.start.loop.iterations.i32(i32 [[TMP5]])19; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]20; CHECK: [[VECTOR_BODY]]:21; CHECK-NEXT: [[LSR_IV2:%.*]] = phi ptr [ [[SCEVGEP3:%.*]], %[[VECTOR_BODY]] ], [ [[A]], %[[VECTOR_PH]] ]22; CHECK-NEXT: [[LSR_IV:%.*]] = phi ptr [ [[SCEVGEP:%.*]], %[[VECTOR_BODY]] ], [ [[B]], %[[VECTOR_PH]] ]23; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP11:%.*]], %[[VECTOR_BODY]] ]24; CHECK-NEXT: [[TMP6:%.*]] = phi i32 [ [[START]], %[[VECTOR_PH]] ], [ [[TMP12:%.*]], %[[VECTOR_BODY]] ]25; CHECK-NEXT: [[TMP7:%.*]] = phi i32 [ [[N]], %[[VECTOR_PH]] ], [ [[TMP9:%.*]], %[[VECTOR_BODY]] ]26; CHECK-NEXT: [[TMP8:%.*]] = call <4 x i1> @llvm.arm.mve.vctp32(i32 [[TMP7]])27; CHECK-NEXT: [[TMP9]] = sub i32 [[TMP7]], 428; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 4 [[LSR_IV2]], <4 x i1> [[TMP8]], <4 x i32> undef)29; CHECK-NEXT: [[WIDE_MASKED_LOAD13:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 4 [[LSR_IV]], <4 x i1> [[TMP8]], <4 x i32> undef)30; CHECK-NEXT: [[TMP10:%.*]] = mul nsw <4 x i32> [[WIDE_MASKED_LOAD13]], [[WIDE_MASKED_LOAD]]31; CHECK-NEXT: [[TMP11]] = add nsw <4 x i32> [[TMP10]], [[VEC_PHI]]32; CHECK-NEXT: [[SCEVGEP]] = getelementptr i32, ptr [[LSR_IV]], i32 433; CHECK-NEXT: [[SCEVGEP3]] = getelementptr i32, ptr [[LSR_IV2]], i32 434; CHECK-NEXT: [[TMP12]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[TMP6]], i32 1)35; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 036; CHECK-NEXT: br i1 [[TMP13]], label %[[VECTOR_BODY]], label %[[MIDDLE_BLOCK:.*]]37; CHECK: [[MIDDLE_BLOCK]]:38; CHECK-NEXT: [[TMP14:%.*]] = select <4 x i1> [[TMP8]], <4 x i32> [[TMP11]], <4 x i32> [[VEC_PHI]]39; CHECK-NEXT: [[TMP15:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP14]])40; CHECK-NEXT: br label %[[FOR_COND_CLEANUP]]41; CHECK: [[FOR_COND_CLEANUP]]:42; CHECK-NEXT: [[RES_0_LCSSA:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[TMP15]], %[[MIDDLE_BLOCK]] ]43; CHECK-NEXT: ret i32 [[RES_0_LCSSA]]44;45entry:46 %cmp8 = icmp eq i32 %N, 047 %0 = add i32 %N, 348 %1 = lshr i32 %0, 249 %2 = shl nuw i32 %1, 250 %3 = add i32 %2, -451 %4 = lshr i32 %3, 252 %5 = add nuw nsw i32 %4, 153 br i1 %cmp8, label %for.cond.cleanup, label %vector.ph54 55vector.ph: ; preds = %entry56 %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)57 br label %vector.body58 59vector.body: ; preds = %vector.body, %vector.ph60 %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]61 %lsr.iv2 = phi ptr [ %scevgep3, %vector.body ], [ %a, %vector.ph ]62 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %b, %vector.ph ]63 %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %9, %vector.body ]64 %6 = phi i32 [ %start, %vector.ph ], [ %10, %vector.body ]65 %7 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %N)66 %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv2, i32 4, <4 x i1> %7, <4 x i32> undef)67 %wide.masked.load13 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv, i32 4, <4 x i1> %7, <4 x i32> undef)68 %8 = mul nsw <4 x i32> %wide.masked.load13, %wide.masked.load69 %9 = add nsw <4 x i32> %8, %vec.phi70 %index.next = add i32 %index, 471 %scevgep = getelementptr i32, ptr %lsr.iv, i32 472 %scevgep3 = getelementptr i32, ptr %lsr.iv2, i32 473 %10 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %6, i32 1)74 %11 = icmp ne i32 %10, 075 br i1 %11, label %vector.body, label %middle.block76 77middle.block: ; preds = %vector.body78 %12 = select <4 x i1> %7, <4 x i32> %9, <4 x i32> %vec.phi79 %13 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %12)80 br label %for.cond.cleanup81 82for.cond.cleanup: ; preds = %middle.block, %entry83 %res.0.lcssa = phi i32 [ 0, %entry ], [ %13, %middle.block ]84 ret i32 %res.0.lcssa85}86 87declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>)88declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)89declare i32 @llvm.start.loop.iterations.i32(i32)90declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)91declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)92