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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s3 4--- |5 define hidden i32 @vmldava_in_vpt(ptr %input_1_vect, ptr %input_2_vect, i32 %input_1_offset, i32 %input_2_offset, i32 %out_offset, i32 %out_mult, i32 %out_shift, i32 %out_activation_min, i32 %out_activation_max, i32 %block_size) local_unnamed_addr #0 {6 entry:7 %add = add i32 %block_size, 38 %div = lshr i32 %add, 29 %0 = call { i32, i1 } @llvm.test.start.loop.iterations.i32(i32 %div)10 %wls0 = extractvalue { i32, i1 } %0, 011 %wls1 = extractvalue { i32, i1 } %0, 112 br i1 %wls1, label %for.body.lr.ph, label %for.cond.cleanup13 14 for.body.lr.ph: ; preds = %entry15 %.splatinsert.i41 = insertelement <4 x i32> undef, i32 %out_activation_min, i32 016 %.splat.i42 = shufflevector <4 x i32> %.splatinsert.i41, <4 x i32> undef, <4 x i32> zeroinitializer17 %.splatinsert.i = insertelement <4 x i32> undef, i32 %out_activation_max, i32 018 %.splat.i = shufflevector <4 x i32> %.splatinsert.i, <4 x i32> undef, <4 x i32> zeroinitializer19 br label %for.body20 21 for.cond.cleanup: ; preds = %for.body, %entry22 %res = phi i32 [ 0, %entry ], [ %acc.next, %for.body ]23 ret i32 %res24 25 for.body: ; preds = %for.body, %for.body.lr.ph26 %lsr.iv = phi i32 [ %iv.next, %for.body ], [ %wls0, %for.body.lr.ph ]27 %input_1_vect.addr.052 = phi ptr [ %input_1_vect, %for.body.lr.ph ], [ %add.ptr, %for.body ]28 %input_2_vect.addr.051 = phi ptr [ %input_2_vect, %for.body.lr.ph ], [ %add.ptr14, %for.body ]29 %num_elements.049 = phi i32 [ %block_size, %for.body.lr.ph ], [ %sub, %for.body ]30 %acc = phi i32 [ 0, %for.body.lr.ph ], [ %acc.next, %for.body ]31 %input_2_cast = bitcast ptr %input_2_vect.addr.051 to ptr32 %input_1_cast = bitcast ptr %input_1_vect.addr.052 to ptr33 %pred = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %num_elements.049)34 %load.1 = tail call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %input_1_cast, i32 4, <4 x i1> %pred, <4 x i32> undef)35 %insert.input_1_offset = insertelement <4 x i32> undef, i32 %input_1_offset, i32 036 %splat.input_1_offset = shufflevector <4 x i32> %insert.input_1_offset, <4 x i32> undef, <4 x i32> zeroinitializer37 %insert.input_2_offset = insertelement <4 x i32> undef, i32 %input_2_offset, i32 038 %splat.input_2_offset = shufflevector <4 x i32> %insert.input_2_offset, <4 x i32> undef, <4 x i32> zeroinitializer39 %add.1 = add <4 x i32> %load.1, %splat.input_1_offset40 %load.2 = tail call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %input_2_cast, i32 4, <4 x i1> %pred, <4 x i32> undef)41 %add.2 = add <4 x i32> %load.2, %splat.input_2_offset42 %mul = mul <4 x i32> %add.1, %add.243 %insert.output = insertelement <4 x i32> undef, i32 %out_offset, i32 044 %splat.output = shufflevector <4 x i32> %insert.output, <4 x i32> undef, <4 x i32> zeroinitializer45 %add7 = add <4 x i32> %mul, %splat.output46 %max = tail call <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32> %add7, <4 x i32> %.splat.i42, i32 1, <4 x i1> %pred, <4 x i32> undef)47 %min = tail call <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32> %max, <4 x i32> %.splat.i, i32 1, <4 x i1> %pred, <4 x i32> undef)48 %acc.next = call i32 @llvm.arm.mve.vmldava.predicated.v4i32.v4i1(i32 0, i32 0, i32 0, i32 %acc, <4 x i32> %min, <4 x i32> %max, <4 x i1> %pred)49 %add.ptr = getelementptr inbounds i8, ptr %input_1_vect.addr.052, i32 450 %add.ptr14 = getelementptr inbounds i8, ptr %input_2_vect.addr.051, i32 451 %sub = add i32 %num_elements.049, -452 %iv.next = call i32 @llvm.loop.decrement.reg.i32(i32 %lsr.iv, i32 1)53 %cmp = icmp ne i32 %iv.next, 054 br i1 %cmp, label %for.body, label %for.cond.cleanup55 }56 declare <4 x i1> @llvm.arm.mve.vctp32(i32) #157 declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>) #258 declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr, i32 immarg, <4 x i1>) #359 declare <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #160 declare <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #161 declare i32 @llvm.arm.mve.vmldava.predicated.v4i32.v4i1(i32, i32, i32, i32, <4 x i32>, <4 x i32>, <4 x i1>) #162 declare { i32, i1 } @llvm.test.start.loop.iterations.i32(i32) #463 declare i32 @llvm.loop.decrement.reg.i32(i32, i32) #464...65---66name: vmldava_in_vpt67alignment: 268exposesReturnsTwice: false69legalized: false70regBankSelected: false71selected: false72failedISel: false73tracksRegLiveness: true74hasWinCFI: false75registers: []76liveins:77 - { reg: '$r0', virtual-reg: '' }78 - { reg: '$r1', virtual-reg: '' }79 - { reg: '$r2', virtual-reg: '' }80 - { reg: '$r3', virtual-reg: '' }81frameInfo:82 isFrameAddressTaken: false83 isReturnAddressTaken: false84 hasStackMap: false85 hasPatchPoint: false86 stackSize: 1687 offsetAdjustment: 088 maxAlignment: 489 adjustsStack: false90 hasCalls: false91 stackProtector: ''92 maxCallFrameSize: 093 cvBytesOfCalleeSavedRegisters: 094 hasOpaqueSPAdjustment: false95 hasVAStart: false96 hasMustTailInVarArgFunc: false97 localFrameSize: 098 savePoint: []99 restorePoint: []100fixedStack:101 - { id: 0, type: default, offset: 20, size: 4, alignment: 4, stack-id: default,102 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,103 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }104 - { id: 1, type: default, offset: 16, size: 4, alignment: 8, stack-id: default,105 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,106 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }107 - { id: 2, type: default, offset: 12, size: 4, alignment: 4, stack-id: default,108 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,109 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }110 - { id: 3, type: default, offset: 8, size: 4, alignment: 8, stack-id: default,111 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,112 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }113 - { id: 4, type: default, offset: 4, size: 4, alignment: 4, stack-id: default,114 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,115 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }116 - { id: 5, type: default, offset: 0, size: 4, alignment: 8, stack-id: default,117 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,118 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }119stack:120 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,121 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,122 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }123 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,124 stack-id: default, callee-saved-register: '$r6', callee-saved-restored: true,125 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }126 - { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,127 stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true,128 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }129 - { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,130 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,131 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }132callSites: []133debugValueSubstitutions: []134constants: []135machineFunctionInfo: {}136body: |137 ; CHECK-LABEL: name: vmldava_in_vpt138 ; CHECK: bb.0.entry:139 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000)140 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6141 ; CHECK-NEXT: {{ $}}142 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp143 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16144 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4145 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r6, -8146 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -12147 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -16148 ; CHECK-NEXT: renamable $r4 = tLDRspi $sp, 9, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.5)149 ; CHECK-NEXT: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg150 ; CHECK-NEXT: $lr = MVE_WLSTP_32 killed renamable $r4, %bb.3151 ; CHECK-NEXT: {{ $}}152 ; CHECK-NEXT: bb.1.for.body.lr.ph:153 ; CHECK-NEXT: successors: %bb.2(0x80000000)154 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3155 ; CHECK-NEXT: {{ $}}156 ; CHECK-NEXT: renamable $r5 = tLDRspi $sp, 4, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)157 ; CHECK-NEXT: $r6, $r12 = t2LDRDi8 $sp, 28, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.3), (load (s32) from %fixed-stack.4, align 8)158 ; CHECK-NEXT: renamable $q0 = MVE_VDUP32 killed renamable $r12, 0, $noreg, $noreg, undef renamable $q0159 ; CHECK-NEXT: renamable $q1 = MVE_VDUP32 killed renamable $r6, 0, $noreg, $noreg, undef renamable $q1160 ; CHECK-NEXT: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg161 ; CHECK-NEXT: {{ $}}162 ; CHECK-NEXT: bb.2.for.body:163 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)164 ; CHECK-NEXT: liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3, $r5, $r12165 ; CHECK-NEXT: {{ $}}166 ; CHECK-NEXT: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 4, 0, $noreg, $noreg :: (load (s128) from %ir.input_2_cast, align 4)167 ; CHECK-NEXT: renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 4, 0, $noreg, $noreg :: (load (s128) from %ir.input_1_cast, align 4)168 ; CHECK-NEXT: renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r3, 0, $noreg, $noreg, undef renamable $q2169 ; CHECK-NEXT: renamable $q3 = MVE_VADD_qr_i32 killed renamable $q3, renamable $r2, 0, $noreg, $noreg, undef renamable $q3170 ; CHECK-NEXT: renamable $q3 = MVE_VMLAS_qr_i32 killed renamable $q3, killed renamable $q2, renamable $r5, 0, $noreg, $noreg171 ; CHECK-NEXT: renamable $q2 = MVE_VMAXu32 killed renamable $q3, renamable $q1, 0, $noreg, $noreg, undef renamable $q2172 ; CHECK-NEXT: renamable $q3 = MVE_VMINu32 renamable $q2, renamable $q0, 0, $noreg, $noreg, undef renamable $q3173 ; CHECK-NEXT: renamable $r12 = MVE_VMLADAVas32 killed renamable $r12, killed renamable $q3, killed renamable $q2, 0, killed $noreg, $noreg174 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2175 ; CHECK-NEXT: {{ $}}176 ; CHECK-NEXT: bb.3.for.cond.cleanup:177 ; CHECK-NEXT: liveins: $r12178 ; CHECK-NEXT: {{ $}}179 ; CHECK-NEXT: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg180 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $pc, implicit killed $r0181 bb.0.entry:182 successors: %bb.1(0x40000000), %bb.3(0x40000000)183 liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr184 185 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp186 frame-setup CFI_INSTRUCTION def_cfa_offset 16187 frame-setup CFI_INSTRUCTION offset $lr, -4188 frame-setup CFI_INSTRUCTION offset $r6, -8189 frame-setup CFI_INSTRUCTION offset $r5, -12190 frame-setup CFI_INSTRUCTION offset $r4, -16191 renamable $r4 = tLDRspi $sp, 9, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0)192 renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg193 renamable $r5, dead $cpsr = tADDi3 renamable $r4, 3, 14 /* CC::al */, $noreg194 renamable $r5, dead $cpsr = tLSRri killed renamable $r5, 2, 14 /* CC::al */, $noreg195 renamable $lr = t2WhileLoopStartLR killed renamable $r5, %bb.3, implicit-def dead $cpsr196 tB %bb.1, 14 /* CC::al */, $noreg197 198 bb.1.for.body.lr.ph:199 successors: %bb.2(0x80000000)200 liveins: $lr, $r0, $r1, $r2, $r3, $r4201 202 renamable $r5 = tLDRspi $sp, 4, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.5, align 8)203 $r6, $r12 = t2LDRDi8 $sp, 28, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.2), (load (s32) from %fixed-stack.1, align 8)204 renamable $q0 = MVE_VDUP32 killed renamable $r12, 0, $noreg, $noreg, undef renamable $q0205 renamable $q1 = MVE_VDUP32 killed renamable $r6, 0, $noreg, $noreg, undef renamable $q1206 renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg207 208 bb.2.for.body:209 successors: %bb.2(0x7c000000), %bb.3(0x04000000)210 liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5, $r12211 212 renamable $vpr = MVE_VCTP32 renamable $r4, 0, $noreg, $noreg213 MVE_VPST 8, implicit $vpr214 renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 4, 1, renamable $vpr, $noreg :: (load (s128) from %ir.input_2_cast, align 4)215 MVE_VPST 8, implicit $vpr216 renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 4, 1, renamable $vpr, $noreg :: (load (s128) from %ir.input_1_cast, align 4)217 renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r3, 0, $noreg, $noreg, undef renamable $q2218 renamable $q3 = MVE_VADD_qr_i32 killed renamable $q3, renamable $r2, 0, $noreg, $noreg, undef renamable $q3219 renamable $r4, dead $cpsr = tSUBi8 killed renamable $r4, 4, 14 /* CC::al */, $noreg220 renamable $q3 = MVE_VMLAS_qr_i32 killed renamable $q3, killed renamable $q2, renamable $r5, 0, $noreg, $noreg221 MVE_VPST 2, implicit $vpr222 renamable $q2 = MVE_VMAXu32 killed renamable $q3, renamable $q1, 1, renamable $vpr, $noreg, undef renamable $q2223 renamable $q3 = MVE_VMINu32 renamable $q2, renamable $q0, 1, renamable $vpr, $noreg, undef renamable $q3224 renamable $r12 = MVE_VMLADAVas32 killed renamable $r12, killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, $noreg225 renamable $lr = t2LoopEndDec killed renamable $lr, %bb.2, implicit-def dead $cpsr226 tB %bb.3, 14 /* CC::al */, $noreg227 228 bb.3.for.cond.cleanup:229 liveins: $r12230 231 $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg232 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $pc, implicit killed $r0233 234...235