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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s3 4--- |5 @_ZL3arr = internal global [10 x i32] [i32 1, i32 2, i32 3, i32 5, i32 5, i32 5, i32 -2, i32 0, i32 -8, i32 -1], align 46 @.str = private unnamed_addr constant [5 x i8] c"%d, \00", align 17 8 define arm_aapcs_vfpcc void @vpt_block(ptr nocapture %A, i32 %n, i32 %x) {9 entry:10 %cmp9 = icmp sgt i32 %n, 011 %0 = add i32 %n, 312 %1 = lshr i32 %0, 213 %2 = shl nuw i32 %1, 214 %3 = add i32 %2, -415 %4 = lshr i32 %3, 216 %5 = add nuw nsw i32 %4, 117 br i1 %cmp9, label %vector.ph, label %for.cond.cleanup18 19 vector.ph: ; preds = %entry20 %sub = sub nsw i32 0, %x21 %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)22 br label %vector.body23 24 vector.body: ; preds = %vector.body, %vector.ph25 %lsr.iv1 = phi ptr [ %scevgep, %vector.body ], [ %A, %vector.ph ]26 %6 = phi i32 [ %start, %vector.ph ], [ %18, %vector.body ]27 %7 = phi i32 [ %n, %vector.ph ], [ %9, %vector.body ]28 %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7)29 %9 = sub i32 %7, 430 %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv1, i32 4, <4 x i1> %8, <4 x i32> undef)31 %10 = insertelement <4 x i32> undef, i32 %x, i32 032 %11 = shufflevector <4 x i32> %10, <4 x i32> undef, <4 x i32> zeroinitializer33 %12 = icmp slt <4 x i32> %wide.masked.load, %1134 %13 = insertelement <4 x i32> undef, i32 %sub, i32 035 %14 = shufflevector <4 x i32> %13, <4 x i32> undef, <4 x i32> zeroinitializer36 %15 = icmp sgt <4 x i32> %wide.masked.load, %1437 %16 = and <4 x i1> %12, %1538 %17 = and <4 x i1> %16, %839 call void @llvm.masked.store.v4i32.p0(<4 x i32> zeroinitializer, ptr %lsr.iv1, i32 4, <4 x i1> %17)40 %scevgep = getelementptr i32, ptr %lsr.iv1, i32 441 %18 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %6, i32 1)42 %19 = icmp ne i32 %18, 043 br i1 %19, label %vector.body, label %for.cond.cleanup44 45 for.cond.cleanup: ; preds = %vector.body, %entry46 ret void47 }48 49 define arm_aapcs_vfpcc void @different_vcpt_reaching_def(ptr nocapture %A, i32 %n, i32 %x) {50 ; Intentionally left blank - see MIR sequence below.51 entry:52 unreachable53 vector.ph:54 unreachable55 vector.body:56 unreachable57 for.cond.cleanup:58 unreachable59 }60 61 define arm_aapcs_vfpcc void @different_vcpt_operand(ptr nocapture %A, i32 %n, i32 %x) {62 ; Intentionally left blank - see MIR sequence below.63 entry:64 unreachable65 vector.ph:66 unreachable67 vector.body:68 unreachable69 for.cond.cleanup:70 unreachable71 }72 73 define arm_aapcs_vfpcc void @else_vcpt(ptr nocapture %data, i32 %N, i32 %T) {74 entry:75 %cmp9 = icmp sgt i32 %N, 076 %0 = add i32 %N, 377 %1 = lshr i32 %0, 278 %2 = shl nuw i32 %1, 279 %3 = add i32 %2, -480 %4 = lshr i32 %3, 281 %5 = add nuw nsw i32 %4, 182 br i1 %cmp9, label %vector.ph, label %for.cond.cleanup83 84 vector.ph: ; preds = %entry85 %sub = sub nsw i32 0, %T86 %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)87 br label %vector.body88 89 vector.body: ; preds = %vector.body, %vector.ph90 %lsr.iv1 = phi ptr [ %scevgep, %vector.body ], [ %data, %vector.ph ]91 %6 = phi i32 [ %start, %vector.ph ], [ %18, %vector.body ]92 %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ]93 %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7)94 %9 = sub i32 %7, 495 %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv1, i32 4, <4 x i1> %8, <4 x i32> undef)96 %10 = insertelement <4 x i32> undef, i32 %T, i32 097 %11 = shufflevector <4 x i32> %10, <4 x i32> undef, <4 x i32> zeroinitializer98 %12 = icmp slt <4 x i32> %wide.masked.load, %1199 %13 = insertelement <4 x i32> undef, i32 %sub, i32 0100 %14 = shufflevector <4 x i32> %13, <4 x i32> undef, <4 x i32> zeroinitializer101 %15 = icmp sgt <4 x i32> %wide.masked.load, %14102 %16 = or <4 x i1> %12, %15103 %17 = and <4 x i1> %16, %8104 call void @llvm.masked.store.v4i32.p0(<4 x i32> zeroinitializer, ptr %lsr.iv1, i32 4, <4 x i1> %17)105 %scevgep = getelementptr i32, ptr %lsr.iv1, i32 4106 %18 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %6, i32 1)107 %19 = icmp ne i32 %18, 0108 br i1 %19, label %vector.body, label %for.cond.cleanup109 110 for.cond.cleanup: ; preds = %vector.body, %entry111 ret void112 }113 114 define arm_aapcs_vfpcc void @loop_invariant_vpt_operands(ptr nocapture %A, i32 %n, i32 %x) {115 ; Intentionally left blank - see MIR sequence below.116 entry:117 unreachable118 vector.ph:119 unreachable120 vector.body:121 unreachable122 for.cond.cleanup:123 unreachable124 }125 126 define arm_aapcs_vfpcc void @vctp_before_vpt(ptr nocapture %A, i32 %n, i32 %x) {127 ; Intentionally left blank - see MIR sequence below.128 entry:129 unreachable130 vector.ph:131 unreachable132 vector.body:133 unreachable134 for.cond.cleanup:135 unreachable136 }137 138 define arm_aapcs_vfpcc void @vpt_load_vctp_store(ptr nocapture %A, i32 %n, i32 %x) {139 ; Intentionally left blank - see MIR sequence below.140 entry:141 unreachable142 vector.ph:143 unreachable144 vector.body:145 unreachable146 for.cond.cleanup:147 unreachable148 }149 150 define arm_aapcs_vfpcc void @emptyblock() {151 unreachable152 }153 define arm_aapcs_vfpcc void @predvcmp() {154 unreachable155 }156 define arm_aapcs_vfpcc void @predvpt() {157 unreachable158 }159 160 declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>)161 declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr, i32 immarg, <4 x i1>)162 declare i32 @llvm.start.loop.iterations.i32(i32)163 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)164 declare <4 x i1> @llvm.arm.mve.vctp32(i32)165...166---167name: vpt_block168alignment: 2169exposesReturnsTwice: false170legalized: false171regBankSelected: false172selected: false173failedISel: false174tracksRegLiveness: true175hasWinCFI: false176registers: []177liveins:178 - { reg: '$r0', virtual-reg: '' }179 - { reg: '$r1', virtual-reg: '' }180 - { reg: '$r2', virtual-reg: '' }181frameInfo:182 isFrameAddressTaken: false183 isReturnAddressTaken: false184 hasStackMap: false185 hasPatchPoint: false186 stackSize: 8187 offsetAdjustment: 0188 maxAlignment: 4189 adjustsStack: false190 hasCalls: false191 stackProtector: ''192 maxCallFrameSize: 0193 cvBytesOfCalleeSavedRegisters: 0194 hasOpaqueSPAdjustment: false195 hasVAStart: false196 hasMustTailInVarArgFunc: false197 localFrameSize: 0198 savePoint: []199 restorePoint: []200fixedStack: []201stack:202 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,203 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,204 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }205 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,206 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,207 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }208callSites: []209constants: []210machineFunctionInfo: {}211body: |212 ; CHECK-LABEL: name: vpt_block213 ; CHECK: bb.0.entry:214 ; CHECK-NEXT: successors: %bb.1(0x80000000)215 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7216 ; CHECK-NEXT: {{ $}}217 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp218 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8219 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4220 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8221 ; CHECK-NEXT: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr222 ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate223 ; CHECK-NEXT: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate224 ; CHECK-NEXT: {{ $}}225 ; CHECK-NEXT: bb.1.vector.ph:226 ; CHECK-NEXT: successors: %bb.2(0x80000000)227 ; CHECK-NEXT: liveins: $r0, $r1, $r2228 ; CHECK-NEXT: {{ $}}229 ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0230 ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg231 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r1232 ; CHECK-NEXT: {{ $}}233 ; CHECK-NEXT: bb.2.vector.body:234 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)235 ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r2, $r3236 ; CHECK-NEXT: {{ $}}237 ; CHECK-NEXT: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 0, killed $noreg, $noreg238 ; CHECK-NEXT: MVE_VPTv4s32r 4, renamable $q1, renamable $r2, 11, implicit-def $vpr239 ; CHECK-NEXT: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr, $noreg240 ; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg241 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2242 ; CHECK-NEXT: {{ $}}243 ; CHECK-NEXT: bb.3.for.cond.cleanup:244 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc245 bb.0.entry:246 successors: %bb.1(0x80000000)247 liveins: $r0, $r1, $r2, $r7, $lr248 249 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp250 frame-setup CFI_INSTRUCTION def_cfa_offset 8251 frame-setup CFI_INSTRUCTION offset $lr, -4252 frame-setup CFI_INSTRUCTION offset $r7, -8253 tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr254 t2IT 11, 8, implicit-def $itstate255 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate256 257 bb.1.vector.ph:258 successors: %bb.2(0x80000000)259 liveins: $r0, $r1, $r2, $r7, $lr260 261 renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg262 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0263 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg264 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg265 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg266 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg267 renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg268 $lr = t2DoLoopStart renamable $lr269 270 bb.2.vector.body:271 successors: %bb.2(0x7c000000), %bb.3(0x04000000)272 liveins: $lr, $q0, $r0, $r1, $r2, $r3273 274 renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg275 MVE_VPST 8, implicit $vpr276 renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr, $noreg277 MVE_VPTv4s32r 2, renamable $q1, renamable $r2, 11, implicit-def $vpr278 renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr, $noreg279 renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed renamable $vpr, $noreg280 renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg281 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg282 renamable $lr = t2LoopDec killed renamable $lr, 1283 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr284 tB %bb.3, 14 /* CC::al */, $noreg285 286 bb.3.for.cond.cleanup:287 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc288...289# Tests that secondary VCTPs are refused when their operand's reaching definition is not the same as the main290# VCTP's.291---292name: different_vcpt_reaching_def293alignment: 2294exposesReturnsTwice: false295legalized: false296regBankSelected: false297selected: false298failedISel: false299tracksRegLiveness: true300hasWinCFI: false301registers: []302liveins:303 - { reg: '$r0', virtual-reg: '' }304 - { reg: '$r1', virtual-reg: '' }305 - { reg: '$r2', virtual-reg: '' }306frameInfo:307 isFrameAddressTaken: false308 isReturnAddressTaken: false309 hasStackMap: false310 hasPatchPoint: false311 stackSize: 8312 offsetAdjustment: 0313 maxAlignment: 4314 adjustsStack: false315 hasCalls: false316 stackProtector: ''317 maxCallFrameSize: 0318 cvBytesOfCalleeSavedRegisters: 0319 hasOpaqueSPAdjustment: false320 hasVAStart: false321 hasMustTailInVarArgFunc: false322 localFrameSize: 0323 savePoint: []324 restorePoint: []325fixedStack: []326stack:327 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,328 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,329 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }330 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,331 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,332 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }333callSites: []334constants: []335machineFunctionInfo: {}336body: |337 ; CHECK-LABEL: name: different_vcpt_reaching_def338 ; CHECK: bb.0.entry:339 ; CHECK-NEXT: successors: %bb.1(0x80000000)340 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7341 ; CHECK-NEXT: {{ $}}342 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp343 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8344 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4345 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8346 ; CHECK-NEXT: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr347 ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate348 ; CHECK-NEXT: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate349 ; CHECK-NEXT: {{ $}}350 ; CHECK-NEXT: bb.1.vector.ph:351 ; CHECK-NEXT: successors: %bb.2(0x80000000)352 ; CHECK-NEXT: liveins: $r0, $r1, $r2353 ; CHECK-NEXT: {{ $}}354 ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg355 ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0356 ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg357 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg358 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg359 ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg360 ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg361 ; CHECK-NEXT: {{ $}}362 ; CHECK-NEXT: bb.2.vector.body:363 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)364 ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1, $r2, $r3365 ; CHECK-NEXT: {{ $}}366 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg367 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr368 ; CHECK-NEXT: renamable $r1 = MVE_VSTRWU32_post renamable $q0, killed renamable $r1, 16, 1, renamable $vpr, $noreg369 ; CHECK-NEXT: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr, $noreg370 ; CHECK-NEXT: MVE_VPTv4s32r 2, renamable $q1, renamable $r2, 11, implicit-def $vpr371 ; CHECK-NEXT: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr, $noreg372 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed renamable $vpr, $noreg373 ; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg374 ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg375 ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2376 ; CHECK-NEXT: {{ $}}377 ; CHECK-NEXT: bb.3.for.cond.cleanup:378 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc379 bb.0.entry:380 successors: %bb.1(0x80000000)381 liveins: $r0, $r1, $r2, $r7, $lr382 383 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp384 frame-setup CFI_INSTRUCTION def_cfa_offset 8385 frame-setup CFI_INSTRUCTION offset $lr, -4386 frame-setup CFI_INSTRUCTION offset $r7, -8387 tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr388 t2IT 11, 8, implicit-def $itstate389 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate390 391 bb.1.vector.ph:392 successors: %bb.2(0x80000000)393 liveins: $r0, $r1, $r2, $r7, $lr394 395 renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg396 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0397 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg398 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg399 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg400 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg401 renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg402 $lr = t2DoLoopStart renamable $lr403 404 bb.2.vector.body:405 successors: %bb.2(0x7c000000), %bb.3(0x04000000)406 liveins: $lr, $q0, $r0, $r1, $r2, $r3407 408 renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg409 MVE_VPST 8, implicit $vpr410 renamable $r1 = MVE_VSTRWU32_post renamable $q0, killed renamable $r1, 16, 1, renamable $vpr, $noreg411 renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr, $noreg412 MVE_VPTv4s32r 2, renamable $q1, renamable $r2, 11, implicit-def $vpr413 renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr, $noreg414 renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed renamable $vpr, $noreg415 renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg416 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg417 renamable $lr = t2LoopDec killed renamable $lr, 1418 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr419 tB %bb.3, 14 /* CC::al */, $noreg420 421 bb.3.for.cond.cleanup:422 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc423...424# Tests that secondary VCTPs are refused when their operand is not the same register as the main VCTP's.425---426name: different_vcpt_operand427alignment: 2428exposesReturnsTwice: false429legalized: false430regBankSelected: false431selected: false432failedISel: false433tracksRegLiveness: true434hasWinCFI: false435registers: []436liveins:437 - { reg: '$r0', virtual-reg: '' }438 - { reg: '$r1', virtual-reg: '' }439 - { reg: '$r2', virtual-reg: '' }440frameInfo:441 isFrameAddressTaken: false442 isReturnAddressTaken: false443 hasStackMap: false444 hasPatchPoint: false445 stackSize: 8446 offsetAdjustment: 0447 maxAlignment: 4448 adjustsStack: false449 hasCalls: false450 stackProtector: ''451 maxCallFrameSize: 0452 cvBytesOfCalleeSavedRegisters: 0453 hasOpaqueSPAdjustment: false454 hasVAStart: false455 hasMustTailInVarArgFunc: false456 localFrameSize: 0457 savePoint: []458 restorePoint: []459fixedStack: []460stack:461 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,462 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,463 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }464 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,465 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,466 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }467callSites: []468constants: []469machineFunctionInfo: {}470body: |471 ; CHECK-LABEL: name: different_vcpt_operand472 ; CHECK: bb.0.entry:473 ; CHECK-NEXT: successors: %bb.1(0x80000000)474 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7475 ; CHECK-NEXT: {{ $}}476 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp477 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8478 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4479 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8480 ; CHECK-NEXT: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr481 ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate482 ; CHECK-NEXT: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate483 ; CHECK-NEXT: {{ $}}484 ; CHECK-NEXT: bb.1.vector.ph:485 ; CHECK-NEXT: successors: %bb.2(0x80000000)486 ; CHECK-NEXT: liveins: $r0, $r1, $r2487 ; CHECK-NEXT: {{ $}}488 ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg489 ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0490 ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg491 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg492 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg493 ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg494 ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg495 ; CHECK-NEXT: {{ $}}496 ; CHECK-NEXT: bb.2.vector.body:497 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)498 ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1, $r2, $r3499 ; CHECK-NEXT: {{ $}}500 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg501 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr502 ; CHECK-NEXT: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr, $noreg503 ; CHECK-NEXT: MVE_VPTv4s32r 2, renamable $q1, renamable $r2, 11, implicit-def $vpr504 ; CHECK-NEXT: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr, $noreg505 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg506 ; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg507 ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg508 ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2509 ; CHECK-NEXT: {{ $}}510 ; CHECK-NEXT: bb.3.for.cond.cleanup:511 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc512 bb.0.entry:513 successors: %bb.1(0x80000000)514 liveins: $r0, $r1, $r2, $r7, $lr515 516 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp517 frame-setup CFI_INSTRUCTION def_cfa_offset 8518 frame-setup CFI_INSTRUCTION offset $lr, -4519 frame-setup CFI_INSTRUCTION offset $r7, -8520 tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr521 t2IT 11, 8, implicit-def $itstate522 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate523 524 bb.1.vector.ph:525 successors: %bb.2(0x80000000)526 liveins: $r0, $r1, $r2, $r7, $lr527 528 renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg529 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0530 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg531 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg532 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg533 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg534 renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg535 $lr = t2DoLoopStart renamable $lr536 537 bb.2.vector.body:538 successors: %bb.2(0x7c000000), %bb.3(0x04000000)539 liveins: $lr, $q0, $r0, $r1, $r2, $r3540 541 renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg542 MVE_VPST 8, implicit $vpr543 renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr, $noreg544 MVE_VPTv4s32r 2, renamable $q1, renamable $r2, 11, implicit-def $vpr545 renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr, $noreg546 renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg547 renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg548 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg549 renamable $lr = t2LoopDec killed renamable $lr, 1550 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr551 tB %bb.3, 14 /* CC::al */, $noreg552 553 bb.3.for.cond.cleanup:554 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc555...556# Test including a else-predicated VCTP.557---558name: else_vcpt559alignment: 2560exposesReturnsTwice: false561legalized: false562regBankSelected: false563selected: false564failedISel: false565tracksRegLiveness: true566hasWinCFI: false567registers: []568liveins:569 - { reg: '$r0', virtual-reg: '' }570 - { reg: '$r1', virtual-reg: '' }571 - { reg: '$r2', virtual-reg: '' }572frameInfo:573 isFrameAddressTaken: false574 isReturnAddressTaken: false575 hasStackMap: false576 hasPatchPoint: false577 stackSize: 8578 offsetAdjustment: 0579 maxAlignment: 4580 adjustsStack: false581 hasCalls: false582 stackProtector: ''583 maxCallFrameSize: 0584 cvBytesOfCalleeSavedRegisters: 0585 hasOpaqueSPAdjustment: false586 hasVAStart: false587 hasMustTailInVarArgFunc: false588 localFrameSize: 0589 savePoint: []590 restorePoint: []591fixedStack: []592stack:593 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,594 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,595 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }596 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,597 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,598 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }599callSites: []600constants: []601machineFunctionInfo: {}602body: |603 ; CHECK-LABEL: name: else_vcpt604 ; CHECK: bb.0.entry:605 ; CHECK-NEXT: successors: %bb.1(0x80000000)606 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7607 ; CHECK-NEXT: {{ $}}608 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp609 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8610 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4611 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8612 ; CHECK-NEXT: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr613 ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate614 ; CHECK-NEXT: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate615 ; CHECK-NEXT: {{ $}}616 ; CHECK-NEXT: bb.1.vector.ph:617 ; CHECK-NEXT: successors: %bb.2(0x80000000)618 ; CHECK-NEXT: liveins: $r0, $r1, $r2619 ; CHECK-NEXT: {{ $}}620 ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0621 ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg622 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r1623 ; CHECK-NEXT: {{ $}}624 ; CHECK-NEXT: bb.2.vector.body:625 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)626 ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r2, $r3627 ; CHECK-NEXT: {{ $}}628 ; CHECK-NEXT: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 0, killed $noreg, $noreg629 ; CHECK-NEXT: MVE_VPTv4s32r 12, renamable $q1, renamable $r2, 10, implicit-def $vpr630 ; CHECK-NEXT: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 13, 1, killed renamable $vpr, $noreg631 ; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 2, killed renamable $vpr, $noreg632 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2633 ; CHECK-NEXT: {{ $}}634 ; CHECK-NEXT: bb.3.for.cond.cleanup:635 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc636 bb.0.entry:637 successors: %bb.1(0x80000000)638 liveins: $r0, $r1, $r2, $r7, $lr639 640 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp641 frame-setup CFI_INSTRUCTION def_cfa_offset 8642 frame-setup CFI_INSTRUCTION offset $lr, -4643 frame-setup CFI_INSTRUCTION offset $r7, -8644 tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr645 t2IT 11, 8, implicit-def $itstate646 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate647 648 bb.1.vector.ph:649 successors: %bb.2(0x80000000)650 liveins: $r0, $r1, $r2, $r7, $lr651 652 renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg653 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0654 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg655 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg656 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg657 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg658 renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg659 $lr = t2DoLoopStart renamable $lr660 661 bb.2.vector.body:662 successors: %bb.2(0x7c000000), %bb.3(0x04000000)663 liveins: $lr, $q0, $r0, $r1, $r2, $r3664 665 renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg666 MVE_VPST 8, implicit $vpr667 renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr, $noreg668 MVE_VPTv4s32r 14, renamable $q1, renamable $r2, 10, implicit-def $vpr669 renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 13, 1, killed renamable $vpr, $noreg670 renamable $vpr = MVE_VCTP32 renamable $r1, 2, killed renamable $vpr, $noreg671 renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 2, killed renamable $vpr, $noreg672 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg673 renamable $lr = t2LoopDec killed renamable $lr, 1674 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr675 tB %bb.3, 14 /* CC::al */, $noreg676 677 bb.3.for.cond.cleanup:678 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc679...680---681name: loop_invariant_vpt_operands682alignment: 2683exposesReturnsTwice: false684legalized: false685regBankSelected: false686selected: false687failedISel: false688tracksRegLiveness: true689hasWinCFI: false690registers: []691liveins:692 - { reg: '$r0', virtual-reg: '' }693 - { reg: '$r1', virtual-reg: '' }694 - { reg: '$r2', virtual-reg: '' }695frameInfo:696 isFrameAddressTaken: false697 isReturnAddressTaken: false698 hasStackMap: false699 hasPatchPoint: false700 stackSize: 8701 offsetAdjustment: 0702 maxAlignment: 4703 adjustsStack: false704 hasCalls: false705 stackProtector: ''706 maxCallFrameSize: 0707 cvBytesOfCalleeSavedRegisters: 0708 hasOpaqueSPAdjustment: false709 hasVAStart: false710 hasMustTailInVarArgFunc: false711 localFrameSize: 0712 savePoint: []713 restorePoint: []714fixedStack: []715stack:716 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,717 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,718 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }719 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,720 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,721 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }722callSites: []723constants: []724machineFunctionInfo: {}725body: |726 ; CHECK-LABEL: name: loop_invariant_vpt_operands727 ; CHECK: bb.0.entry:728 ; CHECK-NEXT: successors: %bb.1(0x80000000)729 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7730 ; CHECK-NEXT: {{ $}}731 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp732 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8733 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4734 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8735 ; CHECK-NEXT: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr736 ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate737 ; CHECK-NEXT: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate738 ; CHECK-NEXT: {{ $}}739 ; CHECK-NEXT: bb.1.vector.ph:740 ; CHECK-NEXT: successors: %bb.2(0x80000000)741 ; CHECK-NEXT: liveins: $r0, $r1, $r2742 ; CHECK-NEXT: {{ $}}743 ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0744 ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg745 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r1746 ; CHECK-NEXT: {{ $}}747 ; CHECK-NEXT: bb.2.vector.body:748 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)749 ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r2, $r3750 ; CHECK-NEXT: {{ $}}751 ; CHECK-NEXT: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 0, killed $noreg, $noreg752 ; CHECK-NEXT: MVE_VPTv4s32r 4, renamable $q0, renamable $r2, 11, implicit-def $vpr753 ; CHECK-NEXT: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr, $noreg754 ; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg755 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2756 ; CHECK-NEXT: {{ $}}757 ; CHECK-NEXT: bb.3.for.cond.cleanup:758 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc759 bb.0.entry:760 successors: %bb.1(0x80000000)761 liveins: $r0, $r1, $r2, $r7, $lr762 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp763 frame-setup CFI_INSTRUCTION def_cfa_offset 8764 frame-setup CFI_INSTRUCTION offset $lr, -4765 frame-setup CFI_INSTRUCTION offset $r7, -8766 tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr767 t2IT 11, 8, implicit-def $itstate768 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate769 770 bb.1.vector.ph:771 successors: %bb.2(0x80000000)772 liveins: $r0, $r1, $r2, $r7, $lr773 774 renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg775 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0776 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg777 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg778 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg779 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg780 renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg781 $lr = t2DoLoopStart renamable $lr782 783 bb.2.vector.body:784 successors: %bb.2(0x7c000000), %bb.3(0x04000000)785 liveins: $lr, $q0, $r0, $r1, $r2, $r3786 787 renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg788 MVE_VPST 8, implicit $vpr789 renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr, $noreg790 MVE_VPTv4s32r 2, renamable $q0, renamable $r2, 11, implicit-def $vpr791 renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr, $noreg792 renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed renamable $vpr, $noreg793 renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg794 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg795 renamable $lr = t2LoopDec killed renamable $lr, 1796 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr797 tB %bb.3, 14 /* CC::al */, $noreg798 799 bb.3.for.cond.cleanup:800 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc801...802---803name: vctp_before_vpt804alignment: 2805exposesReturnsTwice: false806legalized: false807regBankSelected: false808selected: false809failedISel: false810tracksRegLiveness: true811hasWinCFI: false812registers: []813liveins:814 - { reg: '$r0', virtual-reg: '' }815 - { reg: '$r1', virtual-reg: '' }816 - { reg: '$r2', virtual-reg: '' }817frameInfo:818 isFrameAddressTaken: false819 isReturnAddressTaken: false820 hasStackMap: false821 hasPatchPoint: false822 stackSize: 8823 offsetAdjustment: 0824 maxAlignment: 4825 adjustsStack: false826 hasCalls: false827 stackProtector: ''828 maxCallFrameSize: 0829 cvBytesOfCalleeSavedRegisters: 0830 hasOpaqueSPAdjustment: false831 hasVAStart: false832 hasMustTailInVarArgFunc: false833 localFrameSize: 0834 savePoint: []835 restorePoint: []836fixedStack: []837stack:838 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,839 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,840 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }841 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,842 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,843 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }844callSites: []845constants: []846machineFunctionInfo: {}847body: |848 ; CHECK-LABEL: name: vctp_before_vpt849 ; CHECK: bb.0.entry:850 ; CHECK-NEXT: successors: %bb.1(0x80000000)851 ; CHECK-NEXT: liveins: $lr, $r1, $r2, $r7852 ; CHECK-NEXT: {{ $}}853 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp854 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8855 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4856 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8857 ; CHECK-NEXT: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr858 ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate859 ; CHECK-NEXT: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate860 ; CHECK-NEXT: {{ $}}861 ; CHECK-NEXT: bb.1.vector.ph:862 ; CHECK-NEXT: successors: %bb.2(0x80000000)863 ; CHECK-NEXT: liveins: $r1, $r2864 ; CHECK-NEXT: {{ $}}865 ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0866 ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg867 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r1868 ; CHECK-NEXT: {{ $}}869 ; CHECK-NEXT: bb.2.vector.body:870 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)871 ; CHECK-NEXT: liveins: $lr, $q0, $r2, $r3872 ; CHECK-NEXT: {{ $}}873 ; CHECK-NEXT: MVE_VPTv4s32r 8, renamable $q0, renamable $r2, 8, implicit-def $vpr874 ; CHECK-NEXT: dead renamable $vpr = MVE_VCMPs32r renamable $q0, renamable $r3, 12, 1, killed renamable $vpr, $noreg875 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2876 ; CHECK-NEXT: {{ $}}877 ; CHECK-NEXT: bb.3.for.cond.cleanup:878 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc879 bb.0.entry:880 successors: %bb.1(0x80000000)881 liveins: $r0, $r1, $r2, $r7, $lr882 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp883 frame-setup CFI_INSTRUCTION def_cfa_offset 8884 frame-setup CFI_INSTRUCTION offset $lr, -4885 frame-setup CFI_INSTRUCTION offset $r7, -8886 tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr887 t2IT 11, 8, implicit-def $itstate888 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate889 890 bb.1.vector.ph:891 successors: %bb.2(0x80000000)892 liveins: $r0, $r1, $r2, $r7, $lr893 894 renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg895 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0896 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg897 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg898 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg899 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg900 renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg901 $lr = t2DoLoopStart renamable $lr902 903 bb.2.vector.body:904 successors: %bb.2(0x7c000000), %bb.3(0x04000000)905 liveins: $lr, $q0, $r0, $r1, $r2, $r3906 907 MVE_VPTv4s32r 8, renamable $q0, renamable $r2, 8, implicit-def $vpr908 renamable $vpr = MVE_VCMPs32r killed renamable $q0, renamable $r3, 12, 1, killed renamable $vpr, $noreg909 renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg910 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg911 renamable $lr = t2LoopDec killed renamable $lr, 1912 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr913 tB %bb.3, 14 /* CC::al */, $noreg914 915 bb.3.for.cond.cleanup:916 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc917...918# This shouldn't be tail-predicated because the VLDR isn't predicated on the VCTP.919---920name: vpt_load_vctp_store921alignment: 2922exposesReturnsTwice: false923legalized: false924regBankSelected: false925selected: false926failedISel: false927tracksRegLiveness: true928hasWinCFI: false929registers: []930liveins:931 - { reg: '$r0', virtual-reg: '' }932 - { reg: '$r1', virtual-reg: '' }933 - { reg: '$r2', virtual-reg: '' }934frameInfo:935 isFrameAddressTaken: false936 isReturnAddressTaken: false937 hasStackMap: false938 hasPatchPoint: false939 stackSize: 8940 offsetAdjustment: 0941 maxAlignment: 4942 adjustsStack: false943 hasCalls: false944 stackProtector: ''945 maxCallFrameSize: 0946 cvBytesOfCalleeSavedRegisters: 0947 hasOpaqueSPAdjustment: false948 hasVAStart: false949 hasMustTailInVarArgFunc: false950 localFrameSize: 0951 savePoint: []952 restorePoint: []953fixedStack: []954stack:955 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,956 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,957 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }958 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,959 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,960 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }961callSites: []962constants: []963machineFunctionInfo: {}964body: |965 ; CHECK-LABEL: name: vpt_load_vctp_store966 ; CHECK: bb.0.entry:967 ; CHECK-NEXT: successors: %bb.1(0x80000000)968 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7969 ; CHECK-NEXT: {{ $}}970 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp971 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8972 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4973 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8974 ; CHECK-NEXT: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr975 ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate976 ; CHECK-NEXT: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate977 ; CHECK-NEXT: {{ $}}978 ; CHECK-NEXT: bb.1.vector.ph:979 ; CHECK-NEXT: successors: %bb.2(0x80000000)980 ; CHECK-NEXT: liveins: $r0, $r1, $r2981 ; CHECK-NEXT: {{ $}}982 ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg983 ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0984 ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg985 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg986 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg987 ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg988 ; CHECK-NEXT: dead renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg989 ; CHECK-NEXT: {{ $}}990 ; CHECK-NEXT: bb.2.vector.body:991 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)992 ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1, $r2993 ; CHECK-NEXT: {{ $}}994 ; CHECK-NEXT: MVE_VPTv4s32r 2, killed renamable $q0, renamable $r2, 2, implicit-def $vpr995 ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 renamable $r0, 0, 1, $vpr, $noreg996 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed $vpr, $noreg997 ; CHECK-NEXT: MVE_VSTRWU32 renamable $q0, renamable $r0, 0, 1, killed $vpr, $noreg998 ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg999 ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.21000 ; CHECK-NEXT: {{ $}}1001 ; CHECK-NEXT: bb.3.for.cond.cleanup:1002 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc1003 bb.0.entry:1004 successors: %bb.1(0x80000000)1005 liveins: $r0, $r1, $r2, $r7, $lr1006 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp1007 frame-setup CFI_INSTRUCTION def_cfa_offset 81008 frame-setup CFI_INSTRUCTION offset $lr, -41009 frame-setup CFI_INSTRUCTION offset $r7, -81010 tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr1011 t2IT 11, 8, implicit-def $itstate1012 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate1013 1014 bb.1.vector.ph:1015 successors: %bb.2(0x80000000)1016 liveins: $r0, $r1, $r2, $r7, $lr1017 1018 renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg1019 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q01020 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg1021 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg1022 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg1023 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg1024 renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg1025 $lr = t2DoLoopStart renamable $lr1026 1027 bb.2.vector.body:1028 successors: %bb.2(0x7c000000), %bb.3(0x04000000)1029 liveins: $lr, $q0, $r0, $r1, $r2, $r31030 1031 MVE_VPTv4s32r 2, renamable $q0, renamable $r2, 2, implicit-def $vpr1032 renamable $q0 = MVE_VLDRWU32 renamable $r0, 0, 1, $vpr, $noreg1033 renamable $vpr = MVE_VCTP32 renamable $r1, 1, $vpr, $noreg1034 MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, $vpr, $noreg1035 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg1036 renamable $lr = t2LoopDec killed renamable $lr, 11037 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr1038 tB %bb.3, 14 /* CC::al */, $noreg1039 1040 bb.3.for.cond.cleanup:1041 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc1042...1043---1044name: emptyblock1045tracksRegLiveness: true1046liveins:1047 - { reg: '$r0', virtual-reg: '' }1048 - { reg: '$r1', virtual-reg: '' }1049 - { reg: '$r2', virtual-reg: '' }1050stack:1051 - { id: 0, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,1052 stack-id: default, callee-saved-register: '', callee-saved-restored: true,1053 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }1054 - { id: 1, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,1055 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,1056 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }1057 - { id: 2, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,1058 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,1059 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }1060body: |1061 ; CHECK-LABEL: name: emptyblock1062 ; CHECK: bb.0:1063 ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.3(0x30000000)1064 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r71065 ; CHECK-NEXT: {{ $}}1066 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp1067 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 81068 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -41069 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -81070 ; CHECK-NEXT: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg1071 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 121072 ; CHECK-NEXT: tCMPi8 renamable $r0, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr1073 ; CHECK-NEXT: tBcc %bb.3, 11 /* CC::lt */, killed $cpsr1074 ; CHECK-NEXT: {{ $}}1075 ; CHECK-NEXT: bb.1:1076 ; CHECK-NEXT: successors: %bb.2(0x80000000)1077 ; CHECK-NEXT: liveins: $r0, $r1, $r21078 ; CHECK-NEXT: {{ $}}1079 ; CHECK-NEXT: tCMPi8 killed renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr1080 ; CHECK-NEXT: renamable $r2 = t2CSINC $zr, $zr, 0, implicit killed $cpsr1081 ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q01082 ; CHECK-NEXT: renamable $r12 = t2ANDri killed renamable $r2, 1, 14 /* CC::al */, $noreg, $noreg1083 ; CHECK-NEXT: renamable $r2 = t2RSBri killed renamable $r12, 0, 14 /* CC::al */, $noreg, $noreg1084 ; CHECK-NEXT: $vpr = VMSR_P0 killed $r2, 14 /* CC::al */, $noreg1085 ; CHECK-NEXT: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0)1086 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r01087 ; CHECK-NEXT: {{ $}}1088 ; CHECK-NEXT: bb.2 (align 4):1089 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)1090 ; CHECK-NEXT: liveins: $lr, $q0, $r11091 ; CHECK-NEXT: {{ $}}1092 ; CHECK-NEXT: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0)1093 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr1094 ; CHECK-NEXT: renamable $r1 = MVE_VSTRWU32_post renamable $q0, killed renamable $r1, 16, 1, killed renamable $vpr, $noreg :: (store (s128), align 4)1095 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.21096 ; CHECK-NEXT: {{ $}}1097 ; CHECK-NEXT: bb.3:1098 ; CHECK-NEXT: $sp = frame-destroy tADDspi $sp, 1, 14 /* CC::al */, $noreg1099 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit undef $r01100 bb.0:1101 successors: %bb.1(0x50000000), %bb.3(0x30000000)1102 liveins: $r0, $r1, $r2, $r7, $lr1103 1104 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp1105 frame-setup CFI_INSTRUCTION def_cfa_offset 81106 frame-setup CFI_INSTRUCTION offset $lr, -41107 frame-setup CFI_INSTRUCTION offset $r7, -81108 $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg1109 frame-setup CFI_INSTRUCTION def_cfa_offset 121110 tCMPi8 renamable $r0, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr1111 tBcc %bb.3, 11 /* CC::lt */, killed $cpsr1112 1113 bb.1:1114 successors: %bb.2(0x80000000)1115 liveins: $r0, $r1, $r21116 1117 tCMPi8 killed renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr1118 renamable $r2 = t2CSINC $zr, $zr, 0, implicit killed $cpsr1119 renamable $r3, dead $cpsr = tADDi3 renamable $r0, 3, 14 /* CC::al */, $noreg1120 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q01121 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg1122 renamable $r12 = t2ANDri killed renamable $r2, 1, 14 /* CC::al */, $noreg, $noreg1123 renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg1124 renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg1125 renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg1126 renamable $r2 = t2RSBri killed renamable $r12, 0, 14 /* CC::al */, $noreg, $noreg1127 $vpr = VMSR_P0 killed $r2, 14 /* CC::al */, $noreg1128 VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0)1129 renamable $lr = t2DoLoopStartTP killed renamable $lr, renamable $r01130 1131 bb.2 (align 4):1132 successors: %bb.2(0x7c000000), %bb.3(0x04000000)1133 liveins: $lr, $q0, $r0, $r11134 1135 renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0)1136 MVE_VPST 8, implicit $vpr1137 renamable $vpr = MVE_VCTP32 renamable $r0, 1, killed renamable $vpr, $noreg1138 renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg1139 MVE_VPST 8, implicit $vpr1140 renamable $r1 = MVE_VSTRWU32_post renamable $q0, killed renamable $r1, 16, 1, killed renamable $vpr, $noreg :: (store (s128), align 4)1141 renamable $lr = t2LoopDec killed renamable $lr, 11142 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr1143 tB %bb.3, 14 /* CC::al */, $noreg1144 1145 bb.3:1146 $sp = frame-destroy tADDspi $sp, 1, 14 /* CC::al */, $noreg1147 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit undef $r01148...1149---1150name: predvcmp1151alignment: 81152tracksRegLiveness: true1153liveins:1154 - { reg: '$r0', virtual-reg: '' }1155 - { reg: '$r1', virtual-reg: '' }1156 - { reg: '$r2', virtual-reg: '' }1157stack:1158 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,1159 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,1160 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }1161 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,1162 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,1163 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }1164constants:1165 - id: 01166 value: '<4 x i32> <i32 0, i32 1, i32 2, i32 3>'1167 alignment: 81168 isTargetSpecific: false1169body: |1170 ; CHECK-LABEL: name: predvcmp1171 ; CHECK: bb.0:1172 ; CHECK-NEXT: successors: %bb.1(0x80000000)1173 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r71174 ; CHECK-NEXT: {{ $}}1175 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp1176 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 81177 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -41178 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -81179 ; CHECK-NEXT: tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr1180 ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate1181 ; CHECK-NEXT: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate1182 ; CHECK-NEXT: {{ $}}1183 ; CHECK-NEXT: bb.1:1184 ; CHECK-NEXT: successors: %bb.2(0x80000000)1185 ; CHECK-NEXT: liveins: $r0, $r1, $r21186 ; CHECK-NEXT: {{ $}}1187 ; CHECK-NEXT: renamable $r12 = t2LEApcrel %const.0, 14 /* CC::al */, $noreg1188 ; CHECK-NEXT: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q11189 ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool, align 8)1190 ; CHECK-NEXT: renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q21191 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r21192 ; CHECK-NEXT: {{ $}}1193 ; CHECK-NEXT: bb.2 (align 4):1194 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)1195 ; CHECK-NEXT: liveins: $lr, $q0, $q1, $q2, $r0, $r11196 ; CHECK-NEXT: {{ $}}1197 ; CHECK-NEXT: MVE_VPTv4s32r 8, renamable $q0, renamable $r1, 11, implicit-def $vpr1198 ; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post renamable $q1, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128), align 4)1199 ; CHECK-NEXT: renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, $noreg, undef renamable $q01200 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.21201 ; CHECK-NEXT: {{ $}}1202 ; CHECK-NEXT: bb.3:1203 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc1204 ; CHECK-NEXT: {{ $}}1205 ; CHECK-NEXT: bb.4 (align 8):1206 ; CHECK-NEXT: CONSTPOOL_ENTRY 0, %const.0, 161207 bb.0:1208 successors: %bb.1(0x80000000)1209 liveins: $r0, $r1, $r2, $r7, $lr1210 1211 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp1212 frame-setup CFI_INSTRUCTION def_cfa_offset 81213 frame-setup CFI_INSTRUCTION offset $lr, -41214 frame-setup CFI_INSTRUCTION offset $r7, -81215 tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr1216 t2IT 11, 8, implicit-def $itstate1217 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate1218 1219 bb.1:1220 successors: %bb.2(0x80000000)1221 liveins: $r0, $r1, $r21222 1223 renamable $r12 = t2LEApcrel %const.0, 14 /* CC::al */, $noreg1224 renamable $r3, dead $cpsr = nuw tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg1225 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg1226 renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q11227 renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool, align 8)1228 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg1229 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg1230 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg1231 renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q21232 renamable $lr = t2DoLoopStartTP killed renamable $lr, renamable $r21233 1234 bb.2 (align 4):1235 successors: %bb.2(0x7c000000), %bb.3(0x04000000)1236 liveins: $lr, $q0, $q1, $q2, $r0, $r1, $r21237 1238 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg1239 MVE_VPST 4, implicit $vpr1240 renamable $vpr = MVE_VCMPs32r renamable $q0, renamable $r1, 11, 1, killed renamable $vpr, $noreg1241 renamable $r0 = MVE_VSTRWU32_post renamable $q1, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128), align 4)1242 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg1243 renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, $noreg, undef renamable $q01244 renamable $lr = t2LoopDec killed renamable $lr, 1, implicit-def dead $cpsr1245 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr1246 tB %bb.3, 14 /* CC::al */, $noreg1247 1248 bb.3:1249 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc1250 1251 bb.4 (align 8):1252 CONSTPOOL_ENTRY 0, %const.0, 161253 1254...1255---1256name: predvpt1257alignment: 81258tracksRegLiveness: true1259liveins:1260 - { reg: '$r0', virtual-reg: '' }1261 - { reg: '$r1', virtual-reg: '' }1262 - { reg: '$r2', virtual-reg: '' }1263stack:1264 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,1265 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,1266 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }1267 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,1268 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,1269 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }1270constants:1271 - id: 01272 value: '<4 x i32> <i32 0, i32 1, i32 2, i32 3>'1273 alignment: 81274 isTargetSpecific: false1275body: |1276 ; CHECK-LABEL: name: predvpt1277 ; CHECK: bb.0:1278 ; CHECK-NEXT: successors: %bb.1(0x80000000)1279 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r71280 ; CHECK-NEXT: {{ $}}1281 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp1282 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 81283 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -41284 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -81285 ; CHECK-NEXT: tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr1286 ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate1287 ; CHECK-NEXT: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate1288 ; CHECK-NEXT: {{ $}}1289 ; CHECK-NEXT: bb.1:1290 ; CHECK-NEXT: successors: %bb.2(0x80000000)1291 ; CHECK-NEXT: liveins: $r0, $r1, $r21292 ; CHECK-NEXT: {{ $}}1293 ; CHECK-NEXT: renamable $r12 = t2LEApcrel %const.0, 14 /* CC::al */, $noreg1294 ; CHECK-NEXT: renamable $r3, dead $cpsr = nuw tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg1295 ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg1296 ; CHECK-NEXT: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q11297 ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool, align 8)1298 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg1299 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg1300 ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg1301 ; CHECK-NEXT: renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q21302 ; CHECK-NEXT: {{ $}}1303 ; CHECK-NEXT: bb.2 (align 4):1304 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)1305 ; CHECK-NEXT: liveins: $lr, $q0, $q1, $q2, $r0, $r1, $r21306 ; CHECK-NEXT: {{ $}}1307 ; CHECK-NEXT: MVE_VPTv4s32r 8, renamable $q0, renamable $r1, 11, implicit-def $vpr1308 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed $vpr, $noreg1309 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr1310 ; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post renamable $q1, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128), align 4)1311 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg1312 ; CHECK-NEXT: renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, $noreg, undef renamable $q01313 ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.21314 ; CHECK-NEXT: {{ $}}1315 ; CHECK-NEXT: bb.3:1316 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc1317 ; CHECK-NEXT: {{ $}}1318 ; CHECK-NEXT: bb.4 (align 8):1319 ; CHECK-NEXT: CONSTPOOL_ENTRY 0, %const.0, 161320 bb.0:1321 successors: %bb.1(0x80000000)1322 liveins: $r0, $r1, $r2, $r7, $lr1323 1324 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp1325 frame-setup CFI_INSTRUCTION def_cfa_offset 81326 frame-setup CFI_INSTRUCTION offset $lr, -41327 frame-setup CFI_INSTRUCTION offset $r7, -81328 tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr1329 t2IT 11, 8, implicit-def $itstate1330 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate1331 1332 bb.1:1333 successors: %bb.2(0x80000000)1334 liveins: $r0, $r1, $r21335 1336 renamable $r12 = t2LEApcrel %const.0, 14 /* CC::al */, $noreg1337 renamable $r3, dead $cpsr = nuw tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg1338 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg1339 renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q11340 renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool, align 8)1341 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg1342 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg1343 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg1344 renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q21345 renamable $lr = t2DoLoopStartTP killed renamable $lr, renamable $r21346 1347 bb.2 (align 4):1348 successors: %bb.2(0x7c000000), %bb.3(0x04000000)1349 liveins: $lr, $q0, $q1, $q2, $r0, $r1, $r21350 1351 MVE_VPTv4s32r 8, renamable $q0, renamable $r1, 11, implicit-def $vpr1352 renamable $vpr = MVE_VCTP32 renamable $r2, 1, $vpr, $noreg1353 MVE_VPST 8, implicit $vpr1354 renamable $r0 = MVE_VSTRWU32_post renamable $q1, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128), align 4)1355 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg1356 renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, $noreg, undef renamable $q01357 renamable $lr = t2LoopDec killed renamable $lr, 1, implicit-def dead $cpsr1358 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr1359 tB %bb.3, 14 /* CC::al */, $noreg1360 1361 bb.3:1362 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc1363 1364 bb.4 (align 8):1365 CONSTPOOL_ENTRY 0, %const.0, 161366...1367