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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+lob %s -run-pass=arm-low-overhead-loops --verify-machineinstrs -o - | FileCheck %s3 4# TODO: Remove the lr = tMOVr which actually makes the WLS def dead!5 6--- |7 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"8 target triple = "thumbv8.1m.main"9 10 define dso_local arm_aapcscc void @copy(ptr nocapture %a, ptr nocapture readonly %b, i32 %N) {11 entry:12 %0 = call i1 @llvm.test.set.loop.iterations.i32(i32 %N)13 br i1 %0, label %while.body.preheader, label %while.end14 15 while.body.preheader: ; preds = %entry16 %scevgep = getelementptr i16, ptr %a, i32 -117 %scevgep3 = getelementptr i16, ptr %b, i32 -118 br label %while.body19 20 while.body: ; preds = %while.body, %while.body.preheader21 %lsr.iv4 = phi ptr [ %scevgep3, %while.body.preheader ], [ %scevgep5, %while.body ]22 %lsr.iv = phi ptr [ %scevgep, %while.body.preheader ], [ %scevgep1, %while.body ]23 %1 = phi i32 [ %3, %while.body ], [ %N, %while.body.preheader ]24 %scevgep7 = getelementptr i16, ptr %lsr.iv, i32 125 %scevgep4 = getelementptr i16, ptr %lsr.iv4, i32 126 %2 = load i16, ptr %scevgep4, align 227 store i16 %2, ptr %scevgep7, align 228 %3 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %1, i32 1)29 %4 = icmp ne i32 %3, 030 %scevgep1 = getelementptr i16, ptr %lsr.iv, i32 131 %scevgep5 = getelementptr i16, ptr %lsr.iv4, i32 132 br i1 %4, label %while.body, label %while.end33 34 while.end: ; preds = %while.body, %entry35 ret void36 }37 38 declare i1 @llvm.test.set.loop.iterations.i32(i32) #039 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #040 41 attributes #0 = { noduplicate nounwind }42 attributes #1 = { nounwind }43 44...45---46name: copy47alignment: 248exposesReturnsTwice: false49legalized: false50regBankSelected: false51selected: false52failedISel: false53tracksRegLiveness: true54hasWinCFI: false55registers: []56liveins:57 - { reg: '$r0', virtual-reg: '' }58 - { reg: '$r1', virtual-reg: '' }59 - { reg: '$r2', virtual-reg: '' }60frameInfo:61 isFrameAddressTaken: false62 isReturnAddressTaken: false63 hasStackMap: false64 hasPatchPoint: false65 stackSize: 866 offsetAdjustment: 067 maxAlignment: 468 adjustsStack: false69 hasCalls: false70 stackProtector: ''71 maxCallFrameSize: 072 cvBytesOfCalleeSavedRegisters: 073 hasOpaqueSPAdjustment: false74 hasVAStart: false75 hasMustTailInVarArgFunc: false76 localFrameSize: 077 savePoint: []78 restorePoint: []79fixedStack: []80stack:81 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,82 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,83 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }84 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,85 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,86 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }87callSites: []88constants: []89machineFunctionInfo: {}90body: |91 ; CHECK-LABEL: name: copy92 ; CHECK: bb.0.entry:93 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000)94 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r795 ; CHECK-NEXT: {{ $}}96 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp97 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 898 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -499 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8100 ; CHECK-NEXT: dead $lr = t2WLS $r2, %bb.3101 ; CHECK-NEXT: {{ $}}102 ; CHECK-NEXT: bb.1.while.body.preheader:103 ; CHECK-NEXT: successors: %bb.2(0x80000000)104 ; CHECK-NEXT: liveins: $r0, $r1, $r2105 ; CHECK-NEXT: {{ $}}106 ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 2, 14 /* CC::al */, $noreg107 ; CHECK-NEXT: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 2, 14 /* CC::al */, $noreg108 ; CHECK-NEXT: $lr = tMOVr killed $r2, 14 /* CC::al */, $noreg109 ; CHECK-NEXT: {{ $}}110 ; CHECK-NEXT: bb.2.while.body:111 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)112 ; CHECK-NEXT: liveins: $lr, $r0, $r1113 ; CHECK-NEXT: {{ $}}114 ; CHECK-NEXT: renamable $r2, renamable $r1 = t2LDRH_PRE killed renamable $r1, 2, 14 /* CC::al */, $noreg :: (load (s16) from %ir.scevgep4)115 ; CHECK-NEXT: early-clobber renamable $r0 = t2STRH_PRE killed renamable $r2, killed renamable $r0, 2, 14 /* CC::al */, $noreg :: (store (s16) into %ir.scevgep7)116 ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2117 ; CHECK-NEXT: {{ $}}118 ; CHECK-NEXT: bb.3.while.end:119 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc120 bb.0.entry:121 successors: %bb.1(0x40000000), %bb.3(0x40000000)122 liveins: $r0, $r1, $r2, $r7, $lr123 124 frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp125 frame-setup CFI_INSTRUCTION def_cfa_offset 8126 frame-setup CFI_INSTRUCTION offset $lr, -4127 frame-setup CFI_INSTRUCTION offset $r7, -8128 $lr = t2WhileLoopStartLR $r2, %bb.3, implicit-def dead $cpsr129 tB %bb.1, 14, $noreg130 131 bb.1.while.body.preheader:132 successors: %bb.2(0x80000000)133 liveins: $r0, $r1, $r2134 135 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 2, 14, $noreg136 renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 2, 14, $noreg137 $lr = tMOVr killed $r2, 14, $noreg138 139 bb.2.while.body:140 successors: %bb.2(0x7c000000), %bb.3(0x04000000)141 liveins: $lr, $r0, $r1142 143 renamable $r2, renamable $r1 = t2LDRH_PRE killed renamable $r1, 2, 14, $noreg :: (load (s16) from %ir.scevgep4)144 early-clobber renamable $r0 = t2STRH_PRE killed renamable $r2, killed renamable $r0, 2, 14, $noreg :: (store (s16) into %ir.scevgep7)145 renamable $lr = t2LoopDec killed renamable $lr, 1146 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr147 tB %bb.3, 14, $noreg148 149 bb.3.while.end:150 tPOP_RET 14, $noreg, def $r7, def $pc151 152...153