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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve %s -run-pass=arm-mve-vpt-opts --verify-machineinstrs -o - | FileCheck %s3 4--- |5 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"6 target triple = "thumbv8.1m.main-none-eabi"7 8 define i32 @test(ptr nocapture %x, i32 %n, i64 %a, i32 %m) {9 entry:10 %cmp.not = icmp eq i32 %n, 011 %0 = call { i32, i1 } @llvm.test.start.loop.iterations.i32(i32 %n)12 %1 = extractvalue { i32, i1 } %0, 113 %2 = extractvalue { i32, i1 } %0, 014 br i1 %1, label %if.then, label %if.end15 16 if.then: ; preds = %entry17 %conv = sext i32 %m to i6418 %div = sdiv i64 %a, %conv19 %scevgep = getelementptr i64, ptr %x, i32 %m20 br label %do.body21 22 do.body: ; preds = %do.body, %if.then23 %lsr.iv = phi ptr [ %scevgep1, %do.body ], [ %scevgep, %if.then ]24 %3 = phi i32 [ %2, %if.then ], [ %4, %do.body ]25 store i64 %div, ptr %lsr.iv, align 826 %scevgep1 = getelementptr i64, ptr %lsr.iv, i32 127 %4 = call i32 @llvm.loop.decrement.reg.i32(i32 %3, i32 1)28 %5 = icmp ne i32 %4, 029 br i1 %5, label %do.body, label %if.end30 31 if.end: ; preds = %do.body, %entry32 ret i32 undef33 }34 35 declare { i32, i1 } @llvm.test.start.loop.iterations.i32(i32)36 declare i32 @llvm.loop.decrement.reg.i32(i32, i32)37 38...39---40name: test41alignment: 442tracksRegLiveness: true43registers:44 - { id: 0, class: gpr, preferred-register: '' }45 - { id: 1, class: gpr, preferred-register: '' }46 - { id: 2, class: gpr, preferred-register: '' }47 - { id: 3, class: gpr, preferred-register: '' }48 - { id: 4, class: gprnopc, preferred-register: '' }49 - { id: 5, class: gprlr, preferred-register: '' }50 - { id: 6, class: gpr, preferred-register: '' }51 - { id: 7, class: gpr, preferred-register: '' }52 - { id: 8, class: gprnopc, preferred-register: '' }53 - { id: 9, class: rgpr, preferred-register: '' }54 - { id: 10, class: gpr, preferred-register: '' }55 - { id: 11, class: gpr, preferred-register: '' }56 - { id: 12, class: gpr, preferred-register: '' }57 - { id: 13, class: gpr, preferred-register: '' }58 - { id: 14, class: rgpr, preferred-register: '' }59 - { id: 15, class: gprlr, preferred-register: '' }60 - { id: 16, class: rgpr, preferred-register: '' }61 - { id: 17, class: gpr, preferred-register: '' }62 - { id: 18, class: gpr, preferred-register: '' }63 - { id: 19, class: gprnopc, preferred-register: '' }64 - { id: 20, class: rgpr, preferred-register: '' }65 - { id: 21, class: gprlr, preferred-register: '' }66 - { id: 22, class: gprlr, preferred-register: '' }67 - { id: 23, class: gpr, preferred-register: '' }68liveins:69 - { reg: '$r0', virtual-reg: '%8' }70 - { reg: '$r1', virtual-reg: '%9' }71 - { reg: '$r2', virtual-reg: '%10' }72 - { reg: '$r3', virtual-reg: '%11' }73fixedStack:74 - { id: 0, type: default, offset: 0, size: 4, alignment: 8, stack-id: default,75 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,76 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }77body: |78 ; CHECK-LABEL: name: test79 ; CHECK: bb.0.entry:80 ; CHECK: successors: %bb.1(0x40000000), %bb.3(0x40000000)81 ; CHECK: liveins: $r0, $r1, $r2, $r382 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r383 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r284 ; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY $r185 ; CHECK: [[COPY3:%[0-9]+]]:gprnopc = COPY $r086 ; CHECK: t2CMPri [[COPY2]], 0, 14 /* CC::al */, $noreg, implicit-def $cpsr87 ; CHECK: t2Bcc %bb.3, 0 /* CC::eq */, $cpsr88 ; CHECK: t2B %bb.1, 14 /* CC::al */, $noreg89 ; CHECK: bb.1.if.then:90 ; CHECK: successors: %bb.2(0x80000000)91 ; CHECK: [[COPY4:%[0-9]+]]:gpr = COPY [[COPY]]92 ; CHECK: [[COPY5:%[0-9]+]]:gpr = COPY [[COPY1]]93 ; CHECK: [[t2LDRi12_:%[0-9]+]]:rgpr = t2LDRi12 %fixed-stack.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)94 ; CHECK: [[t2ASRri:%[0-9]+]]:rgpr = t2ASRri [[t2LDRi12_]], 31, 14 /* CC::al */, $noreg, $noreg95 ; CHECK: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def dead $sp, implicit $sp96 ; CHECK: $r0 = COPY [[COPY5]]97 ; CHECK: $r1 = COPY [[COPY4]]98 ; CHECK: $r2 = COPY [[t2LDRi12_]]99 ; CHECK: $r3 = COPY [[t2ASRri]]100 ; CHECK: tBL 14 /* CC::al */, $noreg, &__aeabi_ldivmod, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $sp, implicit-def $r0, implicit-def $r1101 ; CHECK: ADJCALLSTACKUP 0, 0, 14 /* CC::al */, $noreg, implicit-def dead $sp, implicit $sp102 ; CHECK: [[COPY6:%[0-9]+]]:gpr = COPY $r0103 ; CHECK: [[COPY7:%[0-9]+]]:gpr = COPY $r1104 ; CHECK: [[COPY8:%[0-9]+]]:gpr = COPY [[COPY7]]105 ; CHECK: [[COPY9:%[0-9]+]]:gpr = COPY [[COPY6]]106 ; CHECK: [[t2ADDrs:%[0-9]+]]:gprnopc = t2ADDrs [[COPY3]], [[t2LDRi12_]], 26, 14 /* CC::al */, $noreg, $noreg107 ; CHECK: [[COPY10:%[0-9]+]]:gpr = COPY [[t2ADDrs]]108 ; CHECK: [[t2DoLoopStart:%[0-9]+]]:gprlr = t2DoLoopStart killed [[COPY2]]109 ; CHECK: bb.2.do.body:110 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)111 ; CHECK: [[PHI:%[0-9]+]]:gprnopc = PHI [[COPY10]], %bb.1, %6, %bb.2112 ; CHECK: [[PHI1:%[0-9]+]]:gprlr = PHI [[t2DoLoopStart]], %bb.1, %21, %bb.2113 ; CHECK: t2STRi12 [[COPY9]], [[PHI]], 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.lsr.iv, align 8)114 ; CHECK: t2STRi12 [[COPY8]], [[PHI]], 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.lsr.iv + 4, basealign 8)115 ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[PHI]], 8, 14 /* CC::al */, $noreg, $noreg116 ; CHECK: [[COPY11:%[0-9]+]]:gpr = COPY [[t2ADDri]]117 ; CHECK: [[t2LoopEndDec:%[0-9]+]]:gprlr = t2LoopEndDec [[PHI1]], %bb.2, implicit-def $cpsr118 ; CHECK: t2B %bb.3, 14 /* CC::al */, $noreg119 ; CHECK: bb.3.if.end:120 ; CHECK: [[DEF:%[0-9]+]]:gpr = IMPLICIT_DEF121 ; CHECK: $r0 = COPY [[DEF]]122 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0123 bb.0.entry:124 successors: %bb.1(0x40000000), %bb.3(0x40000000)125 liveins: $r0, $r1, $r2, $r3126 127 %11:gpr = COPY $r3128 %10:gpr = COPY $r2129 %9:rgpr = COPY $r1130 %8:gprnopc = COPY $r0131 %15:gprlr = t2WhileLoopSetup killed %9132 t2WhileLoopStart %15, %bb.3, implicit-def dead $cpsr133 t2B %bb.1, 14 /* CC::al */, $noreg134 135 bb.1.if.then:136 successors: %bb.2(0x80000000)137 138 %13:gpr = COPY %11139 %12:gpr = COPY %10140 %14:rgpr = t2LDRi12 %fixed-stack.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)141 %0:gpr = COPY %15142 %16:rgpr = t2ASRri %14, 31, 14 /* CC::al */, $noreg, $noreg143 ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def dead $sp, implicit $sp144 $r0 = COPY %12145 $r1 = COPY %13146 $r2 = COPY %14147 $r3 = COPY %16148 tBL 14 /* CC::al */, $noreg, &__aeabi_ldivmod, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $sp, implicit-def $r0, implicit-def $r1149 ADJCALLSTACKUP 0, 0, 14 /* CC::al */, $noreg, implicit-def dead $sp, implicit $sp150 %17:gpr = COPY $r0151 %18:gpr = COPY $r1152 %2:gpr = COPY %18153 %1:gpr = COPY %17154 %19:gprnopc = t2ADDrs %8, %14, 26, 14 /* CC::al */, $noreg, $noreg155 %3:gpr = COPY %19156 157 bb.2.do.body:158 successors: %bb.2(0x7c000000), %bb.3(0x04000000)159 160 %4:gprnopc = PHI %3, %bb.1, %6, %bb.2161 %5:gprlr = PHI %0, %bb.1, %7, %bb.2162 t2STRi12 %1, %4, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.lsr.iv, align 8)163 t2STRi12 %2, %4, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.lsr.iv + 4, basealign 8)164 %20:rgpr = t2ADDri %4, 8, 14 /* CC::al */, $noreg, $noreg165 %6:gpr = COPY %20166 %21:gprlr = t2LoopDec %5, 1167 %7:gpr = COPY %21168 t2LoopEnd %21, %bb.2, implicit-def dead $cpsr169 t2B %bb.3, 14 /* CC::al */, $noreg170 171 bb.3.if.end:172 %23:gpr = IMPLICIT_DEF173 $r0 = COPY %23174 tBX_RET 14 /* CC::al */, $noreg, implicit $r0175 176...177