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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s3 4--- |5 define dso_local arm_aapcs_vfpcc void @test_wlstp8(ptr noalias nocapture %a, ptr noalias nocapture readonly %b, ptr noalias nocapture readonly %c, i32 %N) {6 entry:7 %0 = add i32 %N, 158 %1 = lshr i32 %0, 49 %2 = shl nuw i32 %1, 410 %3 = add i32 %2, -1611 %4 = lshr i32 %3, 412 %n.vec = add nuw nsw i32 %4, 113 %cmp = call i1 @llvm.test.set.loop.iterations.i32(i32 %n.vec)14 br i1 %cmp, label %for.cond.cleanup, label %vector.ph15 16 vector.ph: ; preds = %entry17 br label %vector.body18 19 vector.body: ; preds = %vector.body, %vector.ph20 %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]21 %count = phi i32 [ %n.vec, %vector.ph ], [ %loop.dec, %vector.body ]22 %5 = phi i32 [ %N, %vector.ph ], [ %7, %vector.body ]23 %6 = call <16 x i1> @llvm.arm.vctp8(i32 %5)24 %7 = sub i32 %5, 1625 %scevgep4 = getelementptr i8, ptr %b, i32 %index26 %scevgep45 = bitcast ptr %scevgep4 to ptr27 %wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %scevgep45, i32 1, <16 x i1> %6, <16 x i8> undef)28 %scevgep2 = getelementptr i8, ptr %c, i32 %index29 %scevgep23 = bitcast ptr %scevgep2 to ptr30 %wide.masked.load14 = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %scevgep23, i32 1, <16 x i1> %6, <16 x i8> undef)31 %tmp5 = mul <16 x i8> %wide.masked.load14, %wide.masked.load32 %scevgep = getelementptr i8, ptr %a, i32 %index33 %scevgep1 = bitcast ptr %scevgep to ptr34 call void @llvm.masked.store.v16i8.p0(<16 x i8> %tmp5, ptr %scevgep1, i32 1, <16 x i1> %6)35 %index.next = add i32 %index, 1636 %loop.dec = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %count, i32 1)37 %tmp8 = icmp eq i32 %loop.dec, 038 br i1 %tmp8, label %for.cond.cleanup, label %vector.body39 40 for.cond.cleanup: ; preds = %vector.body, %entry41 ret void42 }43 44 define dso_local arm_aapcs_vfpcc void @test_wlstp16(ptr noalias nocapture %a, ptr noalias nocapture readonly %b, ptr noalias nocapture readonly %c, i32 %N) {45 entry:46 %0 = add i32 %N, 747 %1 = lshr i32 %0, 348 %2 = shl nuw i32 %1, 349 %3 = add i32 %2, -850 %4 = lshr i32 %3, 351 %n.vec = add nuw nsw i32 %4, 152 %cmp = call i1 @llvm.test.set.loop.iterations.i32(i32 %n.vec)53 br i1 %cmp, label %for.cond.cleanup, label %vector.ph54 55 vector.ph: ; preds = %entry56 br label %vector.body57 58 vector.body: ; preds = %vector.body, %vector.ph59 %lsr.iv5 = phi ptr [ %scevgep6, %vector.body ], [ %b, %vector.ph ]60 %lsr.iv2 = phi ptr [ %scevgep3, %vector.body ], [ %c, %vector.ph ]61 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]62 %count = phi i32 [ %n.vec, %vector.ph ], [ %loop.dec, %vector.body ]63 %5 = phi i32 [ %N, %vector.ph ], [ %7, %vector.body ]64 %lsr.iv57 = bitcast ptr %lsr.iv5 to ptr65 %lsr.iv24 = bitcast ptr %lsr.iv2 to ptr66 %lsr.iv1 = bitcast ptr %lsr.iv to ptr67 %6 = call <8 x i1> @llvm.arm.vctp16(i32 %5)68 %7 = sub i32 %5, 869 %wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %lsr.iv57, i32 2, <8 x i1> %6, <8 x i16> undef)70 %wide.masked.load14 = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %lsr.iv24, i32 2, <8 x i1> %6, <8 x i16> undef)71 %tmp5 = mul <8 x i16> %wide.masked.load14, %wide.masked.load72 call void @llvm.masked.store.v8i16.p0(<8 x i16> %tmp5, ptr %lsr.iv1, i32 2, <8 x i1> %6)73 %loop.dec = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %count, i32 1)74 %tmp8 = icmp eq i32 %loop.dec, 075 %scevgep = getelementptr i16, ptr %lsr.iv, i32 876 %scevgep3 = getelementptr i16, ptr %lsr.iv2, i32 877 %scevgep6 = getelementptr i16, ptr %lsr.iv5, i32 878 br i1 %tmp8, label %for.cond.cleanup, label %vector.body79 80 for.cond.cleanup: ; preds = %vector.body, %entry81 ret void82 }83 84 define dso_local i32 @test_wlstp32(ptr noalias nocapture readonly %a, ptr noalias nocapture readonly %b, i32 %N) {85 entry:86 %0 = add i32 %N, 387 %1 = lshr i32 %0, 288 %2 = shl nuw i32 %1, 289 %3 = add i32 %2, -490 %4 = lshr i32 %3, 291 %n.vec = add nuw nsw i32 %4, 192 %cmp = call i1 @llvm.test.set.loop.iterations.i32(i32 %n.vec)93 br i1 %cmp, label %for.cond.cleanup, label %vector.ph94 95 vector.ph: ; preds = %entry96 br label %vector.body97 98 vector.body: ; preds = %vector.body, %vector.ph99 %lsr.iv2 = phi ptr [ %scevgep3, %vector.body ], [ %a, %vector.ph ]100 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %b, %vector.ph ]101 %count = phi i32 [ %n.vec, %vector.ph ], [ %loop.dec, %vector.body ]102 %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %tmp6, %vector.body ]103 %5 = phi i32 [ %N, %vector.ph ], [ %7, %vector.body ]104 %lsr.iv24 = bitcast ptr %lsr.iv2 to ptr105 %lsr.iv1 = bitcast ptr %lsr.iv to ptr106 %6 = call <4 x i1> @llvm.arm.vctp32(i32 %5)107 %7 = sub i32 %5, 4108 %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv24, i32 4, <4 x i1> %6, <4 x i32> undef)109 %wide.masked.load13 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv1, i32 4, <4 x i1> %6, <4 x i32> undef)110 %tmp5 = mul nsw <4 x i32> %wide.masked.load13, %wide.masked.load111 %tmp6 = add nsw <4 x i32> %tmp5, %vec.phi112 %loop.dec = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %count, i32 1)113 %tmp7 = icmp eq i32 %loop.dec, 0114 %scevgep = getelementptr i32, ptr %lsr.iv, i32 4115 %scevgep3 = getelementptr i32, ptr %lsr.iv2, i32 4116 br i1 %tmp7, label %middle.block, label %vector.body117 118 middle.block: ; preds = %vector.body119 %8 = call <4 x i1> @llvm.arm.vctp32(i32 %5)120 %tmp8 = select <4 x i1> %8, <4 x i32> %tmp6, <4 x i32> %vec.phi121 %tmp9 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %tmp8)122 br label %for.cond.cleanup123 124 for.cond.cleanup: ; preds = %middle.block, %entry125 %res.0.lcssa = phi i32 [ 0, %entry ], [ %tmp9, %middle.block ]126 ret i32 %res.0.lcssa127 }128 129 declare i1 @llvm.test.set.loop.iterations.i32(i32)130 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)131 declare <16 x i8> @llvm.masked.load.v16i8.p0(ptr, i32 immarg, <16 x i1>, <16 x i8>)132 declare <8 x i16> @llvm.masked.load.v8i16.p0(ptr, i32 immarg, <8 x i1>, <8 x i16>)133 declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>)134 declare void @llvm.masked.store.v16i8.p0(<16 x i8>, ptr, i32 immarg, <16 x i1>)135 declare void @llvm.masked.store.v8i16.p0(<8 x i16>, ptr, i32 immarg, <8 x i1>)136 declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr, i32 immarg, <4 x i1>)137 declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)138 declare <16 x i1> @llvm.arm.vctp8(i32)139 declare void @llvm.stackprotector(ptr, ptr)140 declare <8 x i1> @llvm.arm.vctp16(i32)141 declare <4 x i1> @llvm.arm.vctp32(i32)142...143---144name: test_wlstp8145alignment: 2146exposesReturnsTwice: false147legalized: false148regBankSelected: false149selected: false150failedISel: false151tracksRegLiveness: true152hasWinCFI: false153registers: []154liveins:155 - { reg: '$r0', virtual-reg: '' }156 - { reg: '$r1', virtual-reg: '' }157 - { reg: '$r2', virtual-reg: '' }158 - { reg: '$r3', virtual-reg: '' }159frameInfo:160 isFrameAddressTaken: false161 isReturnAddressTaken: false162 hasStackMap: false163 hasPatchPoint: false164 stackSize: 8165 offsetAdjustment: 0166 maxAlignment: 4167 adjustsStack: false168 hasCalls: false169 stackProtector: ''170 maxCallFrameSize: 0171 cvBytesOfCalleeSavedRegisters: 0172 hasOpaqueSPAdjustment: false173 hasVAStart: false174 hasMustTailInVarArgFunc: false175 localFrameSize: 0176 savePoint: []177 restorePoint: []178fixedStack: []179stack:180 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,181 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,182 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }183 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,184 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,185 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }186callSites: []187constants: []188machineFunctionInfo: {}189body: |190 ; CHECK-LABEL: name: test_wlstp8191 ; CHECK: bb.0.entry:192 ; CHECK: successors: %bb.3(0x40000000), %bb.1(0x40000000)193 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4194 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp195 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8196 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4197 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8198 ; CHECK: $lr = MVE_WLSTP_8 killed renamable $r3, %bb.1199 ; CHECK: tB %bb.3, 14 /* CC::al */, $noreg200 ; CHECK: bb.1.vector.ph:201 ; CHECK: successors: %bb.2(0x80000000)202 ; CHECK: liveins: $lr, $r0, $r1, $r2203 ; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg204 ; CHECK: bb.2.vector.body:205 ; CHECK: successors: %bb.3(0x04000000), %bb.2(0x7c000000)206 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r12207 ; CHECK: renamable $r4 = t2ADDrr renamable $r1, renamable $r12, 14 /* CC::al */, $noreg, $noreg208 ; CHECK: renamable $q0 = MVE_VLDRBU8 killed renamable $r4, 0, 0, $noreg, $noreg :: (load (s128) from %ir.scevgep45, align 1)209 ; CHECK: renamable $r4 = t2ADDrr renamable $r2, renamable $r12, 14 /* CC::al */, $noreg, $noreg210 ; CHECK: renamable $q1 = MVE_VLDRBU8 killed renamable $r4, 0, 0, $noreg, $noreg :: (load (s128) from %ir.scevgep23, align 1)211 ; CHECK: renamable $r4 = t2ADDrr renamable $r0, renamable $r12, 14 /* CC::al */, $noreg, $noreg212 ; CHECK: renamable $r12 = t2ADDri killed renamable $r12, 16, 14 /* CC::al */, $noreg, $noreg213 ; CHECK: renamable $q0 = MVE_VMULi8 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0214 ; CHECK: MVE_VSTRBU8 killed renamable $q0, killed renamable $r4, 0, 0, killed $noreg, $noreg :: (store (s128) into %ir.scevgep1, align 1)215 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2216 ; CHECK: bb.3.for.cond.cleanup:217 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc218 bb.0.entry:219 successors: %bb.3(0x40000000), %bb.1(0x40000000)220 liveins: $r0, $r1, $r2, $r3, $r4, $lr221 222 frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp223 frame-setup CFI_INSTRUCTION def_cfa_offset 8224 frame-setup CFI_INSTRUCTION offset $lr, -4225 frame-setup CFI_INSTRUCTION offset $r4, -8226 renamable $r12 = t2ADDri renamable $r3, 15, 14, $noreg, $noreg227 renamable $lr = t2MOVi 1, 14, $noreg, $noreg228 renamable $r12 = t2BICri killed renamable $r12, 15, 14, $noreg, $noreg229 renamable $r12 = t2SUBri killed renamable $r12, 16, 14, $noreg, $noreg230 renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 35, 14, $noreg, $noreg231 $lr = t2WhileLoopStartLR renamable $lr, %bb.1, implicit-def dead $cpsr232 tB %bb.3, 14, $noreg233 234 bb.1.vector.ph:235 successors: %bb.2(0x80000000)236 liveins: $lr, $r0, $r1, $r2, $r3237 238 renamable $r12 = t2MOVi 0, 14, $noreg, $noreg239 240 bb.2.vector.body:241 successors: %bb.3(0x04000000), %bb.2(0x7c000000)242 liveins: $lr, $r0, $r1, $r2, $r3, $r12243 244 renamable $r4 = t2ADDrr renamable $r1, renamable $r12, 14, $noreg, $noreg245 renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg, $noreg246 MVE_VPST 8, implicit $vpr247 renamable $q0 = MVE_VLDRBU8 killed renamable $r4, 0, 1, renamable $vpr, $noreg :: (load (s128) from %ir.scevgep45, align 1)248 renamable $r4 = t2ADDrr renamable $r2, renamable $r12, 14, $noreg, $noreg249 MVE_VPST 8, implicit $vpr250 renamable $q1 = MVE_VLDRBU8 killed renamable $r4, 0, 1, renamable $vpr, $noreg :: (load (s128) from %ir.scevgep23, align 1)251 renamable $r4 = t2ADDrr renamable $r0, renamable $r12, 14, $noreg, $noreg252 renamable $r12 = t2ADDri killed renamable $r12, 16, 14, $noreg, $noreg253 renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 16, 14, $noreg254 renamable $q0 = MVE_VMULi8 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0255 MVE_VPST 8, implicit $vpr256 MVE_VSTRBU8 killed renamable $q0, killed renamable $r4, 0, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.scevgep1, align 1)257 renamable $lr = t2LoopDec killed renamable $lr, 1258 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr259 tB %bb.3, 14, $noreg260 261 bb.3.for.cond.cleanup:262 tPOP_RET 14, $noreg, def $r4, def $pc263 264...265---266name: test_wlstp16267alignment: 2268exposesReturnsTwice: false269legalized: false270regBankSelected: false271selected: false272failedISel: false273tracksRegLiveness: true274hasWinCFI: false275registers: []276liveins:277 - { reg: '$r0', virtual-reg: '' }278 - { reg: '$r1', virtual-reg: '' }279 - { reg: '$r2', virtual-reg: '' }280 - { reg: '$r3', virtual-reg: '' }281frameInfo:282 isFrameAddressTaken: false283 isReturnAddressTaken: false284 hasStackMap: false285 hasPatchPoint: false286 stackSize: 8287 offsetAdjustment: 0288 maxAlignment: 4289 adjustsStack: false290 hasCalls: false291 stackProtector: ''292 maxCallFrameSize: 0293 cvBytesOfCalleeSavedRegisters: 0294 hasOpaqueSPAdjustment: false295 hasVAStart: false296 hasMustTailInVarArgFunc: false297 localFrameSize: 0298 savePoint: []299 restorePoint: []300fixedStack: []301stack:302 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,303 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,304 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }305 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,306 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,307 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }308callSites: []309constants: []310machineFunctionInfo: {}311body: |312 ; CHECK-LABEL: name: test_wlstp16313 ; CHECK: bb.0.entry:314 ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)315 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7316 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp317 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8318 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4319 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8320 ; CHECK: $lr = MVE_WLSTP_16 killed renamable $r3, %bb.1321 ; CHECK: tB %bb.2, 14 /* CC::al */, $noreg322 ; CHECK: bb.1.vector.body:323 ; CHECK: successors: %bb.2(0x04000000), %bb.1(0x7c000000)324 ; CHECK: liveins: $lr, $r0, $r1, $r2325 ; CHECK: renamable $q0 = MVE_VLDRHU16 renamable $r1, 0, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv57, align 2)326 ; CHECK: renamable $q1 = MVE_VLDRHU16 renamable $r2, 0, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv24, align 2)327 ; CHECK: renamable $q0 = MVE_VMULi16 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0328 ; CHECK: MVE_VSTRHU16 killed renamable $q0, renamable $r0, 0, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv1, align 2)329 ; CHECK: renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg330 ; CHECK: renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg331 ; CHECK: renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg332 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1333 ; CHECK: bb.2.for.cond.cleanup:334 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc335 bb.0.entry:336 successors: %bb.2(0x40000000), %bb.1(0x40000000)337 liveins: $r0, $r1, $r2, $r3, $r7, $lr338 339 frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp340 frame-setup CFI_INSTRUCTION def_cfa_offset 8341 frame-setup CFI_INSTRUCTION offset $lr, -4342 frame-setup CFI_INSTRUCTION offset $r7, -8343 renamable $r12 = t2ADDri renamable $r3, 7, 14, $noreg, $noreg344 renamable $lr = t2MOVi 1, 14, $noreg, $noreg345 renamable $r12 = t2BICri killed renamable $r12, 7, 14, $noreg, $noreg346 renamable $r12 = t2SUBri killed renamable $r12, 8, 14, $noreg, $noreg347 renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 27, 14, $noreg, $noreg348 $lr = t2WhileLoopStartLR renamable $lr, %bb.1, implicit-def dead $cpsr349 tB %bb.2, 14, $noreg350 351 bb.1.vector.body:352 successors: %bb.2(0x04000000), %bb.1(0x7c000000)353 liveins: $lr, $r0, $r1, $r2, $r3354 355 renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg, $noreg356 MVE_VPST 4, implicit $vpr357 renamable $q0 = MVE_VLDRHU16 renamable $r1, 0, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv57, align 2)358 renamable $q1 = MVE_VLDRHU16 renamable $r2, 0, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv24, align 2)359 renamable $q0 = MVE_VMULi16 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0360 MVE_VPST 8, implicit $vpr361 MVE_VSTRHU16 killed renamable $q0, renamable $r0, 0, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1, align 2)362 renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 16, 14, $noreg363 renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 16, 14, $noreg364 renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 16, 14, $noreg365 renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 8, 14, $noreg366 renamable $lr = t2LoopDec killed renamable $lr, 1367 t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr368 tB %bb.2, 14, $noreg369 370 bb.2.for.cond.cleanup:371 tPOP_RET 14, $noreg, def $r7, def $pc372 373...374---375name: test_wlstp32376alignment: 2377exposesReturnsTwice: false378legalized: false379regBankSelected: false380selected: false381failedISel: false382tracksRegLiveness: true383hasWinCFI: false384registers: []385liveins:386 - { reg: '$r0', virtual-reg: '' }387 - { reg: '$r1', virtual-reg: '' }388 - { reg: '$r2', virtual-reg: '' }389frameInfo:390 isFrameAddressTaken: false391 isReturnAddressTaken: false392 hasStackMap: false393 hasPatchPoint: false394 stackSize: 8395 offsetAdjustment: 0396 maxAlignment: 4397 adjustsStack: false398 hasCalls: false399 stackProtector: ''400 maxCallFrameSize: 0401 cvBytesOfCalleeSavedRegisters: 0402 hasOpaqueSPAdjustment: false403 hasVAStart: false404 hasMustTailInVarArgFunc: false405 localFrameSize: 0406 savePoint: []407 restorePoint: []408fixedStack: []409stack:410 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,411 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,412 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }413 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,414 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,415 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }416callSites: []417constants: []418machineFunctionInfo: {}419body: |420 ; CHECK-LABEL: name: test_wlstp32421 ; CHECK: bb.0.entry:422 ; CHECK: successors: %bb.4(0x40000000), %bb.1(0x40000000)423 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7424 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp425 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8426 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4427 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8428 ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg429 ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg430 ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg431 ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg432 ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg433 ; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg434 ; CHECK: $lr = t2WLS killed renamable $lr, %bb.1435 ; CHECK: tB %bb.4, 14 /* CC::al */, $noreg436 ; CHECK: bb.1.vector.ph:437 ; CHECK: successors: %bb.2(0x80000000)438 ; CHECK: liveins: $lr, $r0, $r1, $r2439 ; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1440 ; CHECK: bb.2.vector.body:441 ; CHECK: successors: %bb.3(0x04000000), %bb.2(0x7c000000)442 ; CHECK: liveins: $lr, $q1, $r0, $r1, $r2443 ; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, $noreg, undef $q0444 ; CHECK: renamable $vpr = MVE_VCTP32 $r2, 0, $noreg, $noreg445 ; CHECK: MVE_VPST 4, implicit $vpr446 ; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv24, align 4)447 ; CHECK: renamable $q2 = MVE_VLDRWU32 renamable $r1, 0, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1, align 4)448 ; CHECK: $r3 = tMOVr $r2, 14 /* CC::al */, $noreg449 ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1450 ; CHECK: renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg451 ; CHECK: renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg452 ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed $r2, 4, 14 /* CC::al */, $noreg453 ; CHECK: MVE_VPST 8, implicit $vpr454 ; CHECK: renamable $q1 = nsw MVE_VADDi32 killed renamable $q1, renamable $q0, 1, killed renamable $vpr, $noreg, undef renamable $q1455 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2456 ; CHECK: bb.3.middle.block:457 ; CHECK: successors: %bb.4(0x80000000)458 ; CHECK: liveins: $q0, $q1, $r3459 ; CHECK: renamable $vpr = MVE_VCTP32 killed renamable $r3, 0, $noreg, $noreg460 ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr, $noreg461 ; CHECK: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg462 ; CHECK: bb.4.for.cond.cleanup:463 ; CHECK: liveins: $r12464 ; CHECK: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg465 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0466 bb.0.entry:467 successors: %bb.4(0x40000000), %bb.1(0x40000000)468 liveins: $r0, $r1, $r2, $r7, $lr469 470 frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp471 frame-setup CFI_INSTRUCTION def_cfa_offset 8472 frame-setup CFI_INSTRUCTION offset $lr, -4473 frame-setup CFI_INSTRUCTION offset $r7, -8474 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg475 renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg476 renamable $r12 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg477 renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg478 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg479 renamable $r12 = t2MOVi 0, 14, $noreg, $noreg480 $lr = t2WhileLoopStartLR renamable $lr, %bb.1, implicit-def dead $cpsr481 tB %bb.4, 14, $noreg482 483 bb.1.vector.ph:484 successors: %bb.2(0x80000000)485 liveins: $lr, $r0, $r1, $r2486 487 renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1488 489 bb.2.vector.body:490 successors: %bb.3(0x04000000), %bb.2(0x7c000000)491 liveins: $lr, $q1, $r0, $r1, $r2492 493 $q0 = MVE_VORR killed $q1, $q1, 0, $noreg, $noreg, undef $q0494 renamable $vpr = MVE_VCTP32 $r2, 0, $noreg, $noreg495 MVE_VPST 4, implicit $vpr496 renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv24, align 4)497 renamable $q2 = MVE_VLDRWU32 renamable $r1, 0, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1, align 4)498 $r3 = tMOVr $r2, 14, $noreg499 renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1500 renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 16, 14, $noreg501 renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 16, 14, $noreg502 renamable $r2, dead $cpsr = tSUBi8 killed $r2, 4, 14, $noreg503 MVE_VPST 8, implicit $vpr504 renamable $q1 = nsw MVE_VADDi32 killed renamable $q1, renamable $q0, 1, renamable $vpr, $noreg, undef renamable $q1505 renamable $lr = t2LoopDec killed renamable $lr, 1506 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr507 tB %bb.3, 14, $noreg508 509 bb.3.middle.block:510 successors: %bb.4(0x80000000)511 liveins: $q0, $q1, $r3512 513 renamable $vpr = MVE_VCTP32 killed renamable $r3, 0, $noreg, $noreg514 renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr, $noreg515 renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg516 517 bb.4.for.cond.cleanup:518 liveins: $r12519 520 $r0 = tMOVr killed $r12, 14, $noreg521 tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0522 523...524