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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s3 4# I think this should be equivalent, but the calculation in the middle block5# is too complex to process for now.6 7--- |8 define dso_local i32 @wrong_vctp_liveout(ptr nocapture readonly %a, ptr nocapture readonly %b, i32 %N) local_unnamed_addr #0 {9 entry:10 %cmp9 = icmp eq i32 %N, 011 %tmp = add i32 %N, 312 %tmp1 = lshr i32 %tmp, 213 %tmp2 = shl nuw i32 %tmp1, 214 %tmp3 = add i32 %tmp2, -415 %tmp4 = lshr i32 %tmp3, 216 %tmp5 = add nuw nsw i32 %tmp4, 117 br i1 %cmp9, label %for.cond.cleanup, label %vector.ph18 19 vector.ph: ; preds = %entry20 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5)21 br label %vector.body22 23 vector.body: ; preds = %vector.body, %vector.ph24 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ]25 %lsr.iv18 = phi ptr [ %scevgep19, %vector.body ], [ %b, %vector.ph ]26 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]27 %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %tmp13, %vector.body ]28 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ]29 %lsr.iv17 = bitcast ptr %lsr.iv to ptr30 %lsr.iv1820 = bitcast ptr %lsr.iv18 to ptr31 %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7)32 %tmp9 = sub i32 %tmp7, 433 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef)34 %tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32>35 %wide.masked.load14 = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv1820, i32 2, <4 x i1> %tmp8, <4 x i16> undef)36 %tmp11 = sext <4 x i16> %wide.masked.load14 to <4 x i32>37 %tmp12 = mul nsw <4 x i32> %tmp11, %tmp1038 %tmp13 = add <4 x i32> %tmp12, %vec.phi39 %scevgep = getelementptr i16, ptr %lsr.iv, i32 440 %scevgep19 = getelementptr i16, ptr %lsr.iv18, i32 441 %tmp14 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1)42 %tmp15 = icmp ne i32 %tmp14, 043 %lsr.iv.next = add nsw i32 %lsr.iv1, -144 br i1 %tmp15, label %vector.body, label %middle.block45 46 middle.block: ; preds = %vector.body47 %0 = add i32 %tmp9, 448 %insert.idx = insertelement <4 x i32> undef, i32 %0, i32 049 %idx.splat = shufflevector <4 x i32> %insert.idx, <4 x i32> undef, <4 x i32> zeroinitializer50 %n.minusone = add i32 %N, -151 %insert.n = insertelement <4 x i32> undef, i32 %n.minusone, i32 052 %n.splat = shufflevector <4 x i32> %insert.n, <4 x i32> undef, <4 x i32> zeroinitializer53 %tmp16 = icmp ult <4 x i32> %idx.splat, %n.splat54 %tmp17 = select <4 x i1> %tmp16, <4 x i32> %tmp13, <4 x i32> %vec.phi55 %tmp18 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %tmp17)56 br label %for.cond.cleanup57 58 for.cond.cleanup: ; preds = %middle.block, %entry59 %res.0.lcssa = phi i32 [ 0, %entry ], [ %tmp18, %middle.block ]60 ret i32 %res.0.lcssa61 }62 declare <4 x i16> @llvm.masked.load.v4i16.p0(ptr, i32 immarg, <4 x i1>, <4 x i16>) #163 declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>) #264 declare i32 @llvm.start.loop.iterations.i32(i32) #365 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #366 declare <4 x i1> @llvm.arm.mve.vctp32(i32) #467 68...69---70name: wrong_vctp_liveout71alignment: 272exposesReturnsTwice: false73legalized: false74regBankSelected: false75selected: false76failedISel: false77tracksRegLiveness: true78hasWinCFI: false79registers: []80liveins:81 - { reg: '$r0', virtual-reg: '' }82 - { reg: '$r1', virtual-reg: '' }83 - { reg: '$r2', virtual-reg: '' }84frameInfo:85 isFrameAddressTaken: false86 isReturnAddressTaken: false87 hasStackMap: false88 hasPatchPoint: false89 stackSize: 890 offsetAdjustment: 091 maxAlignment: 492 adjustsStack: false93 hasCalls: false94 stackProtector: ''95 maxCallFrameSize: 096 cvBytesOfCalleeSavedRegisters: 097 hasOpaqueSPAdjustment: false98 hasVAStart: false99 hasMustTailInVarArgFunc: false100 localFrameSize: 0101 savePoint: []102 restorePoint: []103fixedStack: []104stack:105 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,106 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,107 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }108 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,109 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,110 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }111callSites: []112constants: []113machineFunctionInfo: {}114body: |115 ; CHECK-LABEL: name: wrong_vctp_liveout116 ; CHECK: bb.0.entry:117 ; CHECK: successors: %bb.1(0x80000000)118 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7119 ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr120 ; CHECK: t2IT 0, 4, implicit-def $itstate121 ; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate122 ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate123 ; CHECK: bb.1.vector.ph:124 ; CHECK: successors: %bb.2(0x80000000)125 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7126 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp127 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8128 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4129 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8130 ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg131 ; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1132 ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg133 ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg134 ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg135 ; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg136 ; CHECK: dead $lr = t2DLS renamable $r3137 ; CHECK: $r12 = tMOVr killed $r3, 14 /* CC::al */, $noreg138 ; CHECK: $r3 = tMOVr $r2, 14 /* CC::al */, $noreg139 ; CHECK: bb.2.vector.body:140 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)141 ; CHECK: liveins: $q1, $r0, $r1, $r2, $r3, $r12142 ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg143 ; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, $noreg, undef $q0144 ; CHECK: MVE_VPST 4, implicit $vpr145 ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)146 ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2)147 ; CHECK: $lr = tMOVr $r12, 14 /* CC::al */, $noreg148 ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1149 ; CHECK: renamable $r12 = nsw t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg150 ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg151 ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1152 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2153 ; CHECK: bb.3.middle.block:154 ; CHECK: liveins: $q0, $q1, $r2, $r3155 ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r2, 1, 14 /* CC::al */, $noreg156 ; CHECK: renamable $q2 = MVE_VDUP32 killed renamable $r0, 0, $noreg, $noreg, undef renamable $q2157 ; CHECK: renamable $r0, dead $cpsr = tADDi3 killed renamable $r3, 4, 14 /* CC::al */, $noreg158 ; CHECK: renamable $vpr = MVE_VCMPu32r killed renamable $q2, killed renamable $r0, 8, 0, $noreg, $noreg159 ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr, $noreg160 ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg161 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0162 bb.0.entry:163 successors: %bb.1(0x80000000)164 liveins: $r0, $r1, $r2, $lr, $r7165 166 tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr167 t2IT 0, 4, implicit-def $itstate168 renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate169 tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate170 171 bb.1.vector.ph:172 successors: %bb.2(0x80000000)173 liveins: $r0, $r1, $r2, $lr, $r7174 175 frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp176 frame-setup CFI_INSTRUCTION def_cfa_offset 8177 frame-setup CFI_INSTRUCTION offset $lr, -4178 frame-setup CFI_INSTRUCTION offset $r7, -8179 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg180 renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1181 renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg182 renamable $r12 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg183 renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg184 renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg185 $lr = t2DoLoopStart renamable $r3186 $r12 = tMOVr killed $r3, 14, $noreg187 $r3 = tMOVr $r2, 14, $noreg188 189 bb.2.vector.body:190 successors: %bb.2(0x7c000000), %bb.3(0x04000000)191 liveins: $q1, $r0, $r1, $r2, $r3, $r12192 193 renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg194 $q0 = MVE_VORR killed $q1, $q1, 0, $noreg, $noreg, undef $q0195 MVE_VPST 4, implicit $vpr196 renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)197 renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2)198 $lr = tMOVr $r12, 14, $noreg199 renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1200 renamable $r12 = nsw t2SUBri killed $r12, 1, 14, $noreg, $noreg201 renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg202 renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1203 renamable $lr = t2LoopDec killed renamable $lr, 1204 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr205 tB %bb.3, 14, $noreg206 207 bb.3.middle.block:208 liveins: $q0, $q1, $r2, $r3209 210 renamable $r0, dead $cpsr = tSUBi3 killed renamable $r2, 1, 14, $noreg211 renamable $q2 = MVE_VDUP32 killed renamable $r0, 0, $noreg, $noreg, undef renamable $q2212 renamable $r0, dead $cpsr = tADDi3 killed renamable $r3, 4, 14, $noreg213 renamable $vpr = MVE_VCMPu32r killed renamable $q2, killed renamable $r0, 8, 0, $noreg, $noreg214 renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr, $noreg215 renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg216 tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0217 218...219