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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s3 4# The VCTP uses r2, which is redefined in the loop.5 6--- |7 define dso_local i32 @wrong_vctp_liveout(ptr nocapture readonly %a, ptr nocapture readonly %b, i32 %N) local_unnamed_addr #0 {8 entry:9 %cmp9 = icmp eq i32 %N, 010 %0 = add i32 %N, 311 %1 = lshr i32 %0, 212 %2 = shl nuw i32 %1, 213 %3 = add i32 %2, -414 %4 = lshr i32 %3, 215 %5 = add nuw nsw i32 %4, 116 br i1 %cmp9, label %for.cond.cleanup, label %vector.ph17 18 vector.ph: ; preds = %entry19 %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)20 br label %vector.body21 22 vector.body: ; preds = %vector.body, %vector.ph23 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ]24 %lsr.iv18 = phi ptr [ %scevgep19, %vector.body ], [ %b, %vector.ph ]25 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]26 %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %12, %vector.body ]27 %6 = phi i32 [ %N, %vector.ph ], [ %8, %vector.body ]28 %lsr.iv17 = bitcast ptr %lsr.iv to ptr29 %lsr.iv1820 = bitcast ptr %lsr.iv18 to ptr30 %7 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %6)31 %8 = sub i32 %6, 432 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv17, i32 2, <4 x i1> %7, <4 x i16> undef)33 %9 = sext <4 x i16> %wide.masked.load to <4 x i32>34 %wide.masked.load14 = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv1820, i32 2, <4 x i1> %7, <4 x i16> undef)35 %10 = sext <4 x i16> %wide.masked.load14 to <4 x i32>36 %11 = mul nsw <4 x i32> %10, %937 %12 = add <4 x i32> %11, %vec.phi38 %scevgep = getelementptr i16, ptr %lsr.iv, i32 439 %scevgep19 = getelementptr i16, ptr %lsr.iv18, i32 440 %13 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1)41 %14 = icmp ne i32 %13, 042 %lsr.iv.next = add nsw i32 %lsr.iv1, -143 br i1 %14, label %vector.body, label %middle.block44 45 middle.block: ; preds = %vector.body46 %15 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %8)47 %16 = select <4 x i1> %15, <4 x i32> %12, <4 x i32> %vec.phi48 %17 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %16)49 br label %for.cond.cleanup50 51 for.cond.cleanup: ; preds = %middle.block, %entry52 %res.0.lcssa = phi i32 [ 0, %entry ], [ %17, %middle.block ]53 ret i32 %res.0.lcssa54 }55 declare <4 x i16> @llvm.masked.load.v4i16.p0(ptr, i32 immarg, <4 x i1>, <4 x i16>) #156 declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>) #257 declare i32 @llvm.start.loop.iterations.i32(i32) #358 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #359 declare <4 x i1> @llvm.arm.mve.vctp32(i32) #460...61---62name: wrong_vctp_liveout63alignment: 264exposesReturnsTwice: false65legalized: false66regBankSelected: false67selected: false68failedISel: false69tracksRegLiveness: true70hasWinCFI: false71registers: []72liveins:73 - { reg: '$r0', virtual-reg: '' }74 - { reg: '$r1', virtual-reg: '' }75 - { reg: '$r2', virtual-reg: '' }76frameInfo:77 isFrameAddressTaken: false78 isReturnAddressTaken: false79 hasStackMap: false80 hasPatchPoint: false81 stackSize: 882 offsetAdjustment: 083 maxAlignment: 484 adjustsStack: false85 hasCalls: false86 stackProtector: ''87 maxCallFrameSize: 088 cvBytesOfCalleeSavedRegisters: 089 hasOpaqueSPAdjustment: false90 hasVAStart: false91 hasMustTailInVarArgFunc: false92 localFrameSize: 093 savePoint: []94 restorePoint: []95fixedStack: []96stack:97 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,98 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,99 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }100 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,101 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,102 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }103callSites: []104constants: []105machineFunctionInfo: {}106body: |107 ; CHECK-LABEL: name: wrong_vctp_liveout108 ; CHECK: bb.0.entry:109 ; CHECK: successors: %bb.1(0x80000000)110 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7111 ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr112 ; CHECK: t2IT 0, 4, implicit-def $itstate113 ; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate114 ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate115 ; CHECK: bb.1.vector.ph:116 ; CHECK: successors: %bb.2(0x80000000)117 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7118 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp119 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8120 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4121 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8122 ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg123 ; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1124 ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg125 ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg126 ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg127 ; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg128 ; CHECK: dead $lr = t2DLS renamable $r12129 ; CHECK: $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg130 ; CHECK: bb.2.vector.body:131 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)132 ; CHECK: liveins: $q1, $r0, $r1, $r2, $r3133 ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg134 ; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, $noreg, undef $q0135 ; CHECK: MVE_VPST 4, implicit $vpr136 ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)137 ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2)138 ; CHECK: $lr = tMOVr $r3, 14 /* CC::al */, $noreg139 ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1140 ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg141 ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg142 ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1143 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2144 ; CHECK: bb.3.middle.block:145 ; CHECK: liveins: $q0, $q1, $r2146 ; CHECK: renamable $vpr = MVE_VCTP32 killed renamable $r2, 0, $noreg, $noreg147 ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr, $noreg148 ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg149 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0150 bb.0.entry:151 successors: %bb.1(0x80000000)152 liveins: $r0, $r1, $r2, $lr, $r7153 154 tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr155 t2IT 0, 4, implicit-def $itstate156 renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate157 tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate158 159 bb.1.vector.ph:160 successors: %bb.2(0x80000000)161 liveins: $r0, $r1, $r2, $lr, $r7162 163 frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp164 frame-setup CFI_INSTRUCTION def_cfa_offset 8165 frame-setup CFI_INSTRUCTION offset $lr, -4166 frame-setup CFI_INSTRUCTION offset $r7, -8167 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg168 renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1169 renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg170 renamable $r12 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg171 renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg172 renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg173 $lr = t2DoLoopStart renamable $r12174 $r3 = tMOVr killed $r12, 14, $noreg175 176 bb.2.vector.body:177 successors: %bb.2(0x7c000000), %bb.3(0x04000000)178 liveins: $q1, $r0, $r1, $r2, $r3179 180 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg181 $q0 = MVE_VORR killed $q1, $q1, 0, $noreg, $noreg, undef $q0182 MVE_VPST 4, implicit $vpr183 renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)184 renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2)185 $lr = tMOVr $r3, 14, $noreg186 renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1187 renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14, $noreg188 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg189 renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1190 renamable $lr = t2LoopDec killed renamable $lr, 1191 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr192 tB %bb.3, 14, $noreg193 194 bb.3.middle.block:195 liveins: $q0, $q1, $r2196 197 renamable $vpr = MVE_VCTP32 killed renamable $r2, 0, $noreg, $noreg198 renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr, $noreg199 renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg200 tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0201 202...203