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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve %s -o - | FileCheck %s3 4define <2 x i64> @v2i64(i32 %index, i32 %TC, <2 x i64> %V1, <2 x i64> %V2) {5; CHECK-LABEL: v2i64:6; CHECK: @ %bb.0:7; CHECK-NEXT: push {r4, r5, r6, lr}8; CHECK-NEXT: vmov q1[2], q1[0], r0, r09; CHECK-NEXT: vmov.i64 q0, #0xffffffff10; CHECK-NEXT: vand q1, q1, q011; CHECK-NEXT: movs r5, #012; CHECK-NEXT: vmov r0, r4, d313; CHECK-NEXT: vmov q2[2], q2[0], r1, r114; CHECK-NEXT: vmov lr, r12, d215; CHECK-NEXT: adds r6, r0, #116; CHECK-NEXT: adc r4, r4, #017; CHECK-NEXT: subs.w r0, lr, #-118; CHECK-NEXT: vmov q1[2], q1[0], lr, r619; CHECK-NEXT: sbcs r0, r12, #020; CHECK-NEXT: vmov q1[3], q1[1], r12, r421; CHECK-NEXT: csetm r12, lo22; CHECK-NEXT: subs.w r6, r6, #-123; CHECK-NEXT: bfi r5, r12, #0, #824; CHECK-NEXT: sbcs r6, r4, #025; CHECK-NEXT: mov.w r0, #026; CHECK-NEXT: csetm r6, lo27; CHECK-NEXT: bfi r5, r6, #8, #828; CHECK-NEXT: vmsr p0, r529; CHECK-NEXT: vpsel q1, q1, q030; CHECK-NEXT: vand q0, q2, q031; CHECK-NEXT: vmov r1, r4, d032; CHECK-NEXT: vmov r6, r5, d233; CHECK-NEXT: vmov d0, r2, r334; CHECK-NEXT: subs r1, r6, r135; CHECK-NEXT: sbcs.w r1, r5, r436; CHECK-NEXT: vmov r5, r4, d137; CHECK-NEXT: csetm r1, lo38; CHECK-NEXT: vldr d1, [sp, #16]39; CHECK-NEXT: bfi r0, r1, #0, #840; CHECK-NEXT: vmov r1, r6, d341; CHECK-NEXT: subs r1, r1, r542; CHECK-NEXT: sbcs.w r1, r6, r443; CHECK-NEXT: csetm r1, lo44; CHECK-NEXT: bfi r0, r1, #8, #845; CHECK-NEXT: vmsr p0, r046; CHECK-NEXT: add r0, sp, #2447; CHECK-NEXT: vldrw.u32 q1, [r0]48; CHECK-NEXT: vpsel q0, q0, q149; CHECK-NEXT: vmov r0, r1, d050; CHECK-NEXT: vmov r2, r3, d151; CHECK-NEXT: pop {r4, r5, r6, pc}52 %active.lane.mask = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i32(i32 %index, i32 %TC)53 %select = select <2 x i1> %active.lane.mask, <2 x i64> %V1, <2 x i64> %V254 ret <2 x i64> %select55}56 57define <4 x i32> @v4i32(i32 %index, i32 %TC, <4 x i32> %V1, <4 x i32> %V2) {58; CHECK-LABEL: v4i32:59; CHECK: @ %bb.0:60; CHECK-NEXT: adr.w r12, .LCPI1_061; CHECK-NEXT: vdup.32 q1, r162; CHECK-NEXT: vldrw.u32 q0, [r12]63; CHECK-NEXT: vqadd.u32 q0, q0, r064; CHECK-NEXT: add r0, sp, #865; CHECK-NEXT: vcmp.u32 hi, q1, q066; CHECK-NEXT: vldr d1, [sp]67; CHECK-NEXT: vldrw.u32 q1, [r0]68; CHECK-NEXT: vmov d0, r2, r369; CHECK-NEXT: vpsel q0, q0, q170; CHECK-NEXT: vmov r0, r1, d071; CHECK-NEXT: vmov r2, r3, d172; CHECK-NEXT: bx lr73; CHECK-NEXT: .p2align 474; CHECK-NEXT: @ %bb.1:75; CHECK-NEXT: .LCPI1_0:76; CHECK-NEXT: .long 0 @ 0x077; CHECK-NEXT: .long 1 @ 0x178; CHECK-NEXT: .long 2 @ 0x279; CHECK-NEXT: .long 3 @ 0x380 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %TC)81 %select = select <4 x i1> %active.lane.mask, <4 x i32> %V1, <4 x i32> %V282 ret <4 x i32> %select83}84 85define <7 x i32> @v7i32(i32 %index, i32 %TC, <7 x i32> %V1, <7 x i32> %V2) {86; CHECK-LABEL: v7i32:87; CHECK: @ %bb.0:88; CHECK-NEXT: ldr.w r12, [sp, #40]89; CHECK-NEXT: vdup.32 q3, r290; CHECK-NEXT: ldr r3, [sp, #32]91; CHECK-NEXT: adr r2, .LCPI2_192; CHECK-NEXT: vmov q0[2], q0[0], r3, r1293; CHECK-NEXT: ldr.w r12, [sp, #44]94; CHECK-NEXT: ldr r3, [sp, #36]95; CHECK-NEXT: vmov q0[3], q0[1], r3, r1296; CHECK-NEXT: ldr.w r12, [sp, #8]97; CHECK-NEXT: ldr r3, [sp]98; CHECK-NEXT: vmov q1[2], q1[0], r3, r1299; CHECK-NEXT: ldr.w r12, [sp, #12]100; CHECK-NEXT: ldr r3, [sp, #4]101; CHECK-NEXT: vmov q1[3], q1[1], r3, r12102; CHECK-NEXT: adr r3, .LCPI2_0103; CHECK-NEXT: vldrw.u32 q2, [r3]104; CHECK-NEXT: vqadd.u32 q2, q2, r1105; CHECK-NEXT: vcmp.u32 hi, q3, q2106; CHECK-NEXT: vpsel q0, q1, q0107; CHECK-NEXT: vstrw.32 q0, [r0]108; CHECK-NEXT: vldrw.u32 q0, [r2]109; CHECK-NEXT: ldr r2, [sp, #48]110; CHECK-NEXT: vqadd.u32 q0, q0, r1111; CHECK-NEXT: ldr r1, [sp, #52]112; CHECK-NEXT: vcmp.u32 hi, q3, q0113; CHECK-NEXT: vmov.32 q0[1], r1114; CHECK-NEXT: ldr r1, [sp, #56]115; CHECK-NEXT: vmov q0[2], q0[0], r2, r1116; CHECK-NEXT: ldr r1, [sp, #20]117; CHECK-NEXT: ldr r2, [sp, #16]118; CHECK-NEXT: vmov.32 q1[1], r1119; CHECK-NEXT: ldr r1, [sp, #24]120; CHECK-NEXT: vmov q1[2], q1[0], r2, r1121; CHECK-NEXT: vpsel q0, q1, q0122; CHECK-NEXT: vmov r1, s2123; CHECK-NEXT: vmov.f32 s2, s1124; CHECK-NEXT: vmov r3, s0125; CHECK-NEXT: vmov r2, s2126; CHECK-NEXT: strd r3, r2, [r0, #16]127; CHECK-NEXT: str r1, [r0, #24]128; CHECK-NEXT: bx lr129; CHECK-NEXT: .p2align 4130; CHECK-NEXT: @ %bb.1:131; CHECK-NEXT: .LCPI2_0:132; CHECK-NEXT: .long 0 @ 0x0133; CHECK-NEXT: .long 1 @ 0x1134; CHECK-NEXT: .long 2 @ 0x2135; CHECK-NEXT: .long 3 @ 0x3136; CHECK-NEXT: .LCPI2_1:137; CHECK-NEXT: .long 4 @ 0x4138; CHECK-NEXT: .long 5 @ 0x5139; CHECK-NEXT: .long 6 @ 0x6140; CHECK-NEXT: .zero 4141 %active.lane.mask = call <7 x i1> @llvm.get.active.lane.mask.v7i1.i32(i32 %index, i32 %TC)142 %select = select <7 x i1> %active.lane.mask, <7 x i32> %V1, <7 x i32> %V2143 ret <7 x i32> %select144}145 146define <8 x i16> @v8i16(i32 %index, i32 %TC, <8 x i16> %V1, <8 x i16> %V2) {147; CHECK-LABEL: v8i16:148; CHECK: @ %bb.0:149; CHECK-NEXT: push {r4, lr}150; CHECK-NEXT: sub sp, #16151; CHECK-NEXT: adr.w r12, .LCPI3_0152; CHECK-NEXT: vdup.32 q1, r1153; CHECK-NEXT: vldrw.u32 q0, [r12]154; CHECK-NEXT: vmov.i8 q2, #0xff155; CHECK-NEXT: mov r4, sp156; CHECK-NEXT: adr r1, .LCPI3_1157; CHECK-NEXT: vqadd.u32 q0, q0, r0158; CHECK-NEXT: vcmp.u32 hi, q1, q0159; CHECK-NEXT: vmov.i8 q0, #0x0160; CHECK-NEXT: vpsel q3, q2, q0161; CHECK-NEXT: vstrh.32 q3, [r4, #8]162; CHECK-NEXT: vldrw.u32 q3, [r1]163; CHECK-NEXT: vqadd.u32 q3, q3, r0164; CHECK-NEXT: add r0, sp, #32165; CHECK-NEXT: vcmp.u32 hi, q1, q3166; CHECK-NEXT: vldrw.u32 q1, [r0]167; CHECK-NEXT: vpsel q0, q2, q0168; CHECK-NEXT: vstrh.32 q0, [r4]169; CHECK-NEXT: vldr d1, [sp, #24]170; CHECK-NEXT: vldrw.u32 q2, [r4]171; CHECK-NEXT: vmov d0, r2, r3172; CHECK-NEXT: vcmp.i16 ne, q2, zr173; CHECK-NEXT: vpsel q0, q0, q1174; CHECK-NEXT: vmov r0, r1, d0175; CHECK-NEXT: vmov r2, r3, d1176; CHECK-NEXT: add sp, #16177; CHECK-NEXT: pop {r4, pc}178; CHECK-NEXT: .p2align 4179; CHECK-NEXT: @ %bb.1:180; CHECK-NEXT: .LCPI3_0:181; CHECK-NEXT: .long 4 @ 0x4182; CHECK-NEXT: .long 5 @ 0x5183; CHECK-NEXT: .long 6 @ 0x6184; CHECK-NEXT: .long 7 @ 0x7185; CHECK-NEXT: .LCPI3_1:186; CHECK-NEXT: .long 0 @ 0x0187; CHECK-NEXT: .long 1 @ 0x1188; CHECK-NEXT: .long 2 @ 0x2189; CHECK-NEXT: .long 3 @ 0x3190 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %TC)191 %select = select <8 x i1> %active.lane.mask, <8 x i16> %V1, <8 x i16> %V2192 ret <8 x i16> %select193}194 195define <16 x i8> @v16i8(i32 %index, i32 %TC, <16 x i8> %V1, <16 x i8> %V2) {196; CHECK-LABEL: v16i8:197; CHECK: @ %bb.0:198; CHECK-NEXT: push {r4, r5, r7, lr}199; CHECK-NEXT: sub sp, #48200; CHECK-NEXT: adr.w r12, .LCPI4_0201; CHECK-NEXT: vdup.32 q2, r1202; CHECK-NEXT: vldrw.u32 q0, [r12]203; CHECK-NEXT: vmov.i8 q1, #0xff204; CHECK-NEXT: add r5, sp, #16205; CHECK-NEXT: adr r1, .LCPI4_1206; CHECK-NEXT: vqadd.u32 q0, q0, r0207; CHECK-NEXT: adr r4, .LCPI4_3208; CHECK-NEXT: vcmp.u32 hi, q2, q0209; CHECK-NEXT: vmov.i8 q0, #0x0210; CHECK-NEXT: vpsel q3, q1, q0211; CHECK-NEXT: vstrh.32 q3, [r5, #8]212; CHECK-NEXT: vldrw.u32 q3, [r1]213; CHECK-NEXT: adr r1, .LCPI4_2214; CHECK-NEXT: vqadd.u32 q3, q3, r0215; CHECK-NEXT: vcmp.u32 hi, q2, q3216; CHECK-NEXT: vpsel q3, q1, q0217; CHECK-NEXT: vstrh.32 q3, [r5]218; CHECK-NEXT: vldrw.u32 q3, [r1]219; CHECK-NEXT: mov r1, sp220; CHECK-NEXT: vqadd.u32 q3, q3, r0221; CHECK-NEXT: vcmp.u32 hi, q2, q3222; CHECK-NEXT: vpsel q3, q1, q0223; CHECK-NEXT: vstrh.32 q3, [r1, #8]224; CHECK-NEXT: vldrw.u32 q3, [r4]225; CHECK-NEXT: vqadd.u32 q3, q3, r0226; CHECK-NEXT: add r0, sp, #32227; CHECK-NEXT: vcmp.u32 hi, q2, q3228; CHECK-NEXT: vpsel q2, q1, q0229; CHECK-NEXT: vstrh.32 q2, [r1]230; CHECK-NEXT: vldrw.u32 q2, [r5]231; CHECK-NEXT: vcmp.i16 ne, q2, zr232; CHECK-NEXT: vpsel q2, q1, q0233; CHECK-NEXT: vstrb.16 q2, [r0, #8]234; CHECK-NEXT: vldrw.u32 q2, [r1]235; CHECK-NEXT: add r1, sp, #72236; CHECK-NEXT: vcmp.i16 ne, q2, zr237; CHECK-NEXT: vpsel q0, q1, q0238; CHECK-NEXT: vldrw.u32 q1, [r1]239; CHECK-NEXT: vstrb.16 q0, [r0]240; CHECK-NEXT: vldr d1, [sp, #64]241; CHECK-NEXT: vldrw.u32 q2, [r0]242; CHECK-NEXT: vmov d0, r2, r3243; CHECK-NEXT: vcmp.i8 ne, q2, zr244; CHECK-NEXT: vpsel q0, q0, q1245; CHECK-NEXT: vmov r0, r1, d0246; CHECK-NEXT: vmov r2, r3, d1247; CHECK-NEXT: add sp, #48248; CHECK-NEXT: pop {r4, r5, r7, pc}249; CHECK-NEXT: .p2align 4250; CHECK-NEXT: @ %bb.1:251; CHECK-NEXT: .LCPI4_0:252; CHECK-NEXT: .long 12 @ 0xc253; CHECK-NEXT: .long 13 @ 0xd254; CHECK-NEXT: .long 14 @ 0xe255; CHECK-NEXT: .long 15 @ 0xf256; CHECK-NEXT: .LCPI4_1:257; CHECK-NEXT: .long 8 @ 0x8258; CHECK-NEXT: .long 9 @ 0x9259; CHECK-NEXT: .long 10 @ 0xa260; CHECK-NEXT: .long 11 @ 0xb261; CHECK-NEXT: .LCPI4_2:262; CHECK-NEXT: .long 4 @ 0x4263; CHECK-NEXT: .long 5 @ 0x5264; CHECK-NEXT: .long 6 @ 0x6265; CHECK-NEXT: .long 7 @ 0x7266; CHECK-NEXT: .LCPI4_3:267; CHECK-NEXT: .long 0 @ 0x0268; CHECK-NEXT: .long 1 @ 0x1269; CHECK-NEXT: .long 2 @ 0x2270; CHECK-NEXT: .long 3 @ 0x3271 %active.lane.mask = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 %index, i32 %TC)272 %select = select <16 x i1> %active.lane.mask, <16 x i8> %V1, <16 x i8> %V2273 ret <16 x i8> %select274}275 276define void @test_width2(ptr nocapture readnone %x, ptr nocapture %y, i8 zeroext %m) {277; CHECK-LABEL: test_width2:278; CHECK: @ %bb.0: @ %entry279; CHECK-NEXT: push {r7, lr}280; CHECK-NEXT: sub sp, #4281; CHECK-NEXT: cmp r2, #0282; CHECK-NEXT: beq .LBB5_3283; CHECK-NEXT: @ %bb.1: @ %for.body.preheader284; CHECK-NEXT: adds r0, r2, #1285; CHECK-NEXT: movs r3, #1286; CHECK-NEXT: bic r0, r0, #1287; CHECK-NEXT: subs r0, #2288; CHECK-NEXT: add.w r0, r3, r0, lsr #1289; CHECK-NEXT: dls lr, r0290; CHECK-NEXT: .LBB5_2: @ %vector.body291; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1292; CHECK-NEXT: vctp.64 r2293; CHECK-NEXT: @ implicit-def: $q0294; CHECK-NEXT: subs r2, #2295; CHECK-NEXT: vmrs r3, p0296; CHECK-NEXT: and r0, r3, #1297; CHECK-NEXT: ubfx r3, r3, #8, #1298; CHECK-NEXT: rsb.w r12, r0, #0299; CHECK-NEXT: movs r0, #0300; CHECK-NEXT: rsbs r3, r3, #0301; CHECK-NEXT: bfi r0, r12, #0, #1302; CHECK-NEXT: sub.w r12, r1, #8303; CHECK-NEXT: bfi r0, r3, #1, #1304; CHECK-NEXT: lsls r3, r0, #31305; CHECK-NEXT: itt ne306; CHECK-NEXT: ldrne.w r3, [r12]307; CHECK-NEXT: vmovne.32 q0[0], r3308; CHECK-NEXT: lsls r0, r0, #30309; CHECK-NEXT: itt mi310; CHECK-NEXT: ldrmi.w r0, [r12, #4]311; CHECK-NEXT: vmovmi.32 q0[2], r0312; CHECK-NEXT: vmrs r3, p0313; CHECK-NEXT: and r0, r3, #1314; CHECK-NEXT: ubfx r3, r3, #8, #1315; CHECK-NEXT: rsb.w r12, r0, #0316; CHECK-NEXT: movs r0, #0317; CHECK-NEXT: rsbs r3, r3, #0318; CHECK-NEXT: bfi r0, r12, #0, #1319; CHECK-NEXT: bfi r0, r3, #1, #1320; CHECK-NEXT: lsls r3, r0, #31321; CHECK-NEXT: itt ne322; CHECK-NEXT: vmovne r3, s0323; CHECK-NEXT: strne r3, [r1]324; CHECK-NEXT: lsls r0, r0, #30325; CHECK-NEXT: itt mi326; CHECK-NEXT: vmovmi r0, s2327; CHECK-NEXT: strmi r0, [r1, #4]328; CHECK-NEXT: adds r1, #8329; CHECK-NEXT: le lr, .LBB5_2330; CHECK-NEXT: .LBB5_3: @ %for.cond.cleanup331; CHECK-NEXT: add sp, #4332; CHECK-NEXT: pop {r7, pc}333entry:334 %cmp9.not = icmp eq i8 %m, 0335 br i1 %cmp9.not, label %for.cond.cleanup, label %for.body.preheader336 337for.body.preheader: ; preds = %entry338 %wide.trip.count = zext i8 %m to i32339 %n.rnd.up = add nuw nsw i32 %wide.trip.count, 1340 %n.vec = and i32 %n.rnd.up, 510341 br label %vector.body342 343vector.body: ; preds = %vector.body, %for.body.preheader344 %index = phi i32 [ 0, %for.body.preheader ], [ %index.next, %vector.body ]345 %active.lane.mask = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i32(i32 %index, i32 %wide.trip.count)346 %0 = add nsw i32 %index, -2347 %1 = getelementptr inbounds i32, ptr %y, i32 %0348 %wide.masked.load = call <2 x i32> @llvm.masked.load.v2i32.p0(ptr %1, i32 4, <2 x i1> %active.lane.mask, <2 x i32> undef)349 %2 = getelementptr inbounds i32, ptr %y, i32 %index350 call void @llvm.masked.store.v2i32.p0(<2 x i32> %wide.masked.load, ptr %2, i32 4, <2 x i1> %active.lane.mask)351 %index.next = add i32 %index, 2352 %3 = icmp eq i32 %index.next, %n.vec353 br i1 %3, label %for.cond.cleanup, label %vector.body354 355for.cond.cleanup: ; preds = %vector.body, %entry356 ret void357}358 359declare <2 x i1> @llvm.get.active.lane.mask.v2i1.i32(i32, i32)360declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)361declare <7 x i1> @llvm.get.active.lane.mask.v7i1.i32(i32, i32)362declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32)363declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32, i32)364declare <2 x i32> @llvm.masked.load.v2i32.p0(ptr, i32, <2 x i1>, <2 x i32>)365declare void @llvm.masked.store.v2i32.p0(<2 x i32>, ptr, i32, <2 x i1>)366