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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv7m-eabi %s -o - | FileCheck %s3 4; Check that each outlining candidate and the outlined function are in agreement5; with regard to whether BTI insertion is enabled or not.6 7; volatile int a, b, c, d, e, f;8;9; int x(int p) {10; int r = (a + b) / (c + d) * e + f;11; return r + 1;12; }13;14; __attribute__((target("branch-protection=none")))15; int y(int p) {16; int r = (a + b) / (c + d) * e + f;17; return r + 2;18; }19;20; __attribute__((target("branch-protection=bti")))21; int z(int p) {22; int r = (a + b) / (c + d) * e + f;23; return r + 3;24; }25 26@a = hidden global i32 0, align 427@b = hidden global i32 0, align 428@c = hidden global i32 0, align 429@d = hidden global i32 0, align 430@e = hidden global i32 0, align 431@f = hidden global i32 0, align 432 33define hidden i32 @x(i32 %p) local_unnamed_addr #0 {34; CHECK-LABEL: x:35; CHECK: @ %bb.0: @ %entry36; CHECK-NEXT: ldr r0, .LCPI0_037; CHECK-NEXT: .save {lr}38; CHECK-NEXT: str lr, [sp, #-8]!39; CHECK-NEXT: bl OUTLINED_FUNCTION_040; CHECK-NEXT: ldr lr, [sp], #841; CHECK-NEXT: adds r0, #142; CHECK-NEXT: bx lr43; CHECK-NEXT: .p2align 244; CHECK-NEXT: @ %bb.1:45; CHECK-NEXT: .LCPI0_0:46; CHECK-NEXT: .long .L_MergedGlobals47entry:48 %0 = load volatile i32, ptr @a, align 449 %1 = load volatile i32, ptr @b, align 450 %add = add nsw i32 %1, %051 %2 = load volatile i32, ptr @c, align 452 %3 = load volatile i32, ptr @d, align 453 %add1 = add nsw i32 %3, %254 %div = sdiv i32 %add, %add155 %4 = load volatile i32, ptr @e, align 456 %mul = mul nsw i32 %4, %div57 %5 = load volatile i32, ptr @f, align 458 %add2 = add nsw i32 %mul, %559 %add3 = add nsw i32 %add2, 160 ret i32 %add361}62 63define hidden i32 @y(i32 %p) local_unnamed_addr #0 {64; CHECK-LABEL: y:65; CHECK: @ %bb.0: @ %entry66; CHECK-NEXT: ldr r0, .LCPI1_067; CHECK-NEXT: .save {lr}68; CHECK-NEXT: str lr, [sp, #-8]!69; CHECK-NEXT: bl OUTLINED_FUNCTION_070; CHECK-NEXT: ldr lr, [sp], #871; CHECK-NEXT: adds r0, #272; CHECK-NEXT: bx lr73; CHECK-NEXT: .p2align 274; CHECK-NEXT: @ %bb.1:75; CHECK-NEXT: .LCPI1_0:76; CHECK-NEXT: .long .L_MergedGlobals77entry:78 %0 = load volatile i32, ptr @a, align 479 %1 = load volatile i32, ptr @b, align 480 %add = add nsw i32 %1, %081 %2 = load volatile i32, ptr @c, align 482 %3 = load volatile i32, ptr @d, align 483 %add1 = add nsw i32 %3, %284 %div = sdiv i32 %add, %add185 %4 = load volatile i32, ptr @e, align 486 %mul = mul nsw i32 %4, %div87 %5 = load volatile i32, ptr @f, align 488 %add2 = add nsw i32 %mul, %589 %add3 = add nsw i32 %add2, 290 ret i32 %add391}92 93define hidden i32 @z(i32 %p) local_unnamed_addr #1 {94; CHECK-LABEL: z:95; CHECK: @ %bb.0: @ %entry96; CHECK-NEXT: bti97; CHECK-NEXT: ldr r0, .LCPI2_098; CHECK-NEXT: ldr r1, [r0]99; CHECK-NEXT: ldr r2, [r0, #4]100; CHECK-NEXT: add r1, r2101; CHECK-NEXT: ldr r2, [r0, #8]102; CHECK-NEXT: ldr r3, [r0, #12]103; CHECK-NEXT: add r2, r3104; CHECK-NEXT: sdiv r1, r1, r2105; CHECK-NEXT: ldr r2, [r0, #16]106; CHECK-NEXT: ldr r0, [r0, #20]107; CHECK-NEXT: mla r0, r2, r1, r0108; CHECK-NEXT: adds r0, #3109; CHECK-NEXT: bx lr110; CHECK-NEXT: .p2align 2111; CHECK-NEXT: @ %bb.1:112; CHECK-NEXT: .LCPI2_0:113; CHECK-NEXT: .long .L_MergedGlobals114entry:115 %0 = load volatile i32, ptr @a, align 4116 %1 = load volatile i32, ptr @b, align 4117 %add = add nsw i32 %1, %0118 %2 = load volatile i32, ptr @c, align 4119 %3 = load volatile i32, ptr @d, align 4120 %add1 = add nsw i32 %3, %2121 %div = sdiv i32 %add, %add1122 %4 = load volatile i32, ptr @e, align 4123 %mul = mul nsw i32 %4, %div124 %5 = load volatile i32, ptr @f, align 4125 %add2 = add nsw i32 %mul, %5126 %add3 = add nsw i32 %add2, 3127 ret i32 %add3128}129 130attributes #0 = { minsize nofree norecurse nounwind optsize }131attributes #1 = { minsize nofree norecurse nounwind optsize "branch-target-enforcement" }132 133!llvm.module.flags = !{!0}134 135!0 = !{i32 8, !"branch-target-enforcement", i32 0}136