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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 62; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s3 4define i64 @f1(i64 %a, i64 %b) {5; CHECK-LABEL: f1:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: subs r0, r0, r28; CHECK-NEXT: sbcs r1, r39; CHECK-NEXT: bx lr10entry:11 %tmp = sub i64 %a, %b12 ret i64 %tmp13}14 15define i64 @f2(i64 %a, i64 %b) {16; CHECK-LABEL: f2:17; CHECK: @ %bb.0: @ %entry18; CHECK-NEXT: lsls r1, r1, #119; CHECK-NEXT: orr.w r1, r1, r0, lsr #3120; CHECK-NEXT: rsbs r0, r2, r0, lsl #121; CHECK-NEXT: sbcs r1, r322; CHECK-NEXT: bx lr23entry:24 %tmp1 = shl i64 %a, 125 %tmp2 = sub i64 %tmp1, %b26 ret i64 %tmp227}28 29; rdar://1255938530define i64 @f3(i32 %vi) {31; CHECK-LABEL: f3:32; CHECK: @ %bb.0: @ %entry33; CHECK-NEXT: movw r1, #1949334; CHECK-NEXT: movt r1, #5719135; CHECK-NEXT: eors r0, r136; CHECK-NEXT: movw r2, #2943337; CHECK-NEXT: movw r3, #4604338; CHECK-NEXT: movw r1, #3610239; CHECK-NEXT: movt r2, #6553540; CHECK-NEXT: adds r0, r0, r041; CHECK-NEXT: movt r3, #834442; CHECK-NEXT: sbcs r2, r143; CHECK-NEXT: adds r0, r0, r344; CHECK-NEXT: adcs r1, r245; CHECK-NEXT: bx lr46entry:47 %v0 = zext i32 %vi to i6448 %v1 = xor i64 %v0, -15505745619861949 %v4 = add i64 %v1, 15505745619861950 %v5 = add i64 %v4, %v151 ret i64 %v552}53