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1; RUN: llc -mtriple=thumbv8.1m.main -mattr=+cdecp0 -mattr=+cdecp1 -mattr=+mve -verify-machineinstrs -o - %s | FileCheck %s2; RUN: llc -mtriple=thumbv8m.main -mattr=+cdecp0 -mattr=+cdecp1 -mattr=+fp-armv8d16sp -verify-machineinstrs -o - %s | FileCheck %s3 4declare float @llvm.arm.cde.vcx1.f32(i32 immarg, i32 immarg)5declare float @llvm.arm.cde.vcx1a.f32(i32 immarg, float, i32 immarg)6declare float @llvm.arm.cde.vcx2.f32(i32 immarg, float, i32 immarg)7declare float @llvm.arm.cde.vcx2a.f32(i32 immarg, float, float, i32 immarg)8declare float @llvm.arm.cde.vcx3.f32(i32 immarg, float, float, i32 immarg)9declare float @llvm.arm.cde.vcx3a.f32(i32 immarg, float, float, float, i32 immarg)10 11declare double @llvm.arm.cde.vcx1.f64(i32 immarg, i32 immarg)12declare double @llvm.arm.cde.vcx1a.f64(i32 immarg, double, i32 immarg)13declare double @llvm.arm.cde.vcx2.f64(i32 immarg, double, i32 immarg)14declare double @llvm.arm.cde.vcx2a.f64(i32 immarg, double, double, i32 immarg)15declare double @llvm.arm.cde.vcx3.f64(i32 immarg, double, double, i32 immarg)16declare double @llvm.arm.cde.vcx3a.f64(i32 immarg, double, double, double, i32 immarg)17 18define arm_aapcs_vfpcc i32 @test_vcx1_u32() {19; CHECK-LABEL: test_vcx1_u32:20; CHECK: @ %bb.0: @ %entry21; CHECK-NEXT: vcx1 p0, s0, #1122; CHECK-NEXT: vmov r0, s023; CHECK-NEXT: bx lr24entry:25 %0 = call float @llvm.arm.cde.vcx1.f32(i32 0, i32 11)26 %1 = bitcast float %0 to i3227 ret i32 %128}29 30define arm_aapcs_vfpcc i32 @test_vcx1a_u32(i32 %acc) {31; CHECK-LABEL: test_vcx1a_u32:32; CHECK: @ %bb.0: @ %entry33; CHECK-NEXT: vmov s0, r034; CHECK-NEXT: vcx1a p1, s0, #1235; CHECK-NEXT: vmov r0, s036; CHECK-NEXT: bx lr37entry:38 %0 = bitcast i32 %acc to float39 %1 = call float @llvm.arm.cde.vcx1a.f32(i32 1, float %0, i32 12)40 %2 = bitcast float %1 to i3241 ret i32 %242}43 44define arm_aapcs_vfpcc i32 @test_vcx2_u32(i32 %n) {45; CHECK-LABEL: test_vcx2_u32:46; CHECK: @ %bb.0: @ %entry47; CHECK-NEXT: vmov s0, r048; CHECK-NEXT: vcx2 p0, s0, s0, #2149; CHECK-NEXT: vmov r0, s050; CHECK-NEXT: bx lr51entry:52 %0 = bitcast i32 %n to float53 %1 = call float @llvm.arm.cde.vcx2.f32(i32 0, float %0, i32 21)54 %2 = bitcast float %1 to i3255 ret i32 %256}57 58define arm_aapcs_vfpcc i32 @test_vcx2a_u32(i32 %acc, i32 %n) {59; CHECK-LABEL: test_vcx2a_u32:60; CHECK: @ %bb.0: @ %entry61; CHECK-NEXT: vmov s0, r162; CHECK-NEXT: vmov s2, r063; CHECK-NEXT: vcx2a p0, s2, s0, #2264; CHECK-NEXT: vmov r0, s265; CHECK-NEXT: bx lr66entry:67 %0 = bitcast i32 %acc to float68 %1 = bitcast i32 %n to float69 %2 = call float @llvm.arm.cde.vcx2a.f32(i32 0, float %0, float %1, i32 22)70 %3 = bitcast float %2 to i3271 ret i32 %372}73 74define arm_aapcs_vfpcc i32 @test_vcx3_u32(i32 %n, i32 %m) {75; CHECK-LABEL: test_vcx3_u32:76; CHECK: @ %bb.0: @ %entry77; CHECK-NEXT: vmov s0, r178; CHECK-NEXT: vmov s2, r079; CHECK-NEXT: vcx3 p1, s0, s2, s0, #380; CHECK-NEXT: vmov r0, s081; CHECK-NEXT: bx lr82entry:83 %0 = bitcast i32 %n to float84 %1 = bitcast i32 %m to float85 %2 = call float @llvm.arm.cde.vcx3.f32(i32 1, float %0, float %1, i32 3)86 %3 = bitcast float %2 to i3287 ret i32 %388}89 90define arm_aapcs_vfpcc i32 @test_vcx3a_u32(i32 %acc, i32 %n, i32 %m) {91; CHECK-LABEL: test_vcx3a_u32:92; CHECK: @ %bb.0: @ %entry93; CHECK-NEXT: vmov s0, r294; CHECK-NEXT: vmov s2, r195; CHECK-NEXT: vmov s4, r096; CHECK-NEXT: vcx3a p0, s4, s2, s0, #597; CHECK-NEXT: vmov r0, s498; CHECK-NEXT: bx lr99entry:100 %0 = bitcast i32 %acc to float101 %1 = bitcast i32 %n to float102 %2 = bitcast i32 %m to float103 %3 = call float @llvm.arm.cde.vcx3a.f32(i32 0, float %0, float %1, float %2, i32 5)104 %4 = bitcast float %3 to i32105 ret i32 %4106}107 108define arm_aapcs_vfpcc i64 @test_vcx1d_u64() {109; CHECK-LABEL: test_vcx1d_u64:110; CHECK: @ %bb.0: @ %entry111; CHECK-NEXT: vcx1 p0, d0, #11112; CHECK-NEXT: vmov r0, r1, d0113; CHECK-NEXT: bx lr114entry:115 %0 = call double @llvm.arm.cde.vcx1.f64(i32 0, i32 11)116 %1 = bitcast double %0 to i64117 ret i64 %1118}119 120define arm_aapcs_vfpcc i64 @test_vcx1da_u64(i64 %acc) {121; CHECK-LABEL: test_vcx1da_u64:122; CHECK: @ %bb.0: @ %entry123; CHECK-NEXT: vmov d0, r0, r1124; CHECK-NEXT: vcx1a p1, d0, #12125; CHECK-NEXT: vmov r0, r1, d0126; CHECK-NEXT: bx lr127entry:128 %0 = bitcast i64 %acc to double129 %1 = call double @llvm.arm.cde.vcx1a.f64(i32 1, double %0, i32 12)130 %2 = bitcast double %1 to i64131 ret i64 %2132}133 134define arm_aapcs_vfpcc i64 @test_vcx2d_u64(i64 %n) {135; CHECK-LABEL: test_vcx2d_u64:136; CHECK: @ %bb.0: @ %entry137; CHECK-NEXT: vmov d0, r0, r1138; CHECK-NEXT: vcx2 p0, d0, d0, #21139; CHECK-NEXT: vmov r0, r1, d0140; CHECK-NEXT: bx lr141entry:142 %0 = bitcast i64 %n to double143 %1 = call double @llvm.arm.cde.vcx2.f64(i32 0, double %0, i32 21)144 %2 = bitcast double %1 to i64145 ret i64 %2146}147 148define arm_aapcs_vfpcc i64 @test_vcx2da_u64(i64 %acc, i64 %n) {149; CHECK-LABEL: test_vcx2da_u64:150; CHECK: @ %bb.0: @ %entry151; CHECK-NEXT: vmov d0, r2, r3152; CHECK-NEXT: vmov d1, r0, r1153; CHECK-NEXT: vcx2a p0, d1, d0, #22154; CHECK-NEXT: vmov r0, r1, d1155; CHECK-NEXT: bx lr156entry:157 %0 = bitcast i64 %acc to double158 %1 = bitcast i64 %n to double159 %2 = call double @llvm.arm.cde.vcx2a.f64(i32 0, double %0, double %1, i32 22)160 %3 = bitcast double %2 to i64161 ret i64 %3162}163 164define arm_aapcs_vfpcc i64 @test_vcx3d_u64(i64 %n, i64 %m) {165; CHECK-LABEL: test_vcx3d_u64:166; CHECK: @ %bb.0: @ %entry167; CHECK-NEXT: vmov d0, r2, r3168; CHECK-NEXT: vmov d1, r0, r1169; CHECK-NEXT: vcx3 p1, d0, d1, d0, #3170; CHECK-NEXT: vmov r0, r1, d0171; CHECK-NEXT: bx lr172entry:173 %0 = bitcast i64 %n to double174 %1 = bitcast i64 %m to double175 %2 = call double @llvm.arm.cde.vcx3.f64(i32 1, double %0, double %1, i32 3)176 %3 = bitcast double %2 to i64177 ret i64 %3178}179 180define arm_aapcs_vfpcc i64 @test_vcx3da_u64(i64 %acc, i64 %n, i64 %m) {181; CHECK-LABEL: test_vcx3da_u64:182; CHECK: @ %bb.0: @ %entry183; CHECK-NEXT: push {r7, lr}184; CHECK-NEXT: ldrd lr, r12, [sp, #8]185; CHECK-DAG: vmov [[D0:d.*]], r0, r1186; CHECK-DAG: vmov [[D1:d.*]], r2, r3187; CHECK-DAG: vmov [[D2:d.*]], lr, r12188; CHECK-NEXT: vcx3a p0, [[D0]], [[D1]], [[D2]], #5189; CHECK-NEXT: vmov r0, r1, [[D0]]190; CHECK-NEXT: pop {r7, pc}191entry:192 %0 = bitcast i64 %acc to double193 %1 = bitcast i64 %n to double194 %2 = bitcast i64 %m to double195 %3 = call double @llvm.arm.cde.vcx3a.f64(i32 0, double %0, double %1, double %2, i32 5)196 %4 = bitcast double %3 to i64197 ret i64 %4198}199