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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs < %s -mtriple=thumbv8.1m.main-none-eabi | FileCheck %s3 4define i32 @ori32i32_eq(i32 %x, i32 %y) {5; CHECK-LABEL: ori32i32_eq:6; CHECK: @ %bb.0:7; CHECK-NEXT: and r0, r0, #18; CHECK-NEXT: cmp r1, #09; CHECK-NEXT: csinc r0, r0, zr, ne10; CHECK-NEXT: bx lr11 %xa = and i32 %x, 112 %c = icmp eq i32 %y, 013 %cz = zext i1 %c to i3214 %a = or i32 %xa, %cz15 ret i32 %a16}17 18define i32 @ori32_eq_c(i32 %x, i32 %y) {19; CHECK-LABEL: ori32_eq_c:20; CHECK: @ %bb.0:21; CHECK-NEXT: and r0, r0, #122; CHECK-NEXT: cmp r1, #023; CHECK-NEXT: csinc r0, r0, zr, ne24; CHECK-NEXT: bx lr25 %xa = and i32 %x, 126 %c = icmp eq i32 %y, 027 %cz = zext i1 %c to i3228 %a = or i32 %cz, %xa29 ret i32 %a30}31 32define i32 @ori32i64_eq(i32 %x, i64 %y) {33; CHECK-LABEL: ori32i64_eq:34; CHECK: @ %bb.0:35; CHECK-NEXT: orrs.w r1, r2, r336; CHECK-NEXT: and r0, r0, #137; CHECK-NEXT: csinc r0, r0, zr, ne38; CHECK-NEXT: bx lr39 %xa = and i32 %x, 140 %c = icmp eq i64 %y, 041 %cz = zext i1 %c to i3242 %a = or i32 %xa, %cz43 ret i32 %a44}45 46define i32 @ori32_sgt(i32 %x, i32 %y) {47; CHECK-LABEL: ori32_sgt:48; CHECK: @ %bb.0:49; CHECK-NEXT: and r0, r0, #150; CHECK-NEXT: cmp r1, #051; CHECK-NEXT: csinc r0, r0, zr, le52; CHECK-NEXT: bx lr53 %xa = and i32 %x, 154 %c = icmp sgt i32 %y, 055 %cz = zext i1 %c to i3256 %a = or i32 %xa, %cz57 ret i32 %a58}59 60; Negative test - too many demanded bits61define i32 @ori32_toomanybits(i32 %x, i32 %y) {62; CHECK-LABEL: ori32_toomanybits:63; CHECK: @ %bb.0:64; CHECK-NEXT: and r0, r0, #365; CHECK-NEXT: cmp r1, #066; CHECK-NEXT: it eq67; CHECK-NEXT: orreq r0, r0, #168; CHECK-NEXT: bx lr69 %xa = and i32 %x, 370 %c = icmp eq i32 %y, 071 %cz = zext i1 %c to i3272 %a = or i32 %xa, %cz73 ret i32 %a74}75 76define i32 @andi32_ne(i8 %x, i8 %y) {77; CHECK-LABEL: andi32_ne:78; CHECK: @ %bb.0:79; CHECK-NEXT: tst.w r0, #25580; CHECK-NEXT: cset r0, eq81; CHECK-NEXT: tst.w r1, #25582; CHECK-NEXT: csel r0, zr, r0, eq83; CHECK-NEXT: bx lr84 %xc = icmp eq i8 %x, 085 %xa = zext i1 %xc to i3286 %c = icmp ne i8 %y, 087 %cz = zext i1 %c to i3288 %a = and i32 %xa, %cz89 ret i32 %a90}91 92define i32 @andi32_sgt(i8 %x, i8 %y) {93; CHECK-LABEL: andi32_sgt:94; CHECK: @ %bb.0:95; CHECK-NEXT: tst.w r0, #25596; CHECK-NEXT: sxtb r1, r197; CHECK-NEXT: cset r0, eq98; CHECK-NEXT: cmp r1, #099; CHECK-NEXT: csel r0, zr, r0, le100; CHECK-NEXT: bx lr101 %xc = icmp eq i8 %x, 0102 %xa = zext i1 %xc to i32103 %c = icmp sgt i8 %y, 0104 %cz = zext i1 %c to i32105 %a = and i32 %xa, %cz106 ret i32 %a107}108 109define i64 @ori64i32_eq(i64 %x, i32 %y) {110; CHECK-LABEL: ori64i32_eq:111; CHECK: @ %bb.0:112; CHECK-NEXT: cmp r2, #0113; CHECK-NEXT: and r0, r0, #1114; CHECK-NEXT: cset r1, eq115; CHECK-NEXT: orrs r0, r1116; CHECK-NEXT: movs r1, #0117; CHECK-NEXT: bx lr118 %xa = and i64 %x, 1119 %c = icmp eq i32 %y, 0120 %cz = zext i1 %c to i64121 %a = or i64 %xa, %cz122 ret i64 %a123}124 125define i64 @ori64i64_eq(i64 %x, i64 %y) {126; CHECK-LABEL: ori64i64_eq:127; CHECK: @ %bb.0:128; CHECK-NEXT: orrs.w r1, r2, r3129; CHECK-NEXT: and r0, r0, #1130; CHECK-NEXT: cset r1, eq131; CHECK-NEXT: orrs r0, r1132; CHECK-NEXT: movs r1, #0133; CHECK-NEXT: bx lr134 %xa = and i64 %x, 1135 %c = icmp eq i64 %y, 0136 %cz = zext i1 %c to i64137 %a = or i64 %xa, %cz138 ret i64 %a139}140 141define i64 @ori64_eq_c(i64 %x, i32 %y) {142; CHECK-LABEL: ori64_eq_c:143; CHECK: @ %bb.0:144; CHECK-NEXT: cmp r2, #0145; CHECK-NEXT: and r0, r0, #1146; CHECK-NEXT: cset r1, eq147; CHECK-NEXT: orrs r0, r1148; CHECK-NEXT: movs r1, #0149; CHECK-NEXT: bx lr150 %xa = and i64 %x, 1151 %c = icmp eq i32 %y, 0152 %cz = zext i1 %c to i64153 %a = or i64 %cz, %xa154 ret i64 %a155}156 157define i64 @andi64_ne(i8 %x, i8 %y) {158; CHECK-LABEL: andi64_ne:159; CHECK: @ %bb.0:160; CHECK-NEXT: tst.w r0, #255161; CHECK-NEXT: cset r0, eq162; CHECK-NEXT: tst.w r1, #255163; CHECK-NEXT: csel r0, zr, r0, eq164; CHECK-NEXT: movs r1, #0165; CHECK-NEXT: bx lr166 %xc = icmp eq i8 %x, 0167 %xa = zext i1 %xc to i64168 %c = icmp ne i8 %y, 0169 %cz = zext i1 %c to i64170 %a = and i64 %xa, %cz171 ret i64 %a172}173 174; Check for multiple uses on the csinc175define i32 @t5(i32 %f.0, i32 %call) {176; CHECK-LABEL: t5:177; CHECK: @ %bb.0: @ %entry178; CHECK-NEXT: cmp r1, #0179; CHECK-NEXT: cset r1, ne180; CHECK-NEXT: cmp r0, #13181; CHECK-NEXT: cset r0, eq182; CHECK-NEXT: and.w r2, r0, r1183; CHECK-NEXT: orrs r0, r1184; CHECK-NEXT: eor r0, r0, #1185; CHECK-NEXT: orrs r0, r2186; CHECK-NEXT: bx lr187entry:188 %tobool1.i = icmp ne i32 %call, 0189 %cmp = icmp eq i32 %f.0, 13190 %or.cond = select i1 %cmp, i1 %tobool1.i, i1 false191 %or.cond7.not = select i1 %cmp, i1 true, i1 %tobool1.i192 %or.cond7.not.not = xor i1 %or.cond7.not, true193 %not.or.cond12 = select i1 %or.cond, i1 true, i1 %or.cond7.not.not194 %g.0 = zext i1 %not.or.cond12 to i32195 ret i32 %g.0196}197 198define i32 @test(i32 %a, i32 %b) {199; CHECK-LABEL: test:200; CHECK: @ %bb.0: @ %entry201; CHECK-NEXT: movs r2, #1202; CHECK-NEXT: cmp r1, r0203; CHECK-NEXT: lsr.w r2, r2, r1204; CHECK-NEXT: csinc r0, r2, zr, le205; CHECK-NEXT: bx lr206entry:207 %cmp = icmp sgt i32 %b, %a208 %b.op = lshr i32 1, %b209 %shr = select i1 %cmp, i32 1, i32 %b.op210 ret i32 %shr211}212 213