382 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi %s -verify-machineinstrs -o - | FileCheck %s3 4define i32 @csinc_const_65(i32 %a) {5; CHECK-LABEL: csinc_const_65:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: movs r1, #58; CHECK-NEXT: cmp r0, #459; CHECK-NEXT: cinc r0, r1, gt10; CHECK-NEXT: bx lr11entry:12 %cmp = icmp sgt i32 %a, 4513 %spec.select = select i1 %cmp, i32 6, i32 514 ret i32 %spec.select15}16 17define i32 @csinc_const_56(i32 %a) {18; CHECK-LABEL: csinc_const_56:19; CHECK: @ %bb.0: @ %entry20; CHECK-NEXT: movs r1, #521; CHECK-NEXT: cmp r0, #4522; CHECK-NEXT: cinc r0, r1, le23; CHECK-NEXT: bx lr24entry:25 %cmp = icmp sgt i32 %a, 4526 %spec.select = select i1 %cmp, i32 5, i32 627 ret i32 %spec.select28}29 30define i32 @csinc_const_zext(i32 %a) {31; CHECK-LABEL: csinc_const_zext:32; CHECK: @ %bb.0: @ %entry33; CHECK-NEXT: cmp r0, #4534; CHECK-NEXT: cset r0, gt35; CHECK-NEXT: bx lr36entry:37 %cmp = icmp sgt i32 %a, 4538 %spec.select = zext i1 %cmp to i3239 ret i32 %spec.select40}41 42define i32 @csinv_const_56(i32 %a) {43; CHECK-LABEL: csinv_const_56:44; CHECK: @ %bb.0: @ %entry45; CHECK-NEXT: movs r1, #546; CHECK-NEXT: cmp r0, #4547; CHECK-NEXT: cinv r0, r1, gt48; CHECK-NEXT: bx lr49entry:50 %cmp = icmp sgt i32 %a, 4551 %spec.select = select i1 %cmp, i32 -6, i32 552 ret i32 %spec.select53}54 55define i32 @csinv_const_65(i32 %a) {56; CHECK-LABEL: csinv_const_65:57; CHECK: @ %bb.0: @ %entry58; CHECK-NEXT: movs r1, #559; CHECK-NEXT: cmp r0, #4560; CHECK-NEXT: cinv r0, r1, le61; CHECK-NEXT: bx lr62entry:63 %cmp = icmp sgt i32 %a, 4564 %spec.select = select i1 %cmp, i32 5, i32 -665 ret i32 %spec.select66}67 68define i32 @csinv_const_sext(i32 %a) {69; CHECK-LABEL: csinv_const_sext:70; CHECK: @ %bb.0: @ %entry71; CHECK-NEXT: cmp r0, #4572; CHECK-NEXT: csetm r0, gt73; CHECK-NEXT: bx lr74entry:75 %cmp = icmp sgt i32 %a, 4576 %spec.select = sext i1 %cmp to i3277 ret i32 %spec.select78}79 80define i32 @csneg_const(i32 %a) {81; CHECK-LABEL: csneg_const:82; CHECK: @ %bb.0: @ %entry83; CHECK-NEXT: movs r1, #184; CHECK-NEXT: cmp r0, #4585; CHECK-NEXT: cneg r0, r1, le86; CHECK-NEXT: bx lr87entry:88 %cmp = icmp sgt i32 %a, 4589 %spec.select = select i1 %cmp, i32 1, i32 -190 ret i32 %spec.select91}92 93define i32 @csneg_const_r(i32 %a) {94; CHECK-LABEL: csneg_const_r:95; CHECK: @ %bb.0: @ %entry96; CHECK-NEXT: movs r1, #197; CHECK-NEXT: cmp r0, #4598; CHECK-NEXT: cneg r0, r1, gt99; CHECK-NEXT: bx lr100entry:101 %cmp = icmp sgt i32 %a, 45102 %spec.select = select i1 %cmp, i32 -1, i32 1103 ret i32 %spec.select104}105 106define i32 @csel_var(i32 %a, i32 %b, i32 %c) {107; CHECK-LABEL: csel_var:108; CHECK: @ %bb.0: @ %entry109; CHECK-NEXT: cmp r0, #45110; CHECK-NEXT: csel r0, r1, r2, gt111; CHECK-NEXT: bx lr112entry:113 %cmp = icmp sgt i32 %a, 45114 %spec.select = select i1 %cmp, i32 %b, i32 %c115 ret i32 %spec.select116}117 118define i32 @csinc_var(i32 %a, i32 %b, i32 %c) {119; CHECK-LABEL: csinc_var:120; CHECK: @ %bb.0: @ %entry121; CHECK-NEXT: cmp r0, #45122; CHECK-NEXT: csinc r0, r1, r2, gt123; CHECK-NEXT: bx lr124entry:125 %cmp = icmp sgt i32 %a, 45126 %cplus1 = add nsw i32 %c, 1127 %spec.select = select i1 %cmp, i32 %b, i32 %cplus1128 ret i32 %spec.select129}130 131define i32 @csinc_swap_var(i32 %a, i32 %b, i32 %c) {132; CHECK-LABEL: csinc_swap_var:133; CHECK: @ %bb.0: @ %entry134; CHECK-NEXT: cmp r0, #45135; CHECK-NEXT: csinc r0, r2, r1, le136; CHECK-NEXT: bx lr137entry:138 %cmp = icmp sgt i32 %a, 45139 %bplus1 = add nsw i32 %b, 1140 %spec.select = select i1 %cmp, i32 %bplus1, i32 %c141 ret i32 %spec.select142}143 144define i32 @csinv_var(i32 %a, i32 %b, i32 %c) {145; CHECK-LABEL: csinv_var:146; CHECK: @ %bb.0: @ %entry147; CHECK-NEXT: cmp r0, #45148; CHECK-NEXT: csinv r0, r1, r2, gt149; CHECK-NEXT: bx lr150entry:151 %cmp = icmp sgt i32 %a, 45152 %cinv = xor i32 %c, -1153 %spec.select = select i1 %cmp, i32 %b, i32 %cinv154 ret i32 %spec.select155}156 157define i32 @csinv_swap_var(i32 %a, i32 %b, i32 %c) {158; CHECK-LABEL: csinv_swap_var:159; CHECK: @ %bb.0: @ %entry160; CHECK-NEXT: cmp r0, #45161; CHECK-NEXT: csinv r0, r2, r1, le162; CHECK-NEXT: bx lr163entry:164 %cmp = icmp sgt i32 %a, 45165 %binv = xor i32 %b, -1166 %spec.select = select i1 %cmp, i32 %binv, i32 %c167 ret i32 %spec.select168}169 170define i32 @csneg_var(i32 %a, i32 %b, i32 %c) {171; CHECK-LABEL: csneg_var:172; CHECK: @ %bb.0: @ %entry173; CHECK-NEXT: cmp r0, #45174; CHECK-NEXT: csneg r0, r1, r2, gt175; CHECK-NEXT: bx lr176entry:177 %cmp = icmp sgt i32 %a, 45178 %cneg = sub i32 0, %c179 %spec.select = select i1 %cmp, i32 %b, i32 %cneg180 ret i32 %spec.select181}182 183define i32 @csneg_swap_var_sgt(i32 %a, i32 %b, i32 %c) {184; CHECK-LABEL: csneg_swap_var_sgt:185; CHECK: @ %bb.0: @ %entry186; CHECK-NEXT: cmp r0, #45187; CHECK-NEXT: csneg r0, r2, r1, le188; CHECK-NEXT: bx lr189entry:190 %cmp = icmp sgt i32 %a, 45191 %bneg = sub i32 0, %b192 %spec.select = select i1 %cmp, i32 %bneg, i32 %c193 ret i32 %spec.select194}195 196define i32 @csneg_swap_var_sge(i32 %a, i32 %b, i32 %c) {197; CHECK-LABEL: csneg_swap_var_sge:198; CHECK: @ %bb.0: @ %entry199; CHECK-NEXT: cmp r0, #44200; CHECK-NEXT: csneg r0, r2, r1, le201; CHECK-NEXT: bx lr202entry:203 %cmp = icmp sge i32 %a, 45204 %bneg = sub i32 0, %b205 %spec.select = select i1 %cmp, i32 %bneg, i32 %c206 ret i32 %spec.select207}208 209define i32 @csneg_swap_var_sle(i32 %a, i32 %b, i32 %c) {210; CHECK-LABEL: csneg_swap_var_sle:211; CHECK: @ %bb.0: @ %entry212; CHECK-NEXT: cmp r0, #46213; CHECK-NEXT: csneg r0, r2, r1, ge214; CHECK-NEXT: bx lr215entry:216 %cmp = icmp sle i32 %a, 45217 %bneg = sub i32 0, %b218 %spec.select = select i1 %cmp, i32 %bneg, i32 %c219 ret i32 %spec.select220}221 222define i32 @csneg_swap_var_slt(i32 %a, i32 %b, i32 %c) {223; CHECK-LABEL: csneg_swap_var_slt:224; CHECK: @ %bb.0: @ %entry225; CHECK-NEXT: cmp r0, #45226; CHECK-NEXT: csneg r0, r2, r1, ge227; CHECK-NEXT: bx lr228entry:229 %cmp = icmp slt i32 %a, 45230 %bneg = sub i32 0, %b231 %spec.select = select i1 %cmp, i32 %bneg, i32 %c232 ret i32 %spec.select233}234 235define i32 @csneg_swap_var_ugt(i32 %a, i32 %b, i32 %c) {236; CHECK-LABEL: csneg_swap_var_ugt:237; CHECK: @ %bb.0: @ %entry238; CHECK-NEXT: cmp r0, #45239; CHECK-NEXT: csneg r0, r2, r1, ls240; CHECK-NEXT: bx lr241entry:242 %cmp = icmp ugt i32 %a, 45243 %bneg = sub i32 0, %b244 %spec.select = select i1 %cmp, i32 %bneg, i32 %c245 ret i32 %spec.select246}247 248define i32 @csneg_swap_var_uge(i32 %a, i32 %b, i32 %c) {249; CHECK-LABEL: csneg_swap_var_uge:250; CHECK: @ %bb.0: @ %entry251; CHECK-NEXT: cmp r0, #44252; CHECK-NEXT: csneg r0, r2, r1, ls253; CHECK-NEXT: bx lr254entry:255 %cmp = icmp uge i32 %a, 45256 %bneg = sub i32 0, %b257 %spec.select = select i1 %cmp, i32 %bneg, i32 %c258 ret i32 %spec.select259}260 261define i32 @csneg_swap_var_ule(i32 %a, i32 %b, i32 %c) {262; CHECK-LABEL: csneg_swap_var_ule:263; CHECK: @ %bb.0: @ %entry264; CHECK-NEXT: cmp r0, #46265; CHECK-NEXT: csneg r0, r2, r1, hs266; CHECK-NEXT: bx lr267entry:268 %cmp = icmp ule i32 %a, 45269 %bneg = sub i32 0, %b270 %spec.select = select i1 %cmp, i32 %bneg, i32 %c271 ret i32 %spec.select272}273 274define i32 @csneg_swap_var_ult(i32 %a, i32 %b, i32 %c) {275; CHECK-LABEL: csneg_swap_var_ult:276; CHECK: @ %bb.0: @ %entry277; CHECK-NEXT: cmp r0, #45278; CHECK-NEXT: csneg r0, r2, r1, hs279; CHECK-NEXT: bx lr280entry:281 %cmp = icmp ult i32 %a, 45282 %bneg = sub i32 0, %b283 %spec.select = select i1 %cmp, i32 %bneg, i32 %c284 ret i32 %spec.select285}286 287define i32 @csneg_swap_var_ne(i32 %a, i32 %b, i32 %c) {288; CHECK-LABEL: csneg_swap_var_ne:289; CHECK: @ %bb.0: @ %entry290; CHECK-NEXT: cmp r0, #45291; CHECK-NEXT: csneg r0, r2, r1, ne292; CHECK-NEXT: bx lr293entry:294 %cmp = icmp eq i32 %a, 45295 %bneg = sub i32 0, %b296 %spec.select = select i1 %cmp, i32 %bneg, i32 %c297 ret i32 %spec.select298}299 300define i32 @csneg_swap_var_eq(i32 %a, i32 %b, i32 %c) {301; CHECK-LABEL: csneg_swap_var_eq:302; CHECK: @ %bb.0: @ %entry303; CHECK-NEXT: cmp r0, #45304; CHECK-NEXT: csneg r0, r2, r1, eq305; CHECK-NEXT: bx lr306entry:307 %cmp = icmp ne i32 %a, 45308 %bneg = sub i32 0, %b309 %spec.select = select i1 %cmp, i32 %bneg, i32 %c310 ret i32 %spec.select311}312 313define i32 @csinc_inplace(i32 %a, i32 %b) {314; CHECK-LABEL: csinc_inplace:315; CHECK: @ %bb.0: @ %entry316; CHECK-NEXT: cmp r1, #45317; CHECK-NEXT: cinc r0, r0, gt318; CHECK-NEXT: bx lr319entry:320 %cmp = icmp sgt i32 %b, 45321 %inc = zext i1 %cmp to i32322 %spec.select = add nsw i32 %inc, %a323 ret i32 %spec.select324}325 326define i32 @csinv_inplace(i32 %a, i32 %b) {327; CHECK-LABEL: csinv_inplace:328; CHECK: @ %bb.0: @ %entry329; CHECK-NEXT: cmp r1, #45330; CHECK-NEXT: cinv r0, r0, gt331; CHECK-NEXT: bx lr332entry:333 %cmp = icmp sgt i32 %b, 45334 %sub = sext i1 %cmp to i32335 %xor = xor i32 %sub, %a336 ret i32 %xor337}338 339define i32 @csinc_to_csinv(i32 %a) {340; CHECK-LABEL: csinc_to_csinv:341; CHECK: @ %bb.0: @ %entry342; CHECK-NEXT: cmp r0, #46343; CHECK-NEXT: csetm r0, lt344; CHECK-NEXT: bx lr345entry:346 %cmp = icmp sgt i32 %a, 45347 %spec.select = select i1 %cmp, i32 0, i32 1348 %s = sub i32 0, %spec.select349 ret i32 %s350}351 352define i32 @csinc_to_csinv_multi(i32 %a) {353; CHECK-LABEL: csinc_to_csinv_multi:354; CHECK: @ %bb.0: @ %entry355; CHECK-NEXT: cmp r0, #46356; CHECK-NEXT: cset r0, lt357; CHECK-NEXT: rsbs r1, r0, #0358; CHECK-NEXT: eors r0, r1359; CHECK-NEXT: bx lr360entry:361 %cmp = icmp sgt i32 %a, 45362 %spec.select = select i1 %cmp, i32 0, i32 1363 %s = sub i32 0, %spec.select364 %t = xor i32 %s, %spec.select365 ret i32 %t366}367 368define i32 @test_known_bits(i32 %a, i32 %b) {369; CHECK-LABEL: test_known_bits:370; CHECK: @ %bb.0: @ %entry371; CHECK-NEXT: movs r2, #1372; CHECK-NEXT: cmp r0, #0373; CHECK-NEXT: cneg r0, r2, mi374; CHECK-NEXT: add r0, r1375; CHECK-NEXT: bx lr376entry:377 %c = icmp slt i32 %a, 0378 %s = select i1 %c, i32 -1, i32 1379 %t = add i32 %s, %b380 ret i32 %t381}382