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1; RUN: llc < %s -mtriple=thumbv7-none-eabi -mcpu=cortex-m3 | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT -check-prefix=NONE2; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m4 | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT -check-prefix=SP3; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=VFP -check-prefix=FP-ARMv84; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7 -mattr=-fp64 | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT -check-prefix=SP5; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=NEON -check-prefix=VFP46; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a57 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=NEON -check-prefix=FP-ARMv87 8declare double @llvm.sqrt.f64(double %Val)9define double @sqrt_d(double %a) {10; CHECK-LABEL: sqrt_d:11; SOFT: {{(bl|b)}} sqrt12; HARD: vsqrt.f64 d0, d013 %1 = call double @llvm.sqrt.f64(double %a)14 ret double %115}16 17declare double @llvm.powi.f64.i32(double %Val, i32 %power)18define double @powi_d(double %a, i32 %b) {19; CHECK-LABEL: powi_d:20; SOFT: {{(bl|b)}} __powidf221; HARD: b __powidf222 %1 = call double @llvm.powi.f64.i32(double %a, i32 %b)23 ret double %124}25 26declare double @llvm.sin.f64(double %Val)27define double @sin_d(double %a) {28; CHECK-LABEL: sin_d:29; SOFT: {{(bl|b)}} sin30; HARD: b sin31 %1 = call double @llvm.sin.f64(double %a)32 ret double %133}34 35declare double @llvm.cos.f64(double %Val)36define double @cos_d(double %a) {37; CHECK-LABEL: cos_d:38; SOFT: {{(bl|b)}} cos39; HARD: b cos40 %1 = call double @llvm.cos.f64(double %a)41 ret double %142}43 44declare double @llvm.tan.f64(double %Val)45define double @tan_d(double %a) {46; CHECK-LABEL: tan_d:47; SOFT: {{(bl|b)}} tan48; HARD: b tan49 %1 = call double @llvm.tan.f64(double %a)50 ret double %151}52 53declare double @llvm.pow.f64(double %Val, double %power)54define double @pow_d(double %a, double %b) {55; CHECK-LABEL: pow_d:56; SOFT: {{(bl|b)}} pow57; HARD: b pow58 %1 = call double @llvm.pow.f64(double %a, double %b)59 ret double %160}61 62declare double @llvm.exp.f64(double %Val)63define double @exp_d(double %a) {64; CHECK-LABEL: exp_d:65; SOFT: {{(bl|b)}} exp66; HARD: b exp67 %1 = call double @llvm.exp.f64(double %a)68 ret double %169}70 71declare double @llvm.exp2.f64(double %Val)72define double @exp2_d(double %a) {73; CHECK-LABEL: exp2_d:74; SOFT: {{(bl|b)}} exp275; HARD: b exp276 %1 = call double @llvm.exp2.f64(double %a)77 ret double %178}79 80declare double @llvm.log.f64(double %Val)81define double @log_d(double %a) {82; CHECK-LABEL: log_d:83; SOFT: {{(bl|b)}} log84; HARD: b log85 %1 = call double @llvm.log.f64(double %a)86 ret double %187}88 89declare double @llvm.log10.f64(double %Val)90define double @log10_d(double %a) {91; CHECK-LABEL: log10_d:92; SOFT: {{(bl|b)}} log1093; HARD: b log1094 %1 = call double @llvm.log10.f64(double %a)95 ret double %196}97 98declare double @llvm.log2.f64(double %Val)99define double @log2_d(double %a) {100; CHECK-LABEL: log2_d:101; SOFT: {{(bl|b)}} log2102; HARD: b log2103 %1 = call double @llvm.log2.f64(double %a)104 ret double %1105}106 107declare double @llvm.fma.f64(double %a, double %b, double %c)108define double @fma_d(double %a, double %b, double %c) {109; CHECK-LABEL: fma_d:110; SOFT: {{(bl|b)}} fma111; HARD: vfma.f64112 %1 = call double @llvm.fma.f64(double %a, double %b, double %c)113 ret double %1114}115 116; FIXME: the FPv4-SP version is less efficient than the no-FPU version117declare double @llvm.fabs.f64(double %Val)118define double @abs_d(double %a) {119; CHECK-LABEL: abs_d:120; NONE: bic r1, r1, #-2147483648121; SP: vldr [[D1:d[0-9]+]], .LCPI{{.*}}122; SP-DAG: vmov [[R2:r[0-9]+]], [[R3:r[0-9]+]], [[D1]]123; SP-DAG: vmov [[R0:r[0-9]+]], [[R1:r[0-9]+]], [[D0:d[0-9]+]]124; SP: lsrs [[R4:r[0-9]+]], [[R3]], #31125; SP: bfi [[R5:r[0-9]+]], [[R4]], #31, #1126; SP: vmov [[D0]], [[R0]], [[R5]]127; DP: vabs.f64 d0, d0128 %1 = call double @llvm.fabs.f64(double %a)129 ret double %1130}131 132declare double @llvm.copysign.f64(double %Mag, double %Sgn)133define double @copysign_d(double %a, double %b) {134; CHECK-LABEL: copysign_d:135; SOFT: lsrs [[REG:r[0-9]+]], {{r[0-9]+}}, #31136; SOFT: bfi {{r[0-9]+}}, [[REG]], #31, #1137; VFP: lsrs [[REG:r[0-9]+]], {{r[0-9]+}}, #31138; VFP: bfi {{r[0-9]+}}, [[REG]], #31, #1139; NEON: vmov.i32 d16, #0x80000000140; NEON-NEXT: vshl.i64 d16, d16, #32141; NEON-NEXT: vbit d0, d1, d16142; NEON-NEXT: bx lr143 %1 = call double @llvm.copysign.f64(double %a, double %b)144 ret double %1145}146 147declare double @llvm.floor.f64(double %Val)148define double @floor_d(double %a) {149; CHECK-LABEL: floor_d:150; SOFT: {{(bl|b)}} floor151; VFP4: b floor152; FP-ARMv8: vrintm.f64153 %1 = call double @llvm.floor.f64(double %a)154 ret double %1155}156 157declare double @llvm.ceil.f64(double %Val)158define double @ceil_d(double %a) {159; CHECK-LABEL: ceil_d:160; SOFT: {{(bl|b)}} ceil161; VFP4: b ceil162; FP-ARMv8: vrintp.f64163 %1 = call double @llvm.ceil.f64(double %a)164 ret double %1165}166 167declare double @llvm.trunc.f64(double %Val)168define double @trunc_d(double %a) {169; CHECK-LABEL: trunc_d:170; SOFT: {{(bl|b)}} trunc171; FFP4: b trunc172; FP-ARMv8: vrintz.f64173 %1 = call double @llvm.trunc.f64(double %a)174 ret double %1175}176 177declare double @llvm.rint.f64(double %Val)178define double @rint_d(double %a) {179; CHECK-LABEL: rint_d:180; SOFT: {{(bl|b)}} rint181; VFP4: b rint182; FP-ARMv8: vrintx.f64183 %1 = call double @llvm.rint.f64(double %a)184 ret double %1185}186 187declare double @llvm.nearbyint.f64(double %Val)188define double @nearbyint_d(double %a) {189; CHECK-LABEL: nearbyint_d:190; SOFT: {{(bl|b)}} nearbyint191; VFP4: b nearbyint192; FP-ARMv8: vrintr.f64193 %1 = call double @llvm.nearbyint.f64(double %a)194 ret double %1195}196 197declare double @llvm.round.f64(double %Val)198define double @round_d(double %a) {199; CHECK-LABEL: round_d:200; SOFT: {{(bl|b)}} round201; VFP4: b round202; FP-ARMv8: vrinta.f64203 %1 = call double @llvm.round.f64(double %a)204 ret double %1205}206 207declare double @llvm.roundeven.f64(double %Val)208define double @roundeven_d(double %a) {209; CHECK-LABEL: roundeven_d:210; SOFT: {{(bl|b)}} roundeven211; VFP4: b roundeven212; FP-ARMv8: vrintn.f64213 %1 = call double @llvm.roundeven.f64(double %a)214 ret double %1215}216 217declare double @llvm.fmuladd.f64(double %a, double %b, double %c)218define double @fmuladd_d(double %a, double %b, double %c) {219; CHECK-LABEL: fmuladd_d:220; SOFT: bl __aeabi_dmul221; SOFT: bl __aeabi_dadd222; VFP4: vmul.f64223; VFP4: vadd.f64224; FP-ARMv8: vfma.f64225 %1 = call double @llvm.fmuladd.f64(double %a, double %b, double %c)226 ret double %1227}228 229declare i16 @llvm.convert.to.fp16.f64(double %a)230define i16 @d_to_h(double %a) {231; CHECK-LABEL: d_to_h:232; SOFT: bl __aeabi_d2h233; VFP4: bl __aeabi_d2h234; FP-ARMv8: vcvt{{[bt]}}.f16.f64235 %1 = call i16 @llvm.convert.to.fp16.f64(double %a)236 ret i16 %1237}238 239declare double @llvm.convert.from.fp16.f64(i16 %a)240define double @h_to_d(i16 %a) {241; CHECK-LABEL: h_to_d:242; NONE: bl __aeabi_h2f243; NONE: bl __aeabi_f2d244; SP: vcvt{{[bt]}}.f32.f16245; SP: bl __aeabi_f2d246; VFPv4: vcvt{{[bt]}}.f32.f16247; VFPv4: vcvt.f64.f32248; FP-ARMv8: vcvt{{[bt]}}.f64.f16249 %1 = call double @llvm.convert.from.fp16.f64(i16 %a)250 ret double %1251}252