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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -o - %s -run-pass=if-converter -simplify-mir | FileCheck %s3 4--- |5 ; ModuleID = 'ifcvt-dead-predicate.ll'6 source_filename = "ifcvt-dead-predicate.ll"7 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"8 target triple = "thumbv7-unknown-linux-android16"9 10 ; Function Attrs: minsize nounwind optsize ssp uwtable11 define hidden zeroext i1 @branch_entry(ptr %command_set, ptr %requested_filename, ptr %filename_to_use) local_unnamed_addr #0 {12 entry:13 %0 = load i32, ptr %command_set, align 414 %and.i.i = and i32 %0, 12815 %tobool.i.i.not = icmp eq i32 %and.i.i, 016 br i1 %tobool.i.i.not, label %land.end, label %land.rhs17 18 land.rhs: ; preds = %entry19 %call1 = tail call zeroext i1 @branch_target(ptr %requested_filename, ptr %filename_to_use)20 ret i1 %call121 22 land.end: ; preds = %entry23 ret i1 false24 }25 26 ; Function Attrs: minsize optsize27 declare zeroext i1 @branch_target(ptr, ptr) local_unnamed_addr #128 29 attributes #0 = { minsize nounwind optsize ssp uwtable }30 attributes #1 = { minsize optsize }31 32...33---34name: branch_entry35alignment: 236tracksRegLiveness: true37liveins:38 - { reg: '$r0' }39 - { reg: '$r1' }40 - { reg: '$r2' }41frameInfo:42 maxAlignment: 143 maxCallFrameSize: 044machineFunctionInfo: {}45body: |46 ; CHECK-LABEL: name: branch_entry47 ; CHECK: bb.0.entry:48 ; CHECK: successors: %bb.149 ; CHECK: liveins: $r0, $r1, $r250 ; CHECK: renamable $r0 = tLDRBi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load (s8) from %ir.command_set, align 4)51 ; CHECK: dead renamable $r0, $cpsr = tLSLri killed renamable $r0, 24, 14 /* CC::al */, $noreg52 ; CHECK: $r0, dead $noreg = tMOVi8 0, 5 /* CC::pl */, $cpsr53 ; CHECK: tBX_RET 5 /* CC::pl */, killed $cpsr, implicit killed $r054 ; CHECK: bb.1.land.rhs:55 ; CHECK: liveins: $r1, $r256 ; CHECK: $r0 = tMOVr killed $r1, 14 /* CC::al */, $noreg57 ; CHECK: $r1 = tMOVr killed $r2, 14 /* CC::al */, $noreg58 ; CHECK: tTAILJMPdND @branch_target, 14 /* CC::al */, $noreg, implicit $sp, implicit $sp, implicit $r0, implicit $r159 bb.0.entry:60 successors: %bb.1, %bb.261 liveins: $r0, $r1, $r262 63 renamable $r0 = tLDRBi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load (s8) from %ir.command_set, align 4)64 dead renamable $r0, $cpsr = tLSLri killed renamable $r0, 24, 14 /* CC::al */, $noreg65 t2Bcc %bb.2, 4 /* CC::mi */, killed $cpsr66 67 bb.1.land.end:68 $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg69 tBX_RET 14 /* CC::al */, $noreg, implicit $r070 71 bb.2.land.rhs:72 liveins: $r1, $r273 74 $r0 = tMOVr killed $r1, 14 /* CC::al */, $noreg75 $r1 = tMOVr killed $r2, 14 /* CC::al */, $noreg76 tTAILJMPdND @branch_target, 14 /* CC::al */, $noreg, implicit $sp, implicit $sp, implicit $r0, implicit $r177 78...79