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1; RUN: llc -mtriple=armv8.1-m-eabi -mattr=+mve %s -o - | FileCheck %s2 3define i32 @test1(i32 %tmp54) {4 %tmp56 = tail call i32 asm "uxtb16 $0,$1", "=r,r"( i32 %tmp54 )5 ret i32 %tmp566}7 8define void @test2() {9 tail call void asm sideeffect "/* number: ${0:c} */", "i"( i32 1 )10 ret void11}12 13define arm_aapcs_vfpcc <4 x i32> @mve-t-constraint-128bit(<4 x i32>, <4 x i32>) {14; CHECK-LABEL: mve-t-constraint-128bit15; CHECK: vadd.i32 q{{[0-7]}}, q{{[0-7]}}, q{{[0-7]}}16 %ret = tail call <4 x i32>17 asm "vadd.i32 $0, $1, $2", "=t,t,t"18 (<4 x i32> %0, <4 x i32> %1)19 ret <4 x i32> %ret20}21 22define i32 @even-GPR-constraint() {23entry:24 ; CHECK-LABEL: even-GPR-constraint25 ; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #126 ; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #227 ; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #328 ; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #429 %0 = tail call { i32, i32, i32, i32 }30 asm "add $0, #1\0Aadd $1, #2\0Aadd $2, #3\0Aadd $3, #4\0A", "=^Te,=^Te,=^Te,=^Te,0,1,2,3"31 (i32 0, i32 0, i32 0, i32 0)32 %asmresult = extractvalue { i32, i32, i32, i32 } %0, 033 ret i32 %asmresult34}35 36define i32 @odd-GPR-constraint() {37entry:38 ; CHECK-LABEL: odd-GPR-constraint39 ; CHECK: add [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #140 ; CHECK: add [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #241 ; CHECK: add [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #342 ; CHECK: add [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #443 %0 = tail call { i32, i32, i32, i32 }44 asm "add $0, #1\0Aadd $1, #2\0Aadd $2, #3\0Aadd $3, #4\0A", "=^To,=^To,=^To,=^To,0,1,2,3"45 (i32 0, i32 0, i32 0, i32 0)46 %asmresult = extractvalue { i32, i32, i32, i32 } %0, 047 ret i32 %asmresult48}49