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1; RUN: llc < %s -mtriple=thumbv7-eabi -mcpu=cortex-a8 -show-mc-encoding | FileCheck %s2define void @coproc(ptr %i) nounwind {3entry:4 ; CHECK: mrc p7, #1, r{{[0-9]+}}, c1, c1, #45 %0 = tail call i32 @llvm.arm.mrc(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind6 ; CHECK: mcr p7, #1, r{{[0-9]+}}, c1, c1, #47 tail call void @llvm.arm.mcr(i32 7, i32 1, i32 %0, i32 1, i32 1, i32 4) nounwind8 ; CHECK: mrc2 p7, #1, r{{[0-9]+}}, c1, c1, #49 %1 = tail call i32 @llvm.arm.mrc2(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind10 ; CHECK: mcr2 p7, #1, r{{[0-9]+}}, c1, c1, #411 tail call void @llvm.arm.mcr2(i32 7, i32 1, i32 %1, i32 1, i32 1, i32 4) nounwind12 ; CHECK: mcrr p7, #1, r{{[0-9]+}}, r{{[0-9]+}}, c113 tail call void @llvm.arm.mcrr(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind14 ; CHECK: mcrr2 p7, #1, r{{[0-9]+}}, r{{[0-9]+}}, c115 tail call void @llvm.arm.mcrr2(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind16 ; CHECK: cdp p7, #3, c1, c1, c1, #517 tail call void @llvm.arm.cdp(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind18 ; CHECK: cdp2 p7, #3, c1, c1, c1, #519 tail call void @llvm.arm.cdp2(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind20 ; CHECK: ldc p7, c3, [r{{[0-9]+}}]21 tail call void @llvm.arm.ldc(i32 7, i32 3, ptr %i) nounwind22 ; CHECK: ldcl p7, c3, [r{{[0-9]+}}]23 tail call void @llvm.arm.ldcl(i32 7, i32 3, ptr %i) nounwind24 ; CHECK: ldc2 p7, c3, [r{{[0-9]+}}]25 tail call void @llvm.arm.ldc2(i32 7, i32 3, ptr %i) nounwind26 ; CHECK: ldc2l p7, c3, [r{{[0-9]+}}]27 tail call void @llvm.arm.ldc2l(i32 7, i32 3, ptr %i) nounwind28 ; CHECK: stc p7, c3, [r{{[0-9]+}}]29 tail call void @llvm.arm.stc(i32 7, i32 3, ptr %i) nounwind30 ; CHECK: stcl p7, c3, [r{{[0-9]+}}]31 tail call void @llvm.arm.stcl(i32 7, i32 3, ptr %i) nounwind32 ; CHECK: stc2 p7, c3, [r{{[0-9]+}}]33 tail call void @llvm.arm.stc2(i32 7, i32 3, ptr %i) nounwind34 ; CHECK: stc2l p7, c3, [r{{[0-9]+}}]35 tail call void @llvm.arm.stc2l(i32 7, i32 3, ptr %i) nounwind36 ; CHECK: mrrc p1, #2, r{{[0-9]+}}, r{{[0-9]+}}, c337 %2 = tail call { i32, i32 } @llvm.arm.mrrc(i32 1, i32 2, i32 3) nounwind38 ; CHECK: mrrc2 p1, #2, r{{[0-9]+}}, r{{[0-9]+}}, c339 %3 = tail call { i32, i32 } @llvm.arm.mrrc2(i32 1, i32 2, i32 3) nounwind40 ret void41}42 43define hidden void @cond_cdp(i32 %a) {44; CHECK-LABEL: cond_cdp:45entry:46 %tobool = icmp eq i32 %a, 047 br i1 %tobool, label %if.end, label %if.then48 49if.then:50; CHECK: it ne51; CHECK: cdpne p15, #0, c0, c0, c0, #0 @ encoding: [0x00,0xee,0x00,0x0f]52 tail call void @llvm.arm.cdp(i32 15, i32 0, i32 0, i32 0, i32 0, i32 0)53 br label %if.end54 55if.end:56 ret void57}58 59declare void @llvm.arm.ldc(i32, i32, ptr) nounwind60 61declare void @llvm.arm.ldcl(i32, i32, ptr) nounwind62 63declare void @llvm.arm.ldc2(i32, i32, ptr) nounwind64 65declare void @llvm.arm.ldc2l(i32, i32, ptr) nounwind66 67declare void @llvm.arm.stc(i32, i32, ptr) nounwind68 69declare void @llvm.arm.stcl(i32, i32, ptr) nounwind70 71declare void @llvm.arm.stc2(i32, i32, ptr) nounwind72 73declare void @llvm.arm.stc2l(i32, i32, ptr) nounwind74 75declare void @llvm.arm.cdp2(i32, i32, i32, i32, i32, i32) nounwind76 77declare void @llvm.arm.cdp(i32, i32, i32, i32, i32, i32) nounwind78 79declare void @llvm.arm.mcrr2(i32, i32, i32, i32, i32) nounwind80 81declare void @llvm.arm.mcrr(i32, i32, i32, i32, i32) nounwind82 83declare void @llvm.arm.mcr2(i32, i32, i32, i32, i32, i32) nounwind84 85declare i32 @llvm.arm.mrc2(i32, i32, i32, i32, i32) nounwind86 87declare void @llvm.arm.mcr(i32, i32, i32, i32, i32, i32) nounwind88 89declare i32 @llvm.arm.mrc(i32, i32, i32, i32, i32) nounwind90 91declare { i32, i32 } @llvm.arm.mrrc(i32, i32, i32) nounwind92 93declare { i32, i32 } @llvm.arm.mrrc2(i32, i32, i32) nounwind94