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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -enable-arm-maskedgatscat=false -verify-machineinstrs %s -o - | FileCheck %s3 4define void @_Z4loopPxS_iS_i(ptr %d) {5; CHECK-LABEL: _Z4loopPxS_iS_i:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vldrw.u32 q0, [r0]8; CHECK-NEXT: vmov r1, s29; CHECK-NEXT: vmov r2, s010; CHECK-NEXT: rsbs r1, r1, #011; CHECK-NEXT: rsbs r2, r2, #012; CHECK-NEXT: sxth r1, r113; CHECK-NEXT: sxth r2, r214; CHECK-NEXT: asr.w r12, r1, #3115; CHECK-NEXT: asrs r3, r2, #3116; CHECK-NEXT: strd r2, r3, [r0]17; CHECK-NEXT: strd r1, r12, [r0, #8]18; CHECK-NEXT: bx lr19entry:20 %wide.load = load <2 x i64>, ptr undef, align 821 %0 = trunc <2 x i64> %wide.load to <2 x i32>22 %1 = shl <2 x i32> %0, <i32 16, i32 16>23 %2 = ashr exact <2 x i32> %1, <i32 16, i32 16>24 %3 = sub <2 x i32> %2, %025 %4 = and <2 x i32> %3, <i32 7, i32 7>26 %5 = shl <2 x i32> %2, %427 %6 = extractelement <2 x i32> %5, i32 028 %7 = zext i32 %6 to i6429 %8 = select i1 false, i64 %7, i64 undef30 %9 = trunc i64 %8 to i1631 %10 = sub i16 0, %932 %11 = sext i16 %10 to i6433 %12 = getelementptr inbounds i64, ptr %d, i64 undef34 store i64 %11, ptr %12, align 835 %13 = extractelement <2 x i32> %5, i32 136 %14 = zext i32 %13 to i6437 %15 = select i1 false, i64 %14, i64 undef38 %16 = trunc i64 %15 to i1639 %17 = sub i16 0, %1640 %18 = sext i16 %17 to i6441 %19 = or i32 0, 142 %20 = sext i32 %19 to i6443 %21 = getelementptr inbounds i64, ptr %d, i64 %2044 store i64 %18, ptr %21, align 845 ret void46}47