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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc %s -o - | FileCheck %s3 4target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"5target triple = "thumbv7em-arm-none-eabi"6 7%struct.a = type { i32, ptr, i8, i8, i8, i8, ptr, ptr, i16, i16, i16, i16, i16, i16, i16, i16, i32, i32, i32, i32, i32, i32, i32 }8%struct.b = type { i8, i8, i8, i8, i32, i16, i16, i32, i32, i32, i32, [16 x i8], [64 x i8], [128 x i8], i32, [68 x i8] }9 10define void @test(ptr nocapture %dhcp, i16 zeroext %value) #0 {11; CHECK-LABEL: test:12; CHECK: @ %bb.0: @ %entry13; CHECK-NEXT: ldrh r2, [r0, #20]14; CHECK-NEXT: adds r3, r2, #115; CHECK-NEXT: strh r3, [r0, #20]16; CHECK-NEXT: ldr r3, [r0, #16]17; CHECK-NEXT: add r2, r318; CHECK-NEXT: lsrs r3, r1, #819; CHECK-NEXT: strb.w r3, [r2, #240]20; CHECK-NEXT: ldrh r2, [r0, #20]21; CHECK-NEXT: adds r3, r2, #122; CHECK-NEXT: strh r3, [r0, #20]23; CHECK-NEXT: ldr r0, [r0, #16]24; CHECK-NEXT: add r0, r225; CHECK-NEXT: strb.w r1, [r0, #240]26; CHECK-NEXT: bx lr27entry:28 %shr = lshr i16 %value, 829 %conv1 = trunc i16 %shr to i830 %msg_out = getelementptr inbounds %struct.a, ptr %dhcp, i32 0, i32 731 %0 = load ptr, ptr %msg_out, align 432 %options_out_len = getelementptr inbounds %struct.a, ptr %dhcp, i32 0, i32 833 %1 = load i16, ptr %options_out_len, align 434 %inc = add i16 %1, 135 store i16 %inc, ptr %options_out_len, align 436 %idxprom = zext i16 %1 to i3237 %arrayidx = getelementptr inbounds %struct.b, ptr %0, i32 0, i32 15, i32 %idxprom38 store i8 %conv1, ptr %arrayidx, align 139 %conv4 = trunc i16 %value to i840 %2 = load ptr, ptr %msg_out, align 441 %3 = load i16, ptr %options_out_len, align 442 %inc8 = add i16 %3, 143 store i16 %inc8, ptr %options_out_len, align 444 %idxprom9 = zext i16 %3 to i3245 %arrayidx10 = getelementptr inbounds %struct.b, ptr %2, i32 0, i32 15, i32 %idxprom946 store i8 %conv4, ptr %arrayidx10, align 147 ret void48}49 50attributes #0 = { minsize optsize "target-cpu"="cortex-m4" }51