61 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -o - %s | FileCheck %s3; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -o - %s | FileCheck %s4 5define arm_aapcs_vfpcc <4 x i32> @vector_add_by_value(<4 x i32> %lhs, <4 x i32>%rhs) {6; CHECK-LABEL: vector_add_by_value:7; CHECK: @ %bb.0:8; CHECK-NEXT: @APP9; CHECK-NEXT: vadd.i32 q0, q0, q110; CHECK-NEXT: @NO_APP11; CHECK-NEXT: bx lr12 %result = tail call <4 x i32> asm "vadd.i32 $0,$1,$2", "=t,t,t"(<4 x i32> %lhs, <4 x i32> %rhs)13 ret <4 x i32> %result14}15 16define void @vector_add_by_reference(ptr %resultp, ptr %lhsp, ptr %rhsp) {17; CHECK-LABEL: vector_add_by_reference:18; CHECK: @ %bb.0:19; CHECK-NEXT: vldrw.u32 q0, [r1]20; CHECK-NEXT: vldrw.u32 q1, [r2]21; CHECK-NEXT: @APP22; CHECK-NEXT: vadd.i32 q0, q0, q123; CHECK-NEXT: @NO_APP24; CHECK-NEXT: vstrw.32 q0, [r0]25; CHECK-NEXT: bx lr26 %lhs = load <4 x i32>, ptr %lhsp, align 1627 %rhs = load <4 x i32>, ptr %rhsp, align 1628 %result = tail call <4 x i32> asm "vadd.i32 $0,$1,$2", "=t,t,t"(<4 x i32> %lhs, <4 x i32> %rhs)29 store <4 x i32> %result, ptr %resultp, align 1630 ret void31}32 33define void @vector_f64_copy(ptr %from, ptr %to) {34; CHECK-LABEL: vector_f64_copy:35; CHECK: @ %bb.0:36; CHECK-NEXT: vldrw.u32 q0, [r0]37; CHECK-NEXT: vstrw.32 q0, [r1]38; CHECK-NEXT: bx lr39 %v = load <2 x double>, ptr %from, align 1640 store <2 x double> %v, ptr %to, align 1641 ret void42}43 44define arm_aapcs_vfpcc <16 x i8> @stack_slot_handling(<16 x i8> %a) #0 {45; CHECK-LABEL: stack_slot_handling:46; CHECK: @ %bb.0: @ %entry47; CHECK-NEXT: sub sp, #1648; CHECK-NEXT: mov r0, sp49; CHECK-NEXT: vstrw.32 q0, [r0]50; CHECK-NEXT: vldrw.u32 q0, [r0]51; CHECK-NEXT: add sp, #1652; CHECK-NEXT: bx lr53entry:54 %a.addr = alloca <16 x i8>, align 855 store <16 x i8> %a, ptr %a.addr, align 856 %0 = load <16 x i8>, ptr %a.addr, align 857 ret <16 x i8> %058}59 60attributes #0 = { noinline optnone }61