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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s3 4define arm_aapcs_vfpcc <16 x i8> @and_int8_t(<16 x i8> %src1, <16 x i8> %src2) {5; CHECK-LABEL: and_int8_t:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vand q0, q0, q18; CHECK-NEXT: bx lr9entry:10 %0 = and <16 x i8> %src1, %src211 ret <16 x i8> %012}13 14define arm_aapcs_vfpcc <8 x i16> @and_int16_t(<8 x i16> %src1, <8 x i16> %src2) {15; CHECK-LABEL: and_int16_t:16; CHECK: @ %bb.0: @ %entry17; CHECK-NEXT: vand q0, q0, q118; CHECK-NEXT: bx lr19entry:20 %0 = and <8 x i16> %src1, %src221 ret <8 x i16> %022}23 24define arm_aapcs_vfpcc <4 x i32> @and_int32_t(<4 x i32> %src1, <4 x i32> %src2) {25; CHECK-LABEL: and_int32_t:26; CHECK: @ %bb.0: @ %entry27; CHECK-NEXT: vand q0, q0, q128; CHECK-NEXT: bx lr29entry:30 %0 = and <4 x i32> %src1, %src231 ret <4 x i32> %032}33 34define arm_aapcs_vfpcc <2 x i64> @and_int64_t(<2 x i64> %src1, <2 x i64> %src2) {35; CHECK-LABEL: and_int64_t:36; CHECK: @ %bb.0: @ %entry37; CHECK-NEXT: vand q0, q0, q138; CHECK-NEXT: bx lr39entry:40 %0 = and <2 x i64> %src1, %src241 ret <2 x i64> %042}43 44 45define arm_aapcs_vfpcc <16 x i8> @or_int8_t(<16 x i8> %src1, <16 x i8> %src2) {46; CHECK-LABEL: or_int8_t:47; CHECK: @ %bb.0: @ %entry48; CHECK-NEXT: vorr q0, q0, q149; CHECK-NEXT: bx lr50entry:51 %0 = or <16 x i8> %src1, %src252 ret <16 x i8> %053}54 55define arm_aapcs_vfpcc <8 x i16> @or_int16_t(<8 x i16> %src1, <8 x i16> %src2) {56; CHECK-LABEL: or_int16_t:57; CHECK: @ %bb.0: @ %entry58; CHECK-NEXT: vorr q0, q0, q159; CHECK-NEXT: bx lr60entry:61 %0 = or <8 x i16> %src1, %src262 ret <8 x i16> %063}64 65define arm_aapcs_vfpcc <4 x i32> @or_int32_t(<4 x i32> %src1, <4 x i32> %src2) {66; CHECK-LABEL: or_int32_t:67; CHECK: @ %bb.0: @ %entry68; CHECK-NEXT: vorr q0, q0, q169; CHECK-NEXT: bx lr70entry:71 %0 = or <4 x i32> %src1, %src272 ret <4 x i32> %073}74 75define arm_aapcs_vfpcc <2 x i64> @or_int64_t(<2 x i64> %src1, <2 x i64> %src2) {76; CHECK-LABEL: or_int64_t:77; CHECK: @ %bb.0: @ %entry78; CHECK-NEXT: vorr q0, q0, q179; CHECK-NEXT: bx lr80entry:81 %0 = or <2 x i64> %src1, %src282 ret <2 x i64> %083}84 85 86define arm_aapcs_vfpcc <16 x i8> @xor_int8_t(<16 x i8> %src1, <16 x i8> %src2) {87; CHECK-LABEL: xor_int8_t:88; CHECK: @ %bb.0: @ %entry89; CHECK-NEXT: veor q0, q0, q190; CHECK-NEXT: bx lr91entry:92 %0 = xor <16 x i8> %src1, %src293 ret <16 x i8> %094}95 96define arm_aapcs_vfpcc <8 x i16> @xor_int16_t(<8 x i16> %src1, <8 x i16> %src2) {97; CHECK-LABEL: xor_int16_t:98; CHECK: @ %bb.0: @ %entry99; CHECK-NEXT: veor q0, q0, q1100; CHECK-NEXT: bx lr101entry:102 %0 = xor <8 x i16> %src1, %src2103 ret <8 x i16> %0104}105 106define arm_aapcs_vfpcc <4 x i32> @xor_int32_t(<4 x i32> %src1, <4 x i32> %src2) {107; CHECK-LABEL: xor_int32_t:108; CHECK: @ %bb.0: @ %entry109; CHECK-NEXT: veor q0, q0, q1110; CHECK-NEXT: bx lr111entry:112 %0 = xor <4 x i32> %src1, %src2113 ret <4 x i32> %0114}115 116define arm_aapcs_vfpcc <2 x i64> @xor_int64_t(<2 x i64> %src1, <2 x i64> %src2) {117; CHECK-LABEL: xor_int64_t:118; CHECK: @ %bb.0: @ %entry119; CHECK-NEXT: veor q0, q0, q1120; CHECK-NEXT: bx lr121entry:122 %0 = xor <2 x i64> %src1, %src2123 ret <2 x i64> %0124}125 126define arm_aapcs_vfpcc <16 x i8> @v_mvn_i8(<16 x i8> %src) {127; CHECK-LABEL: v_mvn_i8:128; CHECK: @ %bb.0: @ %entry129; CHECK-NEXT: vmvn q0, q0130; CHECK-NEXT: bx lr131entry:132 %0 = xor <16 x i8> %src, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>133 ret <16 x i8> %0134}135 136define arm_aapcs_vfpcc <8 x i16> @v_mvn_i16(<8 x i16> %src) {137; CHECK-LABEL: v_mvn_i16:138; CHECK: @ %bb.0: @ %entry139; CHECK-NEXT: vmvn q0, q0140; CHECK-NEXT: bx lr141entry:142 %0 = xor <8 x i16> %src, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>143 ret <8 x i16> %0144}145 146define arm_aapcs_vfpcc <4 x i32> @v_mvn_i32(<4 x i32> %src) {147; CHECK-LABEL: v_mvn_i32:148; CHECK: @ %bb.0: @ %entry149; CHECK-NEXT: vmvn q0, q0150; CHECK-NEXT: bx lr151entry:152 %0 = xor <4 x i32> %src, <i32 -1, i32 -1, i32 -1, i32 -1>153 ret <4 x i32> %0154}155 156define arm_aapcs_vfpcc <2 x i64> @v_mvn_i64(<2 x i64> %src) {157; CHECK-LABEL: v_mvn_i64:158; CHECK: @ %bb.0: @ %entry159; CHECK-NEXT: vmvn q0, q0160; CHECK-NEXT: bx lr161entry:162 %0 = xor <2 x i64> %src, <i64 -1, i64 -1>163 ret <2 x i64> %0164}165 166 167define arm_aapcs_vfpcc <16 x i8> @v_bic_i8(<16 x i8> %src1, <16 x i8> %src2) {168; CHECK-LABEL: v_bic_i8:169; CHECK: @ %bb.0: @ %entry170; CHECK-NEXT: vbic q0, q1, q0171; CHECK-NEXT: bx lr172entry:173 %0 = xor <16 x i8> %src1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>174 %1 = and <16 x i8> %src2, %0175 ret <16 x i8> %1176}177 178define arm_aapcs_vfpcc <8 x i16> @v_bic_i16(<8 x i16> %src1, <8 x i16> %src2) {179; CHECK-LABEL: v_bic_i16:180; CHECK: @ %bb.0: @ %entry181; CHECK-NEXT: vbic q0, q1, q0182; CHECK-NEXT: bx lr183entry:184 %0 = xor <8 x i16> %src1, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>185 %1 = and <8 x i16> %src2, %0186 ret <8 x i16> %1187}188 189define arm_aapcs_vfpcc <4 x i32> @v_bic_i32(<4 x i32> %src1, <4 x i32> %src2) {190; CHECK-LABEL: v_bic_i32:191; CHECK: @ %bb.0: @ %entry192; CHECK-NEXT: vbic q0, q1, q0193; CHECK-NEXT: bx lr194entry:195 %0 = xor <4 x i32> %src1, <i32 -1, i32 -1, i32 -1, i32 -1>196 %1 = and <4 x i32> %src2, %0197 ret <4 x i32> %1198}199 200define arm_aapcs_vfpcc <2 x i64> @v_bic_i64(<2 x i64> %src1, <2 x i64> %src2) {201; CHECK-LABEL: v_bic_i64:202; CHECK: @ %bb.0: @ %entry203; CHECK-NEXT: vbic q0, q1, q0204; CHECK-NEXT: bx lr205entry:206 %0 = xor <2 x i64> %src1, <i64 -1, i64 -1>207 %1 = and <2 x i64> %src2, %0208 ret <2 x i64> %1209}210 211 212define arm_aapcs_vfpcc <16 x i8> @v_or_i8(<16 x i8> %src1, <16 x i8> %src2) {213; CHECK-LABEL: v_or_i8:214; CHECK: @ %bb.0: @ %entry215; CHECK-NEXT: vorn q0, q1, q0216; CHECK-NEXT: bx lr217entry:218 %0 = xor <16 x i8> %src1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>219 %1 = or <16 x i8> %src2, %0220 ret <16 x i8> %1221}222 223define arm_aapcs_vfpcc <8 x i16> @v_or_i16(<8 x i16> %src1, <8 x i16> %src2) {224; CHECK-LABEL: v_or_i16:225; CHECK: @ %bb.0: @ %entry226; CHECK-NEXT: vorn q0, q1, q0227; CHECK-NEXT: bx lr228entry:229 %0 = xor <8 x i16> %src1, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>230 %1 = or <8 x i16> %src2, %0231 ret <8 x i16> %1232}233 234define arm_aapcs_vfpcc <4 x i32> @v_or_i32(<4 x i32> %src1, <4 x i32> %src2) {235; CHECK-LABEL: v_or_i32:236; CHECK: @ %bb.0: @ %entry237; CHECK-NEXT: vorn q0, q1, q0238; CHECK-NEXT: bx lr239entry:240 %0 = xor <4 x i32> %src1, <i32 -1, i32 -1, i32 -1, i32 -1>241 %1 = or <4 x i32> %src2, %0242 ret <4 x i32> %1243}244 245define arm_aapcs_vfpcc <2 x i64> @v_or_i64(<2 x i64> %src1, <2 x i64> %src2) {246; CHECK-LABEL: v_or_i64:247; CHECK: @ %bb.0: @ %entry248; CHECK-NEXT: vorn q0, q1, q0249; CHECK-NEXT: bx lr250entry:251 %0 = xor <2 x i64> %src1, <i64 -1, i64 -1>252 %1 = or <2 x i64> %src2, %0253 ret <2 x i64> %1254}255 256