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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s --mattr=+mve.fp,+fp64 -o - | FileCheck %s3 4target triple = "thumbv8.1m.main-none-none-eabi"5 6 7; Expected to not transform8define arm_aapcs_vfpcc <2 x double> @complex_add_v2f64(<2 x double> %a, <2 x double> %b) {9; CHECK-LABEL: complex_add_v2f64:10; CHECK: @ %bb.0: @ %entry11; CHECK-NEXT: vadd.f64 d3, d3, d012; CHECK-NEXT: vsub.f64 d2, d2, d113; CHECK-NEXT: vmov q0, q114; CHECK-NEXT: bx lr15entry:16 %a.real = shufflevector <2 x double> %a, <2 x double> zeroinitializer, <1 x i32> <i32 0>17 %a.imag = shufflevector <2 x double> %a, <2 x double> zeroinitializer, <1 x i32> <i32 1>18 %b.real = shufflevector <2 x double> %b, <2 x double> zeroinitializer, <1 x i32> <i32 0>19 %b.imag = shufflevector <2 x double> %b, <2 x double> zeroinitializer, <1 x i32> <i32 1>20 %0 = fsub fast <1 x double> %b.real, %a.imag21 %1 = fadd fast <1 x double> %b.imag, %a.real22 %interleaved.vec = shufflevector <1 x double> %0, <1 x double> %1, <2 x i32> <i32 0, i32 1>23 ret <2 x double> %interleaved.vec24}25 26; Expected to not transform27define arm_aapcs_vfpcc <4 x double> @complex_add_v4f64(<4 x double> %a, <4 x double> %b) {28; CHECK-LABEL: complex_add_v4f64:29; CHECK: @ %bb.0: @ %entry30; CHECK-NEXT: vadd.f64 d5, d5, d031; CHECK-NEXT: vsub.f64 d4, d4, d132; CHECK-NEXT: vadd.f64 d7, d7, d233; CHECK-NEXT: vmov q0, q234; CHECK-NEXT: vsub.f64 d6, d6, d335; CHECK-NEXT: vmov q1, q336; CHECK-NEXT: bx lr37entry:38 %a.real = shufflevector <4 x double> %a, <4 x double> zeroinitializer, <2 x i32> <i32 0, i32 2>39 %a.imag = shufflevector <4 x double> %a, <4 x double> zeroinitializer, <2 x i32> <i32 1, i32 3>40 %b.real = shufflevector <4 x double> %b, <4 x double> zeroinitializer, <2 x i32> <i32 0, i32 2>41 %b.imag = shufflevector <4 x double> %b, <4 x double> zeroinitializer, <2 x i32> <i32 1, i32 3>42 %0 = fsub fast <2 x double> %b.real, %a.imag43 %1 = fadd fast <2 x double> %b.imag, %a.real44 %interleaved.vec = shufflevector <2 x double> %0, <2 x double> %1, <4 x i32> <i32 0, i32 2, i32 1, i32 3>45 ret <4 x double> %interleaved.vec46}47 48; Expected to not transform49define arm_aapcs_vfpcc <8 x double> @complex_add_v8f64(<8 x double> %a, <8 x double> %b) {50; CHECK-LABEL: complex_add_v8f64:51; CHECK: @ %bb.0: @ %entry52; CHECK-NEXT: .vsave {d8, d9, d10, d11}53; CHECK-NEXT: vpush {d8, d9, d10, d11}54; CHECK-NEXT: add r0, sp, #3255; CHECK-NEXT: vmov q4, q156; CHECK-NEXT: vmov q1, q057; CHECK-NEXT: vldrw.u32 q0, [r0]58; CHECK-NEXT: add r0, sp, #4859; CHECK-NEXT: vadd.f64 d1, d1, d260; CHECK-NEXT: vsub.f64 d0, d0, d361; CHECK-NEXT: vldrw.u32 q1, [r0]62; CHECK-NEXT: add r0, sp, #6463; CHECK-NEXT: vadd.f64 d3, d3, d864; CHECK-NEXT: vsub.f64 d2, d2, d965; CHECK-NEXT: vldrw.u32 q4, [r0]66; CHECK-NEXT: add r0, sp, #8067; CHECK-NEXT: vadd.f64 d9, d9, d468; CHECK-NEXT: vsub.f64 d8, d8, d569; CHECK-NEXT: vldrw.u32 q2, [r0]70; CHECK-NEXT: vadd.f64 d11, d5, d671; CHECK-NEXT: vsub.f64 d10, d4, d772; CHECK-NEXT: vmov q2, q473; CHECK-NEXT: vmov q3, q574; CHECK-NEXT: vpop {d8, d9, d10, d11}75; CHECK-NEXT: bx lr76entry:77 %a.real = shufflevector <8 x double> %a, <8 x double> zeroinitializer, <4 x i32> <i32 0, i32 2, i32 4, i32 6>78 %a.imag = shufflevector <8 x double> %a, <8 x double> zeroinitializer, <4 x i32> <i32 1, i32 3, i32 5, i32 7>79 %b.real = shufflevector <8 x double> %b, <8 x double> zeroinitializer, <4 x i32> <i32 0, i32 2, i32 4, i32 6>80 %b.imag = shufflevector <8 x double> %b, <8 x double> zeroinitializer, <4 x i32> <i32 1, i32 3, i32 5, i32 7>81 %0 = fsub fast <4 x double> %b.real, %a.imag82 %1 = fadd fast <4 x double> %b.imag, %a.real83 %interleaved.vec = shufflevector <4 x double> %0, <4 x double> %1, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>84 ret <8 x double> %interleaved.vec85}86