165 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s --mattr=+mve -o - --verify-machineinstrs | FileCheck %s3 4target triple = "thumbv8.1m.main-none-none-eabi"5 6 7; Expected to not transform8define arm_aapcs_vfpcc <2 x i64> @complex_add_v2i64(<2 x i64> %a, <2 x i64> %b) {9; CHECK-LABEL: complex_add_v2i64:10; CHECK: @ %bb.0: @ %entry11; CHECK-NEXT: .save {r7, lr}12; CHECK-NEXT: push {r7, lr}13; CHECK-NEXT: vmov r0, r1, d014; CHECK-NEXT: vmov r2, r3, d315; CHECK-NEXT: adds.w lr, r2, r016; CHECK-NEXT: adc.w r12, r3, r117; CHECK-NEXT: vmov r2, r3, d118; CHECK-NEXT: vmov r1, r0, d219; CHECK-NEXT: subs r1, r1, r220; CHECK-NEXT: vmov q0[2], q0[0], r1, lr21; CHECK-NEXT: sbcs r0, r322; CHECK-NEXT: vmov q0[3], q0[1], r0, r1223; CHECK-NEXT: pop {r7, pc}24entry:25 %a.real = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <1 x i32> <i32 0>26 %a.imag = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <1 x i32> <i32 1>27 %b.real = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <1 x i32> <i32 0>28 %b.imag = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <1 x i32> <i32 1>29 %0 = sub <1 x i64> %b.real, %a.imag30 %1 = add <1 x i64> %b.imag, %a.real31 %interleaved.vec = shufflevector <1 x i64> %0, <1 x i64> %1, <2 x i32> <i32 0, i32 1>32 ret <2 x i64> %interleaved.vec33}34 35; Expected to not transform36define arm_aapcs_vfpcc <4 x i64> @complex_add_v4i64(<4 x i64> %a, <4 x i64> %b) {37; CHECK-LABEL: complex_add_v4i64:38; CHECK: @ %bb.0: @ %entry39; CHECK-NEXT: .save {r7, lr}40; CHECK-NEXT: push {r7, lr}41; CHECK-NEXT: .vsave {d8, d9}42; CHECK-NEXT: vpush {d8, d9}43; CHECK-NEXT: vmov q4, q144; CHECK-NEXT: vmov r2, r3, d745; CHECK-NEXT: vmov r0, r1, d846; CHECK-NEXT: adds.w lr, r2, r047; CHECK-NEXT: adc.w r12, r3, r148; CHECK-NEXT: vmov r2, r3, d049; CHECK-NEXT: vmov r1, r0, d550; CHECK-NEXT: adds r1, r1, r251; CHECK-NEXT: adcs r0, r352; CHECK-NEXT: vmov q1[2], q1[0], r1, lr53; CHECK-NEXT: vmov q1[3], q1[1], r0, r1254; CHECK-NEXT: vmov r0, r1, d955; CHECK-NEXT: vmov r2, r3, d656; CHECK-NEXT: subs.w lr, r2, r057; CHECK-NEXT: sbc.w r12, r3, r158; CHECK-NEXT: vmov r2, r3, d159; CHECK-NEXT: vmov r1, r0, d460; CHECK-NEXT: vmov.f32 s2, s461; CHECK-NEXT: vmov.f32 s3, s562; CHECK-NEXT: subs r1, r1, r263; CHECK-NEXT: vmov q2[2], q2[0], r1, lr64; CHECK-NEXT: sbcs r0, r365; CHECK-NEXT: vmov q2[3], q2[1], r0, r1266; CHECK-NEXT: vmov.f32 s0, s867; CHECK-NEXT: vmov.f32 s4, s1068; CHECK-NEXT: vmov.f32 s1, s969; CHECK-NEXT: vmov.f32 s5, s1170; CHECK-NEXT: vpop {d8, d9}71; CHECK-NEXT: pop {r7, pc}72entry:73 %a.real = shufflevector <4 x i64> %a, <4 x i64> zeroinitializer, <2 x i32> <i32 0, i32 2>74 %a.imag = shufflevector <4 x i64> %a, <4 x i64> zeroinitializer, <2 x i32> <i32 1, i32 3>75 %b.real = shufflevector <4 x i64> %b, <4 x i64> zeroinitializer, <2 x i32> <i32 0, i32 2>76 %b.imag = shufflevector <4 x i64> %b, <4 x i64> zeroinitializer, <2 x i32> <i32 1, i32 3>77 %0 = sub <2 x i64> %b.real, %a.imag78 %1 = add <2 x i64> %b.imag, %a.real79 %interleaved.vec = shufflevector <2 x i64> %0, <2 x i64> %1, <4 x i32> <i32 0, i32 2, i32 1, i32 3>80 ret <4 x i64> %interleaved.vec81}82 83; Expected to not transform84define arm_aapcs_vfpcc <8 x i64> @complex_add_v8i64(<8 x i64> %a, <8 x i64> %b) {85; CHECK-LABEL: complex_add_v8i64:86; CHECK: @ %bb.0: @ %entry87; CHECK-NEXT: .save {r7, lr}88; CHECK-NEXT: push {r7, lr}89; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}90; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}91; CHECK-NEXT: add r2, sp, #7292; CHECK-NEXT: vmov q4, q193; CHECK-NEXT: vldrw.u32 q5, [r2]94; CHECK-NEXT: vmov r0, r1, d895; CHECK-NEXT: vmov r2, r3, d1196; CHECK-NEXT: adds.w lr, r2, r097; CHECK-NEXT: adc.w r12, r3, r198; CHECK-NEXT: add r1, sp, #5699; CHECK-NEXT: vldrw.u32 q6, [r1]100; CHECK-NEXT: vmov r2, r3, d0101; CHECK-NEXT: vmov r1, r0, d13102; CHECK-NEXT: adds r1, r1, r2103; CHECK-NEXT: adcs r0, r3104; CHECK-NEXT: vmov q1[2], q1[0], r1, lr105; CHECK-NEXT: vmov q1[3], q1[1], r0, r12106; CHECK-NEXT: vmov r0, r1, d9107; CHECK-NEXT: vmov r2, r3, d10108; CHECK-NEXT: subs.w lr, r2, r0109; CHECK-NEXT: sbc.w r12, r3, r1110; CHECK-NEXT: vmov r2, r3, d1111; CHECK-NEXT: vmov r1, r0, d12112; CHECK-NEXT: vmov.f32 s2, s4113; CHECK-NEXT: vmov.f32 s3, s5114; CHECK-NEXT: subs r1, r1, r2115; CHECK-NEXT: add r2, sp, #104116; CHECK-NEXT: vldrw.u32 q5, [r2]117; CHECK-NEXT: sbcs r0, r3118; CHECK-NEXT: vmov q4[2], q4[0], r1, lr119; CHECK-NEXT: vmov q4[3], q4[1], r0, r12120; CHECK-NEXT: vmov r0, r1, d6121; CHECK-NEXT: vmov r2, r3, d11122; CHECK-NEXT: vmov.f32 s0, s16123; CHECK-NEXT: vmov.f32 s4, s18124; CHECK-NEXT: vmov.f32 s1, s17125; CHECK-NEXT: vmov.f32 s5, s19126; CHECK-NEXT: adds.w lr, r2, r0127; CHECK-NEXT: adc.w r12, r3, r1128; CHECK-NEXT: add r1, sp, #88129; CHECK-NEXT: vldrw.u32 q6, [r1]130; CHECK-NEXT: vmov r2, r3, d4131; CHECK-NEXT: vmov r1, r0, d13132; CHECK-NEXT: adds r1, r1, r2133; CHECK-NEXT: adcs r0, r3134; CHECK-NEXT: vmov q4[2], q4[0], r1, lr135; CHECK-NEXT: vmov q4[3], q4[1], r0, r12136; CHECK-NEXT: vmov r0, r1, d7137; CHECK-NEXT: vmov r2, r3, d10138; CHECK-NEXT: subs.w lr, r2, r0139; CHECK-NEXT: sbc.w r12, r3, r1140; CHECK-NEXT: vmov r2, r3, d5141; CHECK-NEXT: vmov r1, r0, d12142; CHECK-NEXT: vmov.f32 s10, s16143; CHECK-NEXT: vmov.f32 s11, s17144; CHECK-NEXT: subs r1, r1, r2145; CHECK-NEXT: vmov q3[2], q3[0], r1, lr146; CHECK-NEXT: sbcs r0, r3147; CHECK-NEXT: vmov q3[3], q3[1], r0, r12148; CHECK-NEXT: vmov.f32 s16, s14149; CHECK-NEXT: vmov.f32 s8, s12150; CHECK-NEXT: vmov.f32 s17, s15151; CHECK-NEXT: vmov.f32 s9, s13152; CHECK-NEXT: vmov q3, q4153; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}154; CHECK-NEXT: pop {r7, pc}155entry:156 %a.real = shufflevector <8 x i64> %a, <8 x i64> zeroinitializer, <4 x i32> <i32 0, i32 2, i32 4, i32 6>157 %a.imag = shufflevector <8 x i64> %a, <8 x i64> zeroinitializer, <4 x i32> <i32 1, i32 3, i32 5, i32 7>158 %b.real = shufflevector <8 x i64> %b, <8 x i64> zeroinitializer, <4 x i32> <i32 0, i32 2, i32 4, i32 6>159 %b.imag = shufflevector <8 x i64> %b, <8 x i64> zeroinitializer, <4 x i32> <i32 1, i32 3, i32 5, i32 7>160 %0 = sub <4 x i64> %b.real, %a.imag161 %1 = add <4 x i64> %b.imag, %a.real162 %interleaved.vec = shufflevector <4 x i64> %0, <4 x i64> %1, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>163 ret <8 x i64> %interleaved.vec164}165