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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s3; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve %s -early-live-intervals -verify-machineinstrs -o - | FileCheck %s4 5define arm_aapcs_vfpcc <2 x i64> @ctlz_2i64_0_t(<2 x i64> %src){6; CHECK-LABEL: ctlz_2i64_0_t:7; CHECK: @ %bb.0: @ %entry8; CHECK-NEXT: vmov r0, r1, d19; CHECK-NEXT: clz r0, r010; CHECK-NEXT: cmp r1, #011; CHECK-NEXT: add.w r0, r0, #3212; CHECK-NEXT: it ne13; CHECK-NEXT: clzne r0, r114; CHECK-NEXT: vmov s2, r015; CHECK-NEXT: vmov r0, r1, d016; CHECK-NEXT: vldr s1, .LCPI0_017; CHECK-NEXT: vmov.f32 s3, s118; CHECK-NEXT: clz r0, r019; CHECK-NEXT: cmp r1, #020; CHECK-NEXT: add.w r0, r0, #3221; CHECK-NEXT: it ne22; CHECK-NEXT: clzne r0, r123; CHECK-NEXT: vmov s0, r024; CHECK-NEXT: bx lr25; CHECK-NEXT: .p2align 226; CHECK-NEXT: @ %bb.1:27; CHECK-NEXT: .LCPI0_0:28; CHECK-NEXT: .long 0x00000000 @ float 029entry:30 %0 = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %src, i1 0)31 ret <2 x i64> %032}33 34define arm_aapcs_vfpcc <4 x i32> @ctlz_4i32_0_t(<4 x i32> %src){35; CHECK-LABEL: ctlz_4i32_0_t:36; CHECK: @ %bb.0: @ %entry37; CHECK-NEXT: vclz.i32 q0, q038; CHECK-NEXT: bx lr39entry:40 %0 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %src, i1 0)41 ret <4 x i32> %042}43 44define arm_aapcs_vfpcc <8 x i16> @ctlz_8i16_0_t(<8 x i16> %src){45; CHECK-LABEL: ctlz_8i16_0_t:46; CHECK: @ %bb.0: @ %entry47; CHECK-NEXT: vclz.i16 q0, q048; CHECK-NEXT: bx lr49entry:50 %0 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %src, i1 0)51 ret <8 x i16> %052}53 54define arm_aapcs_vfpcc <16 x i8> @ctlz_16i8_0_t(<16 x i8> %src){55; CHECK-LABEL: ctlz_16i8_0_t:56; CHECK: @ %bb.0: @ %entry57; CHECK-NEXT: vclz.i8 q0, q058; CHECK-NEXT: bx lr59entry:60 %0 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %src, i1 0)61 ret <16 x i8> %062}63 64define arm_aapcs_vfpcc <2 x i64> @ctlz_2i64_1_t(<2 x i64> %src){65; CHECK-LABEL: ctlz_2i64_1_t:66; CHECK: @ %bb.0: @ %entry67; CHECK-NEXT: vmov r0, r1, d168; CHECK-NEXT: clz r0, r069; CHECK-NEXT: cmp r1, #070; CHECK-NEXT: add.w r0, r0, #3271; CHECK-NEXT: it ne72; CHECK-NEXT: clzne r0, r173; CHECK-NEXT: vmov s2, r074; CHECK-NEXT: vmov r0, r1, d075; CHECK-NEXT: vldr s1, .LCPI4_076; CHECK-NEXT: vmov.f32 s3, s177; CHECK-NEXT: clz r0, r078; CHECK-NEXT: cmp r1, #079; CHECK-NEXT: add.w r0, r0, #3280; CHECK-NEXT: it ne81; CHECK-NEXT: clzne r0, r182; CHECK-NEXT: vmov s0, r083; CHECK-NEXT: bx lr84; CHECK-NEXT: .p2align 285; CHECK-NEXT: @ %bb.1:86; CHECK-NEXT: .LCPI4_0:87; CHECK-NEXT: .long 0x00000000 @ float 088entry:89 %0 = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %src, i1 1)90 ret <2 x i64> %091}92 93define arm_aapcs_vfpcc <4 x i32> @ctlz_4i32_1_t(<4 x i32> %src){94; CHECK-LABEL: ctlz_4i32_1_t:95; CHECK: @ %bb.0: @ %entry96; CHECK-NEXT: vclz.i32 q0, q097; CHECK-NEXT: bx lr98entry:99 %0 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %src, i1 1)100 ret <4 x i32> %0101}102 103define arm_aapcs_vfpcc <8 x i16> @ctlz_8i16_1_t(<8 x i16> %src){104; CHECK-LABEL: ctlz_8i16_1_t:105; CHECK: @ %bb.0: @ %entry106; CHECK-NEXT: vclz.i16 q0, q0107; CHECK-NEXT: bx lr108entry:109 %0 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %src, i1 1)110 ret <8 x i16> %0111}112 113define arm_aapcs_vfpcc <16 x i8> @ctlz_16i8_1_t(<16 x i8> %src){114; CHECK-LABEL: ctlz_16i8_1_t:115; CHECK: @ %bb.0: @ %entry116; CHECK-NEXT: vclz.i8 q0, q0117; CHECK-NEXT: bx lr118entry:119 %0 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %src, i1 1)120 ret <16 x i8> %0121}122 123 124declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1)125declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1)126declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1)127declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1)128