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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK3 4define arm_aapcs_vfpcc <2 x i64> @ctpop_2i64_t(<2 x i64> %src){5; CHECK-LABEL: ctpop_2i64_t:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: .save {r4, r5, r7, lr}8; CHECK-NEXT: push {r4, r5, r7, lr}9; CHECK-NEXT: vmov r1, r2, d110; CHECK-NEXT: mov.w lr, #143165576511; CHECK-NEXT: vmov r3, r4, d012; CHECK-NEXT: mov.w r12, #85899345913; CHECK-NEXT: vldr s1, .LCPI0_014; CHECK-NEXT: vmov.f32 s3, s115; CHECK-NEXT: and.w r0, lr, r2, lsr #116; CHECK-NEXT: subs r0, r2, r017; CHECK-NEXT: and.w r2, r12, r0, lsr #218; CHECK-NEXT: bic r0, r0, #-85899346019; CHECK-NEXT: add r0, r220; CHECK-NEXT: and.w r2, lr, r1, lsr #121; CHECK-NEXT: subs r1, r1, r222; CHECK-NEXT: add.w r0, r0, r0, lsr #423; CHECK-NEXT: and.w r2, r12, r1, lsr #224; CHECK-NEXT: bic r1, r1, #-85899346025; CHECK-NEXT: add r1, r226; CHECK-NEXT: and.w r2, lr, r3, lsr #127; CHECK-NEXT: subs r2, r3, r228; CHECK-NEXT: bic r5, r0, #-25264513629; CHECK-NEXT: add.w r1, r1, r1, lsr #430; CHECK-NEXT: mov.w r0, #1684300931; CHECK-NEXT: and.w r3, r12, r2, lsr #232; CHECK-NEXT: bic r2, r2, #-85899346033; CHECK-NEXT: add r2, r334; CHECK-NEXT: and.w r3, lr, r4, lsr #135; CHECK-NEXT: subs r3, r4, r336; CHECK-NEXT: bic r1, r1, #-25264513637; CHECK-NEXT: add.w r2, r2, r2, lsr #438; CHECK-NEXT: muls r5, r0, r539; CHECK-NEXT: and.w r4, r12, r3, lsr #240; CHECK-NEXT: bic r3, r3, #-85899346041; CHECK-NEXT: bic r2, r2, #-25264513642; CHECK-NEXT: add r3, r443; CHECK-NEXT: muls r1, r0, r144; CHECK-NEXT: add.w r3, r3, r3, lsr #445; CHECK-NEXT: muls r2, r0, r246; CHECK-NEXT: bic r3, r3, #-25264513647; CHECK-NEXT: muls r0, r3, r048; CHECK-NEXT: lsrs r1, r1, #2449; CHECK-NEXT: add.w r1, r1, r5, lsr #2450; CHECK-NEXT: lsrs r2, r2, #2451; CHECK-NEXT: vmov s2, r152; CHECK-NEXT: add.w r0, r2, r0, lsr #2453; CHECK-NEXT: vmov s0, r054; CHECK-NEXT: pop {r4, r5, r7, pc}55; CHECK-NEXT: .p2align 256; CHECK-NEXT: @ %bb.1:57; CHECK-NEXT: .LCPI0_0:58; CHECK-NEXT: .long 0x00000000 @ float 059entry:60 %0 = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %src)61 ret <2 x i64> %062}63 64define arm_aapcs_vfpcc <4 x i32> @ctpop_4i32_t(<4 x i32> %src){65; CHECK-LABEL: ctpop_4i32_t:66; CHECK: @ %bb.0: @ %entry67; CHECK-NEXT: .vsave {d8, d9, d10, d11}68; CHECK-NEXT: vpush {d8, d9, d10, d11}69; CHECK-NEXT: vmov.i8 q4, #0x5570; CHECK-NEXT: vshr.u32 q5, q0, #171; CHECK-NEXT: vand q4, q5, q472; CHECK-NEXT: vmov.i8 q3, #0x3373; CHECK-NEXT: vsub.i32 q0, q0, q474; CHECK-NEXT: vmov.i8 q2, #0xf75; CHECK-NEXT: vshr.u32 q4, q0, #276; CHECK-NEXT: vand q0, q0, q377; CHECK-NEXT: vand q4, q4, q378; CHECK-NEXT: vmov.i8 q1, #0x179; CHECK-NEXT: vadd.i32 q0, q0, q480; CHECK-NEXT: vshr.u32 q3, q0, #481; CHECK-NEXT: vadd.i32 q0, q0, q382; CHECK-NEXT: vand q0, q0, q283; CHECK-NEXT: vmul.i32 q0, q0, q184; CHECK-NEXT: vshr.u32 q0, q0, #2485; CHECK-NEXT: vpop {d8, d9, d10, d11}86; CHECK-NEXT: bx lr87entry:88 %0 = call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %src)89 ret <4 x i32> %090}91 92define arm_aapcs_vfpcc <8 x i16> @ctpop_8i16_t(<8 x i16> %src){93; CHECK-LABEL: ctpop_8i16_t:94; CHECK: @ %bb.0: @ %entry95; CHECK-NEXT: .vsave {d8, d9, d10, d11}96; CHECK-NEXT: vpush {d8, d9, d10, d11}97; CHECK-NEXT: vmov.i8 q4, #0x5598; CHECK-NEXT: vshr.u16 q5, q0, #199; CHECK-NEXT: vand q4, q5, q4100; CHECK-NEXT: vmov.i8 q3, #0x33101; CHECK-NEXT: vsub.i16 q0, q0, q4102; CHECK-NEXT: vmov.i8 q2, #0xf103; CHECK-NEXT: vshr.u16 q4, q0, #2104; CHECK-NEXT: vand q0, q0, q3105; CHECK-NEXT: vand q4, q4, q3106; CHECK-NEXT: vmov.i8 q1, #0x1107; CHECK-NEXT: vadd.i16 q0, q0, q4108; CHECK-NEXT: vshr.u16 q3, q0, #4109; CHECK-NEXT: vadd.i16 q0, q0, q3110; CHECK-NEXT: vand q0, q0, q2111; CHECK-NEXT: vmul.i16 q0, q0, q1112; CHECK-NEXT: vshr.u16 q0, q0, #8113; CHECK-NEXT: vpop {d8, d9, d10, d11}114; CHECK-NEXT: bx lr115entry:116 %0 = call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %src)117 ret <8 x i16> %0118}119 120define arm_aapcs_vfpcc <16 x i8> @ctpop_16i8_t(<16 x i8> %src){121; CHECK-LABEL: ctpop_16i8_t:122; CHECK: @ %bb.0: @ %entry123; CHECK-NEXT: .vsave {d8, d9}124; CHECK-NEXT: vpush {d8, d9}125; CHECK-NEXT: vmov.i8 q3, #0x55126; CHECK-NEXT: vshr.u8 q4, q0, #1127; CHECK-NEXT: vand q3, q4, q3128; CHECK-NEXT: vmov.i8 q2, #0x33129; CHECK-NEXT: vsub.i8 q0, q0, q3130; CHECK-NEXT: vmov.i8 q1, #0xf131; CHECK-NEXT: vshr.u8 q3, q0, #2132; CHECK-NEXT: vand q0, q0, q2133; CHECK-NEXT: vand q3, q3, q2134; CHECK-NEXT: vadd.i8 q0, q0, q3135; CHECK-NEXT: vshr.u8 q2, q0, #4136; CHECK-NEXT: vadd.i8 q0, q0, q2137; CHECK-NEXT: vand q0, q0, q1138; CHECK-NEXT: vpop {d8, d9}139; CHECK-NEXT: bx lr140entry:141 %0 = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %src)142 ret <16 x i8> %0143}144 145declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>)146declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>)147declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16>)148declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>)149