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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s3 4define arm_aapcs_vfpcc <2 x i64> @cttz_2i64_0_t(<2 x i64> %src){5; CHECK-LABEL: cttz_2i64_0_t:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vmov r0, r1, d18; CHECK-NEXT: rbit r1, r19; CHECK-NEXT: rbit r2, r010; CHECK-NEXT: clz r1, r111; CHECK-NEXT: cmp r0, #012; CHECK-NEXT: add.w r1, r1, #3213; CHECK-NEXT: it ne14; CHECK-NEXT: clzne r1, r215; CHECK-NEXT: vmov s2, r116; CHECK-NEXT: vmov r0, r1, d017; CHECK-NEXT: vldr s1, .LCPI0_018; CHECK-NEXT: vmov.f32 s3, s119; CHECK-NEXT: rbit r1, r120; CHECK-NEXT: rbit r2, r021; CHECK-NEXT: clz r1, r122; CHECK-NEXT: cmp r0, #023; CHECK-NEXT: add.w r1, r1, #3224; CHECK-NEXT: it ne25; CHECK-NEXT: clzne r1, r226; CHECK-NEXT: vmov s0, r127; CHECK-NEXT: bx lr28; CHECK-NEXT: .p2align 229; CHECK-NEXT: @ %bb.1:30; CHECK-NEXT: .LCPI0_0:31; CHECK-NEXT: .long 0x00000000 @ float 032entry:33 %0 = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %src, i1 0)34 ret <2 x i64> %035}36 37define arm_aapcs_vfpcc <4 x i32> @cttz_4i32_0_t(<4 x i32> %src){38; CHECK-LABEL: cttz_4i32_0_t:39; CHECK: @ %bb.0: @ %entry40; CHECK-NEXT: movs r0, #3241; CHECK-NEXT: vbrsr.32 q0, q0, r042; CHECK-NEXT: vclz.i32 q0, q043; CHECK-NEXT: bx lr44entry:45 %0 = call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %src, i1 0)46 ret <4 x i32> %047}48 49define arm_aapcs_vfpcc <8 x i16> @cttz_8i16_0_t(<8 x i16> %src){50; CHECK-LABEL: cttz_8i16_0_t:51; CHECK: @ %bb.0: @ %entry52; CHECK-NEXT: movs r0, #1653; CHECK-NEXT: vbrsr.16 q0, q0, r054; CHECK-NEXT: vclz.i16 q0, q055; CHECK-NEXT: bx lr56entry:57 %0 = call <8 x i16> @llvm.cttz.v8i16(<8 x i16> %src, i1 0)58 ret <8 x i16> %059}60 61define arm_aapcs_vfpcc <16 x i8> @cttz_16i8_0_t(<16 x i8> %src) {62; CHECK-LABEL: cttz_16i8_0_t:63; CHECK: @ %bb.0: @ %entry64; CHECK-NEXT: movs r0, #865; CHECK-NEXT: vbrsr.8 q0, q0, r066; CHECK-NEXT: vclz.i8 q0, q067; CHECK-NEXT: bx lr68entry:69 %0 = call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %src, i1 0)70 ret <16 x i8> %071}72 73define arm_aapcs_vfpcc <2 x i64> @cttz_2i64_1_t(<2 x i64> %src){74; CHECK-LABEL: cttz_2i64_1_t:75; CHECK: @ %bb.0: @ %entry76; CHECK-NEXT: vmov r0, r1, d177; CHECK-NEXT: rbit r1, r178; CHECK-NEXT: rbit r2, r079; CHECK-NEXT: clz r1, r180; CHECK-NEXT: cmp r0, #081; CHECK-NEXT: add.w r1, r1, #3282; CHECK-NEXT: it ne83; CHECK-NEXT: clzne r1, r284; CHECK-NEXT: vmov s2, r185; CHECK-NEXT: vmov r0, r1, d086; CHECK-NEXT: vldr s1, .LCPI4_087; CHECK-NEXT: vmov.f32 s3, s188; CHECK-NEXT: rbit r1, r189; CHECK-NEXT: rbit r2, r090; CHECK-NEXT: clz r1, r191; CHECK-NEXT: cmp r0, #092; CHECK-NEXT: add.w r1, r1, #3293; CHECK-NEXT: it ne94; CHECK-NEXT: clzne r1, r295; CHECK-NEXT: vmov s0, r196; CHECK-NEXT: bx lr97; CHECK-NEXT: .p2align 298; CHECK-NEXT: @ %bb.1:99; CHECK-NEXT: .LCPI4_0:100; CHECK-NEXT: .long 0x00000000 @ float 0101entry:102 %0 = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %src, i1 1)103 ret <2 x i64> %0104}105 106define arm_aapcs_vfpcc <4 x i32> @cttz_4i32_1_t(<4 x i32> %src){107; CHECK-LABEL: cttz_4i32_1_t:108; CHECK: @ %bb.0: @ %entry109; CHECK-NEXT: movs r0, #32110; CHECK-NEXT: vbrsr.32 q0, q0, r0111; CHECK-NEXT: vclz.i32 q0, q0112; CHECK-NEXT: bx lr113entry:114 %0 = call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %src, i1 1)115 ret <4 x i32> %0116}117 118define arm_aapcs_vfpcc <8 x i16> @cttz_8i16_1_t(<8 x i16> %src){119; CHECK-LABEL: cttz_8i16_1_t:120; CHECK: @ %bb.0: @ %entry121; CHECK-NEXT: movs r0, #16122; CHECK-NEXT: vbrsr.16 q0, q0, r0123; CHECK-NEXT: vclz.i16 q0, q0124; CHECK-NEXT: bx lr125entry:126 %0 = call <8 x i16> @llvm.cttz.v8i16(<8 x i16> %src, i1 1)127 ret <8 x i16> %0128}129 130define arm_aapcs_vfpcc <16 x i8> @cttz_16i8_1_t(<16 x i8> %src) {131; CHECK-LABEL: cttz_16i8_1_t:132; CHECK: @ %bb.0: @ %entry133; CHECK-NEXT: movs r0, #8134; CHECK-NEXT: vbrsr.8 q0, q0, r0135; CHECK-NEXT: vclz.i8 q0, q0136; CHECK-NEXT: bx lr137entry:138 %0 = call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %src, i1 1)139 ret <16 x i8> %0140}141 142 143declare <2 x i64> @llvm.cttz.v2i64(<2 x i64>, i1)144declare <4 x i32> @llvm.cttz.v4i32(<4 x i32>, i1)145declare <8 x i16> @llvm.cttz.v8i16(<8 x i16>, i1)146declare <16 x i8> @llvm.cttz.v16i8(<16 x i8>, i1)147