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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK3; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK4 5define arm_aapcs_vfpcc <4 x i32> @udiv_i32(<4 x i32> %in1, <4 x i32> %in2) {6; CHECK-LABEL: udiv_i32:7; CHECK: @ %bb.0: @ %entry8; CHECK-NEXT: .save {r4, r5, r7, lr}9; CHECK-NEXT: push {r4, r5, r7, lr}10; CHECK-NEXT: vmov r0, r12, d311; CHECK-NEXT: vmov r2, lr, d112; CHECK-NEXT: vmov r1, r3, d213; CHECK-NEXT: udiv r0, r2, r014; CHECK-NEXT: vmov r4, r5, d015; CHECK-NEXT: udiv r1, r4, r116; CHECK-NEXT: vmov q0[2], q0[0], r1, r017; CHECK-NEXT: udiv r0, lr, r1218; CHECK-NEXT: udiv r1, r5, r319; CHECK-NEXT: vmov q0[3], q0[1], r1, r020; CHECK-NEXT: pop {r4, r5, r7, pc}21entry:22 %out = udiv <4 x i32> %in1, %in223 ret <4 x i32> %out24}25 26define arm_aapcs_vfpcc <4 x i32> @sdiv_i32(<4 x i32> %in1, <4 x i32> %in2) {27; CHECK-LABEL: sdiv_i32:28; CHECK: @ %bb.0: @ %entry29; CHECK-NEXT: .save {r4, r5, r7, lr}30; CHECK-NEXT: push {r4, r5, r7, lr}31; CHECK-NEXT: vmov r0, r12, d332; CHECK-NEXT: vmov r2, lr, d133; CHECK-NEXT: vmov r1, r3, d234; CHECK-NEXT: sdiv r0, r2, r035; CHECK-NEXT: vmov r4, r5, d036; CHECK-NEXT: sdiv r1, r4, r137; CHECK-NEXT: vmov q0[2], q0[0], r1, r038; CHECK-NEXT: sdiv r0, lr, r1239; CHECK-NEXT: sdiv r1, r5, r340; CHECK-NEXT: vmov q0[3], q0[1], r1, r041; CHECK-NEXT: pop {r4, r5, r7, pc}42entry:43 %out = sdiv <4 x i32> %in1, %in244 ret <4 x i32> %out45}46 47define arm_aapcs_vfpcc <4 x i32> @urem_i32(<4 x i32> %in1, <4 x i32> %in2) {48; CHECK-LABEL: urem_i32:49; CHECK: @ %bb.0: @ %entry50; CHECK-NEXT: .save {r4, r5, r7, lr}51; CHECK-NEXT: push {r4, r5, r7, lr}52; CHECK-NEXT: vmov r0, r12, d353; CHECK-NEXT: vmov r2, r3, d154; CHECK-NEXT: vmov r1, lr, d255; CHECK-NEXT: udiv r4, r2, r056; CHECK-NEXT: mls r0, r4, r0, r257; CHECK-NEXT: vmov r2, r4, d058; CHECK-NEXT: udiv r5, r2, r159; CHECK-NEXT: mls r1, r5, r1, r260; CHECK-NEXT: udiv r2, r3, r1261; CHECK-NEXT: mls r2, r2, r12, r362; CHECK-NEXT: udiv r3, r4, lr63; CHECK-NEXT: vmov q0[2], q0[0], r1, r064; CHECK-NEXT: mls r3, r3, lr, r465; CHECK-NEXT: vmov q0[3], q0[1], r3, r266; CHECK-NEXT: pop {r4, r5, r7, pc}67entry:68 %out = urem <4 x i32> %in1, %in269 ret <4 x i32> %out70}71 72define arm_aapcs_vfpcc <4 x i32> @srem_i32(<4 x i32> %in1, <4 x i32> %in2) {73; CHECK-LABEL: srem_i32:74; CHECK: @ %bb.0: @ %entry75; CHECK-NEXT: .save {r4, r5, r7, lr}76; CHECK-NEXT: push {r4, r5, r7, lr}77; CHECK-NEXT: vmov r0, r12, d378; CHECK-NEXT: vmov r2, r3, d179; CHECK-NEXT: vmov r1, lr, d280; CHECK-NEXT: sdiv r4, r2, r081; CHECK-NEXT: mls r0, r4, r0, r282; CHECK-NEXT: vmov r2, r4, d083; CHECK-NEXT: sdiv r5, r2, r184; CHECK-NEXT: mls r1, r5, r1, r285; CHECK-NEXT: sdiv r2, r3, r1286; CHECK-NEXT: mls r2, r2, r12, r387; CHECK-NEXT: sdiv r3, r4, lr88; CHECK-NEXT: vmov q0[2], q0[0], r1, r089; CHECK-NEXT: mls r3, r3, lr, r490; CHECK-NEXT: vmov q0[3], q0[1], r3, r291; CHECK-NEXT: pop {r4, r5, r7, pc}92entry:93 %out = srem <4 x i32> %in1, %in294 ret <4 x i32> %out95}96 97 98define arm_aapcs_vfpcc <8 x i16> @udiv_i16(<8 x i16> %in1, <8 x i16> %in2) {99; CHECK-LABEL: udiv_i16:100; CHECK: @ %bb.0: @ %entry101; CHECK-NEXT: vmov.u16 r0, q1[0]102; CHECK-NEXT: vmov.u16 r1, q0[0]103; CHECK-NEXT: udiv r0, r1, r0104; CHECK-NEXT: vmov.u16 r1, q1[1]105; CHECK-NEXT: vmov.u16 r2, q0[1]106; CHECK-NEXT: vmov.16 q2[0], r0107; CHECK-NEXT: udiv r1, r2, r1108; CHECK-NEXT: vmov.u16 r0, q1[2]109; CHECK-NEXT: vmov.16 q2[1], r1110; CHECK-NEXT: vmov.u16 r1, q0[2]111; CHECK-NEXT: udiv r0, r1, r0112; CHECK-NEXT: vmov.u16 r1, q0[3]113; CHECK-NEXT: vmov.16 q2[2], r0114; CHECK-NEXT: vmov.u16 r0, q1[3]115; CHECK-NEXT: udiv r0, r1, r0116; CHECK-NEXT: vmov.u16 r1, q0[4]117; CHECK-NEXT: vmov.16 q2[3], r0118; CHECK-NEXT: vmov.u16 r0, q1[4]119; CHECK-NEXT: udiv r0, r1, r0120; CHECK-NEXT: vmov.u16 r1, q0[5]121; CHECK-NEXT: vmov.16 q2[4], r0122; CHECK-NEXT: vmov.u16 r0, q1[5]123; CHECK-NEXT: udiv r0, r1, r0124; CHECK-NEXT: vmov.u16 r1, q0[6]125; CHECK-NEXT: vmov.16 q2[5], r0126; CHECK-NEXT: vmov.u16 r0, q1[6]127; CHECK-NEXT: udiv r0, r1, r0128; CHECK-NEXT: vmov.u16 r1, q0[7]129; CHECK-NEXT: vmov.16 q2[6], r0130; CHECK-NEXT: vmov.u16 r0, q1[7]131; CHECK-NEXT: udiv r0, r1, r0132; CHECK-NEXT: vmov.16 q2[7], r0133; CHECK-NEXT: vmov q0, q2134; CHECK-NEXT: bx lr135entry:136 %out = udiv <8 x i16> %in1, %in2137 ret <8 x i16> %out138}139 140define arm_aapcs_vfpcc <8 x i16> @sdiv_i16(<8 x i16> %in1, <8 x i16> %in2) {141; CHECK-LABEL: sdiv_i16:142; CHECK: @ %bb.0: @ %entry143; CHECK-NEXT: vmov.s16 r0, q1[0]144; CHECK-NEXT: vmov.s16 r1, q0[0]145; CHECK-NEXT: sdiv r0, r1, r0146; CHECK-NEXT: vmov.s16 r1, q1[1]147; CHECK-NEXT: vmov.s16 r2, q0[1]148; CHECK-NEXT: vmov.16 q2[0], r0149; CHECK-NEXT: sdiv r1, r2, r1150; CHECK-NEXT: vmov.s16 r0, q1[2]151; CHECK-NEXT: vmov.16 q2[1], r1152; CHECK-NEXT: vmov.s16 r1, q0[2]153; CHECK-NEXT: sdiv r0, r1, r0154; CHECK-NEXT: vmov.s16 r1, q0[3]155; CHECK-NEXT: vmov.16 q2[2], r0156; CHECK-NEXT: vmov.s16 r0, q1[3]157; CHECK-NEXT: sdiv r0, r1, r0158; CHECK-NEXT: vmov.s16 r1, q0[4]159; CHECK-NEXT: vmov.16 q2[3], r0160; CHECK-NEXT: vmov.s16 r0, q1[4]161; CHECK-NEXT: sdiv r0, r1, r0162; CHECK-NEXT: vmov.s16 r1, q0[5]163; CHECK-NEXT: vmov.16 q2[4], r0164; CHECK-NEXT: vmov.s16 r0, q1[5]165; CHECK-NEXT: sdiv r0, r1, r0166; CHECK-NEXT: vmov.s16 r1, q0[6]167; CHECK-NEXT: vmov.16 q2[5], r0168; CHECK-NEXT: vmov.s16 r0, q1[6]169; CHECK-NEXT: sdiv r0, r1, r0170; CHECK-NEXT: vmov.s16 r1, q0[7]171; CHECK-NEXT: vmov.16 q2[6], r0172; CHECK-NEXT: vmov.s16 r0, q1[7]173; CHECK-NEXT: sdiv r0, r1, r0174; CHECK-NEXT: vmov.16 q2[7], r0175; CHECK-NEXT: vmov q0, q2176; CHECK-NEXT: bx lr177entry:178 %out = sdiv <8 x i16> %in1, %in2179 ret <8 x i16> %out180}181 182define arm_aapcs_vfpcc <8 x i16> @urem_i16(<8 x i16> %in1, <8 x i16> %in2) {183; CHECK-LABEL: urem_i16:184; CHECK: @ %bb.0: @ %entry185; CHECK-NEXT: .save {r4, r5, r6, r7, lr}186; CHECK-NEXT: push {r4, r5, r6, r7, lr}187; CHECK-NEXT: vmov.u16 r0, q1[6]188; CHECK-NEXT: vmov.u16 r1, q0[6]189; CHECK-NEXT: udiv r2, r1, r0190; CHECK-NEXT: mls r12, r2, r0, r1191; CHECK-NEXT: vmov.u16 r1, q1[7]192; CHECK-NEXT: vmov.u16 r2, q0[7]193; CHECK-NEXT: udiv r3, r2, r1194; CHECK-NEXT: mls lr, r3, r1, r2195; CHECK-NEXT: vmov.u16 r2, q1[4]196; CHECK-NEXT: vmov.u16 r3, q0[4]197; CHECK-NEXT: udiv r0, r3, r2198; CHECK-NEXT: mls r2, r0, r2, r3199; CHECK-NEXT: vmov.u16 r0, q1[5]200; CHECK-NEXT: vmov.u16 r3, q0[5]201; CHECK-NEXT: udiv r1, r3, r0202; CHECK-NEXT: mls r0, r1, r0, r3203; CHECK-NEXT: vmov.u16 r1, q1[2]204; CHECK-NEXT: vmov.u16 r3, q0[2]205; CHECK-NEXT: udiv r4, r3, r1206; CHECK-NEXT: mls r1, r4, r1, r3207; CHECK-NEXT: vmov.u16 r3, q1[3]208; CHECK-NEXT: vmov.u16 r4, q0[3]209; CHECK-NEXT: udiv r5, r4, r3210; CHECK-NEXT: mls r3, r5, r3, r4211; CHECK-NEXT: vmov.u16 r4, q1[0]212; CHECK-NEXT: vmov.u16 r5, q0[0]213; CHECK-NEXT: udiv r6, r5, r4214; CHECK-NEXT: mls r4, r6, r4, r5215; CHECK-NEXT: vmov.u16 r6, q0[1]216; CHECK-NEXT: vmov.u16 r5, q1[1]217; CHECK-NEXT: udiv r7, r6, r5218; CHECK-NEXT: vmov.16 q0[0], r4219; CHECK-NEXT: mls r5, r7, r5, r6220; CHECK-NEXT: vmov.16 q0[1], r5221; CHECK-NEXT: vmov.16 q0[2], r1222; CHECK-NEXT: vmov.16 q0[3], r3223; CHECK-NEXT: vmov.16 q0[4], r2224; CHECK-NEXT: vmov.16 q0[5], r0225; CHECK-NEXT: vmov.16 q0[6], r12226; CHECK-NEXT: vmov.16 q0[7], lr227; CHECK-NEXT: pop {r4, r5, r6, r7, pc}228entry:229 %out = urem <8 x i16> %in1, %in2230 ret <8 x i16> %out231}232 233define arm_aapcs_vfpcc <8 x i16> @srem_i16(<8 x i16> %in1, <8 x i16> %in2) {234; CHECK-LABEL: srem_i16:235; CHECK: @ %bb.0: @ %entry236; CHECK-NEXT: .save {r4, r5, r6, r7, lr}237; CHECK-NEXT: push {r4, r5, r6, r7, lr}238; CHECK-NEXT: vmov.s16 r0, q1[6]239; CHECK-NEXT: vmov.s16 r1, q0[6]240; CHECK-NEXT: sdiv r2, r1, r0241; CHECK-NEXT: mls r12, r2, r0, r1242; CHECK-NEXT: vmov.s16 r1, q1[7]243; CHECK-NEXT: vmov.s16 r2, q0[7]244; CHECK-NEXT: sdiv r3, r2, r1245; CHECK-NEXT: mls lr, r3, r1, r2246; CHECK-NEXT: vmov.s16 r2, q1[4]247; CHECK-NEXT: vmov.s16 r3, q0[4]248; CHECK-NEXT: sdiv r0, r3, r2249; CHECK-NEXT: mls r2, r0, r2, r3250; CHECK-NEXT: vmov.s16 r0, q1[5]251; CHECK-NEXT: vmov.s16 r3, q0[5]252; CHECK-NEXT: sdiv r1, r3, r0253; CHECK-NEXT: mls r0, r1, r0, r3254; CHECK-NEXT: vmov.s16 r1, q1[2]255; CHECK-NEXT: vmov.s16 r3, q0[2]256; CHECK-NEXT: sdiv r4, r3, r1257; CHECK-NEXT: mls r1, r4, r1, r3258; CHECK-NEXT: vmov.s16 r3, q1[3]259; CHECK-NEXT: vmov.s16 r4, q0[3]260; CHECK-NEXT: sdiv r5, r4, r3261; CHECK-NEXT: mls r3, r5, r3, r4262; CHECK-NEXT: vmov.s16 r4, q1[0]263; CHECK-NEXT: vmov.s16 r5, q0[0]264; CHECK-NEXT: sdiv r6, r5, r4265; CHECK-NEXT: mls r4, r6, r4, r5266; CHECK-NEXT: vmov.s16 r6, q0[1]267; CHECK-NEXT: vmov.s16 r5, q1[1]268; CHECK-NEXT: sdiv r7, r6, r5269; CHECK-NEXT: vmov.16 q0[0], r4270; CHECK-NEXT: mls r5, r7, r5, r6271; CHECK-NEXT: vmov.16 q0[1], r5272; CHECK-NEXT: vmov.16 q0[2], r1273; CHECK-NEXT: vmov.16 q0[3], r3274; CHECK-NEXT: vmov.16 q0[4], r2275; CHECK-NEXT: vmov.16 q0[5], r0276; CHECK-NEXT: vmov.16 q0[6], r12277; CHECK-NEXT: vmov.16 q0[7], lr278; CHECK-NEXT: pop {r4, r5, r6, r7, pc}279entry:280 %out = srem <8 x i16> %in1, %in2281 ret <8 x i16> %out282}283 284 285define arm_aapcs_vfpcc <16 x i8> @udiv_i8(<16 x i8> %in1, <16 x i8> %in2) {286; CHECK-LABEL: udiv_i8:287; CHECK: @ %bb.0: @ %entry288; CHECK-NEXT: vmov.u8 r0, q1[0]289; CHECK-NEXT: vmov.u8 r1, q0[0]290; CHECK-NEXT: udiv r0, r1, r0291; CHECK-NEXT: vmov.u8 r1, q1[1]292; CHECK-NEXT: vmov.u8 r2, q0[1]293; CHECK-NEXT: vmov.8 q2[0], r0294; CHECK-NEXT: udiv r1, r2, r1295; CHECK-NEXT: vmov.u8 r0, q1[2]296; CHECK-NEXT: vmov.8 q2[1], r1297; CHECK-NEXT: vmov.u8 r1, q0[2]298; CHECK-NEXT: udiv r0, r1, r0299; CHECK-NEXT: vmov.u8 r1, q0[3]300; CHECK-NEXT: vmov.8 q2[2], r0301; CHECK-NEXT: vmov.u8 r0, q1[3]302; CHECK-NEXT: udiv r0, r1, r0303; CHECK-NEXT: vmov.u8 r1, q0[4]304; CHECK-NEXT: vmov.8 q2[3], r0305; CHECK-NEXT: vmov.u8 r0, q1[4]306; CHECK-NEXT: udiv r0, r1, r0307; CHECK-NEXT: vmov.u8 r1, q0[5]308; CHECK-NEXT: vmov.8 q2[4], r0309; CHECK-NEXT: vmov.u8 r0, q1[5]310; CHECK-NEXT: udiv r0, r1, r0311; CHECK-NEXT: vmov.u8 r1, q0[6]312; CHECK-NEXT: vmov.8 q2[5], r0313; CHECK-NEXT: vmov.u8 r0, q1[6]314; CHECK-NEXT: udiv r0, r1, r0315; CHECK-NEXT: vmov.u8 r1, q0[7]316; CHECK-NEXT: vmov.8 q2[6], r0317; CHECK-NEXT: vmov.u8 r0, q1[7]318; CHECK-NEXT: udiv r0, r1, r0319; CHECK-NEXT: vmov.u8 r1, q0[8]320; CHECK-NEXT: vmov.8 q2[7], r0321; CHECK-NEXT: vmov.u8 r0, q1[8]322; CHECK-NEXT: udiv r0, r1, r0323; CHECK-NEXT: vmov.u8 r1, q0[9]324; CHECK-NEXT: vmov.8 q2[8], r0325; CHECK-NEXT: vmov.u8 r0, q1[9]326; CHECK-NEXT: udiv r0, r1, r0327; CHECK-NEXT: vmov.u8 r1, q0[10]328; CHECK-NEXT: vmov.8 q2[9], r0329; CHECK-NEXT: vmov.u8 r0, q1[10]330; CHECK-NEXT: udiv r0, r1, r0331; CHECK-NEXT: vmov.u8 r1, q0[11]332; CHECK-NEXT: vmov.8 q2[10], r0333; CHECK-NEXT: vmov.u8 r0, q1[11]334; CHECK-NEXT: udiv r0, r1, r0335; CHECK-NEXT: vmov.u8 r1, q0[12]336; CHECK-NEXT: vmov.8 q2[11], r0337; CHECK-NEXT: vmov.u8 r0, q1[12]338; CHECK-NEXT: udiv r0, r1, r0339; CHECK-NEXT: vmov.u8 r1, q0[13]340; CHECK-NEXT: vmov.8 q2[12], r0341; CHECK-NEXT: vmov.u8 r0, q1[13]342; CHECK-NEXT: udiv r0, r1, r0343; CHECK-NEXT: vmov.u8 r1, q0[14]344; CHECK-NEXT: vmov.8 q2[13], r0345; CHECK-NEXT: vmov.u8 r0, q1[14]346; CHECK-NEXT: udiv r0, r1, r0347; CHECK-NEXT: vmov.u8 r1, q0[15]348; CHECK-NEXT: vmov.8 q2[14], r0349; CHECK-NEXT: vmov.u8 r0, q1[15]350; CHECK-NEXT: udiv r0, r1, r0351; CHECK-NEXT: vmov.8 q2[15], r0352; CHECK-NEXT: vmov q0, q2353; CHECK-NEXT: bx lr354entry:355 %out = udiv <16 x i8> %in1, %in2356 ret <16 x i8> %out357}358 359define arm_aapcs_vfpcc <16 x i8> @sdiv_i8(<16 x i8> %in1, <16 x i8> %in2) {360; CHECK-LABEL: sdiv_i8:361; CHECK: @ %bb.0: @ %entry362; CHECK-NEXT: vmov.s8 r0, q1[0]363; CHECK-NEXT: vmov.s8 r1, q0[0]364; CHECK-NEXT: sdiv r0, r1, r0365; CHECK-NEXT: vmov.s8 r1, q1[1]366; CHECK-NEXT: vmov.s8 r2, q0[1]367; CHECK-NEXT: vmov.8 q2[0], r0368; CHECK-NEXT: sdiv r1, r2, r1369; CHECK-NEXT: vmov.s8 r0, q1[2]370; CHECK-NEXT: vmov.8 q2[1], r1371; CHECK-NEXT: vmov.s8 r1, q0[2]372; CHECK-NEXT: sdiv r0, r1, r0373; CHECK-NEXT: vmov.s8 r1, q0[3]374; CHECK-NEXT: vmov.8 q2[2], r0375; CHECK-NEXT: vmov.s8 r0, q1[3]376; CHECK-NEXT: sdiv r0, r1, r0377; CHECK-NEXT: vmov.s8 r1, q0[4]378; CHECK-NEXT: vmov.8 q2[3], r0379; CHECK-NEXT: vmov.s8 r0, q1[4]380; CHECK-NEXT: sdiv r0, r1, r0381; CHECK-NEXT: vmov.s8 r1, q0[5]382; CHECK-NEXT: vmov.8 q2[4], r0383; CHECK-NEXT: vmov.s8 r0, q1[5]384; CHECK-NEXT: sdiv r0, r1, r0385; CHECK-NEXT: vmov.s8 r1, q0[6]386; CHECK-NEXT: vmov.8 q2[5], r0387; CHECK-NEXT: vmov.s8 r0, q1[6]388; CHECK-NEXT: sdiv r0, r1, r0389; CHECK-NEXT: vmov.s8 r1, q0[7]390; CHECK-NEXT: vmov.8 q2[6], r0391; CHECK-NEXT: vmov.s8 r0, q1[7]392; CHECK-NEXT: sdiv r0, r1, r0393; CHECK-NEXT: vmov.s8 r1, q0[8]394; CHECK-NEXT: vmov.8 q2[7], r0395; CHECK-NEXT: vmov.s8 r0, q1[8]396; CHECK-NEXT: sdiv r0, r1, r0397; CHECK-NEXT: vmov.s8 r1, q0[9]398; CHECK-NEXT: vmov.8 q2[8], r0399; CHECK-NEXT: vmov.s8 r0, q1[9]400; CHECK-NEXT: sdiv r0, r1, r0401; CHECK-NEXT: vmov.s8 r1, q0[10]402; CHECK-NEXT: vmov.8 q2[9], r0403; CHECK-NEXT: vmov.s8 r0, q1[10]404; CHECK-NEXT: sdiv r0, r1, r0405; CHECK-NEXT: vmov.s8 r1, q0[11]406; CHECK-NEXT: vmov.8 q2[10], r0407; CHECK-NEXT: vmov.s8 r0, q1[11]408; CHECK-NEXT: sdiv r0, r1, r0409; CHECK-NEXT: vmov.s8 r1, q0[12]410; CHECK-NEXT: vmov.8 q2[11], r0411; CHECK-NEXT: vmov.s8 r0, q1[12]412; CHECK-NEXT: sdiv r0, r1, r0413; CHECK-NEXT: vmov.s8 r1, q0[13]414; CHECK-NEXT: vmov.8 q2[12], r0415; CHECK-NEXT: vmov.s8 r0, q1[13]416; CHECK-NEXT: sdiv r0, r1, r0417; CHECK-NEXT: vmov.s8 r1, q0[14]418; CHECK-NEXT: vmov.8 q2[13], r0419; CHECK-NEXT: vmov.s8 r0, q1[14]420; CHECK-NEXT: sdiv r0, r1, r0421; CHECK-NEXT: vmov.s8 r1, q0[15]422; CHECK-NEXT: vmov.8 q2[14], r0423; CHECK-NEXT: vmov.s8 r0, q1[15]424; CHECK-NEXT: sdiv r0, r1, r0425; CHECK-NEXT: vmov.8 q2[15], r0426; CHECK-NEXT: vmov q0, q2427; CHECK-NEXT: bx lr428entry:429 %out = sdiv <16 x i8> %in1, %in2430 ret <16 x i8> %out431}432 433define arm_aapcs_vfpcc <16 x i8> @urem_i8(<16 x i8> %in1, <16 x i8> %in2) {434; CHECK-LABEL: urem_i8:435; CHECK: @ %bb.0: @ %entry436; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}437; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, lr}438; CHECK-NEXT: vmov.u8 r0, q1[14]439; CHECK-NEXT: vmov.u8 r1, q0[14]440; CHECK-NEXT: udiv r2, r1, r0441; CHECK-NEXT: mls r12, r2, r0, r1442; CHECK-NEXT: vmov.u8 r0, q1[15]443; CHECK-NEXT: vmov.u8 r1, q0[15]444; CHECK-NEXT: udiv r2, r1, r0445; CHECK-NEXT: mls lr, r2, r0, r1446; CHECK-NEXT: vmov.u8 r0, q1[12]447; CHECK-NEXT: vmov.u8 r1, q0[12]448; CHECK-NEXT: udiv r2, r1, r0449; CHECK-NEXT: mls r8, r2, r0, r1450; CHECK-NEXT: vmov.u8 r0, q1[13]451; CHECK-NEXT: vmov.u8 r1, q0[13]452; CHECK-NEXT: udiv r3, r1, r0453; CHECK-NEXT: mls r3, r3, r0, r1454; CHECK-NEXT: vmov.u8 r0, q1[10]455; CHECK-NEXT: vmov.u8 r1, q0[10]456; CHECK-NEXT: udiv r4, r1, r0457; CHECK-NEXT: mls r0, r4, r0, r1458; CHECK-NEXT: vmov.u8 r1, q1[11]459; CHECK-NEXT: vmov.u8 r4, q0[11]460; CHECK-NEXT: udiv r5, r4, r1461; CHECK-NEXT: mls r1, r5, r1, r4462; CHECK-NEXT: vmov.u8 r4, q1[8]463; CHECK-NEXT: vmov.u8 r5, q0[8]464; CHECK-NEXT: udiv r6, r5, r4465; CHECK-NEXT: mls r4, r6, r4, r5466; CHECK-NEXT: vmov.u8 r5, q1[0]467; CHECK-NEXT: vmov.u8 r6, q0[0]468; CHECK-NEXT: udiv r7, r6, r5469; CHECK-NEXT: mls r5, r7, r5, r6470; CHECK-NEXT: vmov.u8 r6, q1[1]471; CHECK-NEXT: vmov.u8 r7, q0[1]472; CHECK-NEXT: udiv r2, r7, r6473; CHECK-NEXT: vmov.8 q2[0], r5474; CHECK-NEXT: mls r2, r2, r6, r7475; CHECK-NEXT: vmov.u8 r5, q0[2]476; CHECK-NEXT: vmov.8 q2[1], r2477; CHECK-NEXT: vmov.u8 r2, q1[2]478; CHECK-NEXT: udiv r6, r5, r2479; CHECK-NEXT: mls r2, r6, r2, r5480; CHECK-NEXT: vmov.u8 r5, q0[3]481; CHECK-NEXT: vmov.8 q2[2], r2482; CHECK-NEXT: vmov.u8 r2, q1[3]483; CHECK-NEXT: udiv r6, r5, r2484; CHECK-NEXT: mls r2, r6, r2, r5485; CHECK-NEXT: vmov.u8 r5, q0[4]486; CHECK-NEXT: vmov.8 q2[3], r2487; CHECK-NEXT: vmov.u8 r2, q1[4]488; CHECK-NEXT: udiv r6, r5, r2489; CHECK-NEXT: mls r2, r6, r2, r5490; CHECK-NEXT: vmov.u8 r5, q0[5]491; CHECK-NEXT: vmov.8 q2[4], r2492; CHECK-NEXT: vmov.u8 r2, q1[5]493; CHECK-NEXT: udiv r6, r5, r2494; CHECK-NEXT: mls r2, r6, r2, r5495; CHECK-NEXT: vmov.u8 r5, q0[6]496; CHECK-NEXT: vmov.8 q2[5], r2497; CHECK-NEXT: vmov.u8 r2, q1[6]498; CHECK-NEXT: udiv r6, r5, r2499; CHECK-NEXT: mls r2, r6, r2, r5500; CHECK-NEXT: vmov.u8 r5, q0[7]501; CHECK-NEXT: vmov.8 q2[6], r2502; CHECK-NEXT: vmov.u8 r2, q1[7]503; CHECK-NEXT: udiv r6, r5, r2504; CHECK-NEXT: mls r2, r6, r2, r5505; CHECK-NEXT: vmov.u8 r5, q0[9]506; CHECK-NEXT: vmov.8 q2[7], r2507; CHECK-NEXT: vmov.u8 r2, q1[9]508; CHECK-NEXT: udiv r6, r5, r2509; CHECK-NEXT: vmov.8 q2[8], r4510; CHECK-NEXT: mls r2, r6, r2, r5511; CHECK-NEXT: vmov.8 q2[9], r2512; CHECK-NEXT: vmov.8 q2[10], r0513; CHECK-NEXT: vmov.8 q2[11], r1514; CHECK-NEXT: vmov.8 q2[12], r8515; CHECK-NEXT: vmov.8 q2[13], r3516; CHECK-NEXT: vmov.8 q2[14], r12517; CHECK-NEXT: vmov.8 q2[15], lr518; CHECK-NEXT: vmov q0, q2519; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, pc}520entry:521 %out = urem <16 x i8> %in1, %in2522 ret <16 x i8> %out523}524 525define arm_aapcs_vfpcc <16 x i8> @srem_i8(<16 x i8> %in1, <16 x i8> %in2) {526; CHECK-LABEL: srem_i8:527; CHECK: @ %bb.0: @ %entry528; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}529; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, lr}530; CHECK-NEXT: vmov.s8 r0, q1[14]531; CHECK-NEXT: vmov.s8 r1, q0[14]532; CHECK-NEXT: sdiv r2, r1, r0533; CHECK-NEXT: mls r12, r2, r0, r1534; CHECK-NEXT: vmov.s8 r0, q1[15]535; CHECK-NEXT: vmov.s8 r1, q0[15]536; CHECK-NEXT: sdiv r2, r1, r0537; CHECK-NEXT: mls lr, r2, r0, r1538; CHECK-NEXT: vmov.s8 r0, q1[12]539; CHECK-NEXT: vmov.s8 r1, q0[12]540; CHECK-NEXT: sdiv r2, r1, r0541; CHECK-NEXT: mls r8, r2, r0, r1542; CHECK-NEXT: vmov.s8 r0, q1[13]543; CHECK-NEXT: vmov.s8 r1, q0[13]544; CHECK-NEXT: sdiv r3, r1, r0545; CHECK-NEXT: mls r3, r3, r0, r1546; CHECK-NEXT: vmov.s8 r0, q1[10]547; CHECK-NEXT: vmov.s8 r1, q0[10]548; CHECK-NEXT: sdiv r4, r1, r0549; CHECK-NEXT: mls r0, r4, r0, r1550; CHECK-NEXT: vmov.s8 r1, q1[11]551; CHECK-NEXT: vmov.s8 r4, q0[11]552; CHECK-NEXT: sdiv r5, r4, r1553; CHECK-NEXT: mls r1, r5, r1, r4554; CHECK-NEXT: vmov.s8 r4, q1[8]555; CHECK-NEXT: vmov.s8 r5, q0[8]556; CHECK-NEXT: sdiv r6, r5, r4557; CHECK-NEXT: mls r4, r6, r4, r5558; CHECK-NEXT: vmov.s8 r5, q1[0]559; CHECK-NEXT: vmov.s8 r6, q0[0]560; CHECK-NEXT: sdiv r7, r6, r5561; CHECK-NEXT: mls r5, r7, r5, r6562; CHECK-NEXT: vmov.s8 r6, q1[1]563; CHECK-NEXT: vmov.s8 r7, q0[1]564; CHECK-NEXT: sdiv r2, r7, r6565; CHECK-NEXT: vmov.8 q2[0], r5566; CHECK-NEXT: mls r2, r2, r6, r7567; CHECK-NEXT: vmov.s8 r5, q0[2]568; CHECK-NEXT: vmov.8 q2[1], r2569; CHECK-NEXT: vmov.s8 r2, q1[2]570; CHECK-NEXT: sdiv r6, r5, r2571; CHECK-NEXT: mls r2, r6, r2, r5572; CHECK-NEXT: vmov.s8 r5, q0[3]573; CHECK-NEXT: vmov.8 q2[2], r2574; CHECK-NEXT: vmov.s8 r2, q1[3]575; CHECK-NEXT: sdiv r6, r5, r2576; CHECK-NEXT: mls r2, r6, r2, r5577; CHECK-NEXT: vmov.s8 r5, q0[4]578; CHECK-NEXT: vmov.8 q2[3], r2579; CHECK-NEXT: vmov.s8 r2, q1[4]580; CHECK-NEXT: sdiv r6, r5, r2581; CHECK-NEXT: mls r2, r6, r2, r5582; CHECK-NEXT: vmov.s8 r5, q0[5]583; CHECK-NEXT: vmov.8 q2[4], r2584; CHECK-NEXT: vmov.s8 r2, q1[5]585; CHECK-NEXT: sdiv r6, r5, r2586; CHECK-NEXT: mls r2, r6, r2, r5587; CHECK-NEXT: vmov.s8 r5, q0[6]588; CHECK-NEXT: vmov.8 q2[5], r2589; CHECK-NEXT: vmov.s8 r2, q1[6]590; CHECK-NEXT: sdiv r6, r5, r2591; CHECK-NEXT: mls r2, r6, r2, r5592; CHECK-NEXT: vmov.s8 r5, q0[7]593; CHECK-NEXT: vmov.8 q2[6], r2594; CHECK-NEXT: vmov.s8 r2, q1[7]595; CHECK-NEXT: sdiv r6, r5, r2596; CHECK-NEXT: mls r2, r6, r2, r5597; CHECK-NEXT: vmov.s8 r5, q0[9]598; CHECK-NEXT: vmov.8 q2[7], r2599; CHECK-NEXT: vmov.s8 r2, q1[9]600; CHECK-NEXT: sdiv r6, r5, r2601; CHECK-NEXT: vmov.8 q2[8], r4602; CHECK-NEXT: mls r2, r6, r2, r5603; CHECK-NEXT: vmov.8 q2[9], r2604; CHECK-NEXT: vmov.8 q2[10], r0605; CHECK-NEXT: vmov.8 q2[11], r1606; CHECK-NEXT: vmov.8 q2[12], r8607; CHECK-NEXT: vmov.8 q2[13], r3608; CHECK-NEXT: vmov.8 q2[14], r12609; CHECK-NEXT: vmov.8 q2[15], lr610; CHECK-NEXT: vmov q0, q2611; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, pc}612entry:613 %out = srem <16 x i8> %in1, %in2614 ret <16 x i8> %out615}616 617define arm_aapcs_vfpcc <2 x i64> @udiv_i64(<2 x i64> %in1, <2 x i64> %in2) {618; CHECK-LABEL: udiv_i64:619; CHECK: @ %bb.0: @ %entry620; CHECK-NEXT: .save {r4, r5, r7, lr}621; CHECK-NEXT: push {r4, r5, r7, lr}622; CHECK-NEXT: .vsave {d8, d9, d10, d11}623; CHECK-NEXT: vpush {d8, d9, d10, d11}624; CHECK-NEXT: vmov q4, q1625; CHECK-NEXT: vmov q5, q0626; CHECK-NEXT: vmov r0, r1, d11627; CHECK-NEXT: vmov r2, r3, d9628; CHECK-NEXT: bl __aeabi_uldivmod629; CHECK-NEXT: mov r4, r0630; CHECK-NEXT: mov r5, r1631; CHECK-NEXT: vmov r0, r1, d10632; CHECK-NEXT: vmov r2, r3, d8633; CHECK-NEXT: bl __aeabi_uldivmod634; CHECK-NEXT: vmov q0[2], q0[0], r0, r4635; CHECK-NEXT: vmov q0[3], q0[1], r1, r5636; CHECK-NEXT: vpop {d8, d9, d10, d11}637; CHECK-NEXT: pop {r4, r5, r7, pc}638entry:639 %out = udiv <2 x i64> %in1, %in2640 ret <2 x i64> %out641}642 643define arm_aapcs_vfpcc <2 x i64> @sdiv_i64(<2 x i64> %in1, <2 x i64> %in2) {644; CHECK-LABEL: sdiv_i64:645; CHECK: @ %bb.0: @ %entry646; CHECK-NEXT: .save {r4, r5, r7, lr}647; CHECK-NEXT: push {r4, r5, r7, lr}648; CHECK-NEXT: .vsave {d8, d9, d10, d11}649; CHECK-NEXT: vpush {d8, d9, d10, d11}650; CHECK-NEXT: vmov q4, q1651; CHECK-NEXT: vmov q5, q0652; CHECK-NEXT: vmov r0, r1, d11653; CHECK-NEXT: vmov r2, r3, d9654; CHECK-NEXT: bl __aeabi_ldivmod655; CHECK-NEXT: mov r4, r0656; CHECK-NEXT: mov r5, r1657; CHECK-NEXT: vmov r0, r1, d10658; CHECK-NEXT: vmov r2, r3, d8659; CHECK-NEXT: bl __aeabi_ldivmod660; CHECK-NEXT: vmov q0[2], q0[0], r0, r4661; CHECK-NEXT: vmov q0[3], q0[1], r1, r5662; CHECK-NEXT: vpop {d8, d9, d10, d11}663; CHECK-NEXT: pop {r4, r5, r7, pc}664entry:665 %out = sdiv <2 x i64> %in1, %in2666 ret <2 x i64> %out667}668 669define arm_aapcs_vfpcc <2 x i64> @urem_i64(<2 x i64> %in1, <2 x i64> %in2) {670; CHECK-LABEL: urem_i64:671; CHECK: @ %bb.0: @ %entry672; CHECK-NEXT: .save {r4, r5, r7, lr}673; CHECK-NEXT: push {r4, r5, r7, lr}674; CHECK-NEXT: .vsave {d8, d9, d10, d11}675; CHECK-NEXT: vpush {d8, d9, d10, d11}676; CHECK-NEXT: vmov q4, q1677; CHECK-NEXT: vmov q5, q0678; CHECK-NEXT: vmov r0, r1, d11679; CHECK-NEXT: vmov r2, r3, d9680; CHECK-NEXT: bl __aeabi_uldivmod681; CHECK-NEXT: mov r4, r2682; CHECK-NEXT: mov r5, r3683; CHECK-NEXT: vmov r0, r1, d10684; CHECK-NEXT: vmov r2, r3, d8685; CHECK-NEXT: bl __aeabi_uldivmod686; CHECK-NEXT: vmov q0[2], q0[0], r2, r4687; CHECK-NEXT: vmov q0[3], q0[1], r3, r5688; CHECK-NEXT: vpop {d8, d9, d10, d11}689; CHECK-NEXT: pop {r4, r5, r7, pc}690entry:691 %out = urem <2 x i64> %in1, %in2692 ret <2 x i64> %out693}694 695define arm_aapcs_vfpcc <2 x i64> @srem_i64(<2 x i64> %in1, <2 x i64> %in2) {696; CHECK-LABEL: srem_i64:697; CHECK: @ %bb.0: @ %entry698; CHECK-NEXT: .save {r4, r5, r7, lr}699; CHECK-NEXT: push {r4, r5, r7, lr}700; CHECK-NEXT: .vsave {d8, d9, d10, d11}701; CHECK-NEXT: vpush {d8, d9, d10, d11}702; CHECK-NEXT: vmov q4, q1703; CHECK-NEXT: vmov q5, q0704; CHECK-NEXT: vmov r0, r1, d11705; CHECK-NEXT: vmov r2, r3, d9706; CHECK-NEXT: bl __aeabi_ldivmod707; CHECK-NEXT: mov r4, r2708; CHECK-NEXT: mov r5, r3709; CHECK-NEXT: vmov r0, r1, d10710; CHECK-NEXT: vmov r2, r3, d8711; CHECK-NEXT: bl __aeabi_ldivmod712; CHECK-NEXT: vmov q0[2], q0[0], r2, r4713; CHECK-NEXT: vmov q0[3], q0[1], r3, r5714; CHECK-NEXT: vpop {d8, d9, d10, d11}715; CHECK-NEXT: pop {r4, r5, r7, pc}716entry:717 %out = srem <2 x i64> %in1, %in2718 ret <2 x i64> %out719}720 721 722 723 724define arm_aapcs_vfpcc <4 x float> @fdiv_f32(<4 x float> %in1, <4 x float> %in2) {725; CHECK-LABEL: fdiv_f32:726; CHECK: @ %bb.0: @ %entry727; CHECK-NEXT: vdiv.f32 s3, s3, s7728; CHECK-NEXT: vdiv.f32 s2, s2, s6729; CHECK-NEXT: vdiv.f32 s1, s1, s5730; CHECK-NEXT: vdiv.f32 s0, s0, s4731; CHECK-NEXT: bx lr732entry:733 %out = fdiv <4 x float> %in1, %in2734 ret <4 x float> %out735}736 737define arm_aapcs_vfpcc <4 x float> @frem_f32(<4 x float> %in1, <4 x float> %in2) {738; CHECK-LABEL: frem_f32:739; CHECK: @ %bb.0: @ %entry740; CHECK-NEXT: .save {r4, r5, r6, lr}741; CHECK-NEXT: push {r4, r5, r6, lr}742; CHECK-NEXT: .vsave {d8, d9, d10, d11}743; CHECK-NEXT: vpush {d8, d9, d10, d11}744; CHECK-NEXT: vmov q4, q1745; CHECK-NEXT: vmov q5, q0746; CHECK-NEXT: vmov r0, r4, d11747; CHECK-NEXT: vmov r1, r5, d9748; CHECK-NEXT: bl fmodf749; CHECK-NEXT: mov r6, r0750; CHECK-NEXT: mov r0, r4751; CHECK-NEXT: mov r1, r5752; CHECK-NEXT: bl fmodf753; CHECK-NEXT: vmov r4, r2, d10754; CHECK-NEXT: vmov r5, r1, d8755; CHECK-NEXT: vmov s19, r0756; CHECK-NEXT: vmov s18, r6757; CHECK-NEXT: mov r0, r2758; CHECK-NEXT: bl fmodf759; CHECK-NEXT: vmov s17, r0760; CHECK-NEXT: mov r0, r4761; CHECK-NEXT: mov r1, r5762; CHECK-NEXT: bl fmodf763; CHECK-NEXT: vmov s16, r0764; CHECK-NEXT: vmov q0, q4765; CHECK-NEXT: vpop {d8, d9, d10, d11}766; CHECK-NEXT: pop {r4, r5, r6, pc}767entry:768 %out = frem <4 x float> %in1, %in2769 ret <4 x float> %out770}771 772 773define arm_aapcs_vfpcc <8 x half> @fdiv_f16(<8 x half> %in1, <8 x half> %in2) {774; CHECK-LABEL: fdiv_f16:775; CHECK: @ %bb.0: @ %entry776; CHECK-NEXT: vmovx.f16 s10, s0777; CHECK-NEXT: vmovx.f16 s8, s4778; CHECK-NEXT: vdiv.f16 s0, s0, s4779; CHECK-NEXT: vdiv.f16 s8, s10, s8780; CHECK-NEXT: vins.f16 s0, s8781; CHECK-NEXT: vmovx.f16 s8, s1782; CHECK-NEXT: vmovx.f16 s4, s5783; CHECK-NEXT: vdiv.f16 s1, s1, s5784; CHECK-NEXT: vdiv.f16 s4, s8, s4785; CHECK-NEXT: vmovx.f16 s8, s2786; CHECK-NEXT: vins.f16 s1, s4787; CHECK-NEXT: vmovx.f16 s4, s6788; CHECK-NEXT: vdiv.f16 s2, s2, s6789; CHECK-NEXT: vdiv.f16 s4, s8, s4790; CHECK-NEXT: vins.f16 s2, s4791; CHECK-NEXT: vmovx.f16 s6, s3792; CHECK-NEXT: vmovx.f16 s4, s7793; CHECK-NEXT: vdiv.f16 s3, s3, s7794; CHECK-NEXT: vdiv.f16 s4, s6, s4795; CHECK-NEXT: vins.f16 s3, s4796; CHECK-NEXT: bx lr797entry:798 %out = fdiv <8 x half> %in1, %in2799 ret <8 x half> %out800}801 802define arm_aapcs_vfpcc <8 x half> @frem_f16(<8 x half> %in1, <8 x half> %in2) {803; CHECK-LABEL: frem_f16:804; CHECK: @ %bb.0: @ %entry805; CHECK-NEXT: .save {r7, lr}806; CHECK-NEXT: push {r7, lr}807; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}808; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}809; CHECK-NEXT: vmov q5, q0810; CHECK-NEXT: vmov q4, q1811; CHECK-NEXT: vcvtb.f32.f16 s0, s20812; CHECK-NEXT: vmov r0, s0813; CHECK-NEXT: vcvtb.f32.f16 s0, s16814; CHECK-NEXT: vmov r1, s0815; CHECK-NEXT: bl fmodf816; CHECK-NEXT: vcvtt.f32.f16 s0, s20817; CHECK-NEXT: vmov r2, s0818; CHECK-NEXT: vcvtt.f32.f16 s0, s16819; CHECK-NEXT: vmov r1, s0820; CHECK-NEXT: vmov s16, r0821; CHECK-NEXT: mov r0, r2822; CHECK-NEXT: bl fmodf823; CHECK-NEXT: vmov s0, r0824; CHECK-NEXT: vcvtb.f16.f32 s24, s16825; CHECK-NEXT: vcvtt.f16.f32 s24, s0826; CHECK-NEXT: vcvtb.f32.f16 s0, s21827; CHECK-NEXT: vmov r0, s0828; CHECK-NEXT: vcvtb.f32.f16 s0, s17829; CHECK-NEXT: vmov r1, s0830; CHECK-NEXT: bl fmodf831; CHECK-NEXT: vmov s0, r0832; CHECK-NEXT: vcvtb.f16.f32 s25, s0833; CHECK-NEXT: vcvtt.f32.f16 s0, s21834; CHECK-NEXT: vmov r0, s0835; CHECK-NEXT: vcvtt.f32.f16 s0, s17836; CHECK-NEXT: vmov r1, s0837; CHECK-NEXT: bl fmodf838; CHECK-NEXT: vmov s0, r0839; CHECK-NEXT: vcvtt.f16.f32 s25, s0840; CHECK-NEXT: vcvtb.f32.f16 s0, s22841; CHECK-NEXT: vmov r0, s0842; CHECK-NEXT: vcvtb.f32.f16 s0, s18843; CHECK-NEXT: vmov r1, s0844; CHECK-NEXT: bl fmodf845; CHECK-NEXT: vmov s0, r0846; CHECK-NEXT: vcvtb.f16.f32 s26, s0847; CHECK-NEXT: vcvtt.f32.f16 s0, s22848; CHECK-NEXT: vmov r0, s0849; CHECK-NEXT: vcvtt.f32.f16 s0, s18850; CHECK-NEXT: vmov r1, s0851; CHECK-NEXT: bl fmodf852; CHECK-NEXT: vmov s0, r0853; CHECK-NEXT: vcvtt.f16.f32 s26, s0854; CHECK-NEXT: vcvtb.f32.f16 s0, s23855; CHECK-NEXT: vmov r0, s0856; CHECK-NEXT: vcvtb.f32.f16 s0, s19857; CHECK-NEXT: vmov r1, s0858; CHECK-NEXT: bl fmodf859; CHECK-NEXT: vmov s0, r0860; CHECK-NEXT: vcvtb.f16.f32 s27, s0861; CHECK-NEXT: vcvtt.f32.f16 s0, s23862; CHECK-NEXT: vmov r0, s0863; CHECK-NEXT: vcvtt.f32.f16 s0, s19864; CHECK-NEXT: vmov r1, s0865; CHECK-NEXT: bl fmodf866; CHECK-NEXT: vmov s0, r0867; CHECK-NEXT: vcvtt.f16.f32 s27, s0868; CHECK-NEXT: vmov q0, q6869; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}870; CHECK-NEXT: pop {r7, pc}871entry:872 %out = frem <8 x half> %in1, %in2873 ret <8 x half> %out874}875 876define arm_aapcs_vfpcc <2 x double> @fdiv_f64(<2 x double> %in1, <2 x double> %in2) {877; CHECK-LABEL: fdiv_f64:878; CHECK: @ %bb.0: @ %entry879; CHECK-NEXT: .save {r7, lr}880; CHECK-NEXT: push {r7, lr}881; CHECK-NEXT: .vsave {d8, d9, d10, d11}882; CHECK-NEXT: vpush {d8, d9, d10, d11}883; CHECK-NEXT: vmov q4, q1884; CHECK-NEXT: vmov q5, q0885; CHECK-NEXT: vmov r0, r1, d11886; CHECK-NEXT: vmov r2, r3, d9887; CHECK-NEXT: bl __aeabi_ddiv888; CHECK-NEXT: vmov lr, r12, d10889; CHECK-NEXT: vmov r2, r3, d8890; CHECK-NEXT: vmov d9, r0, r1891; CHECK-NEXT: mov r0, lr892; CHECK-NEXT: mov r1, r12893; CHECK-NEXT: bl __aeabi_ddiv894; CHECK-NEXT: vmov d8, r0, r1895; CHECK-NEXT: vmov q0, q4896; CHECK-NEXT: vpop {d8, d9, d10, d11}897; CHECK-NEXT: pop {r7, pc}898entry:899 %out = fdiv <2 x double> %in1, %in2900 ret <2 x double> %out901}902 903define arm_aapcs_vfpcc <2 x double> @frem_f64(<2 x double> %in1, <2 x double> %in2) {904; CHECK-LABEL: frem_f64:905; CHECK: @ %bb.0: @ %entry906; CHECK-NEXT: .save {r7, lr}907; CHECK-NEXT: push {r7, lr}908; CHECK-NEXT: .vsave {d8, d9, d10, d11}909; CHECK-NEXT: vpush {d8, d9, d10, d11}910; CHECK-NEXT: vmov q4, q1911; CHECK-NEXT: vmov q5, q0912; CHECK-NEXT: vmov r0, r1, d11913; CHECK-NEXT: vmov r2, r3, d9914; CHECK-NEXT: bl fmod915; CHECK-NEXT: vmov lr, r12, d10916; CHECK-NEXT: vmov r2, r3, d8917; CHECK-NEXT: vmov d9, r0, r1918; CHECK-NEXT: mov r0, lr919; CHECK-NEXT: mov r1, r12920; CHECK-NEXT: bl fmod921; CHECK-NEXT: vmov d8, r0, r1922; CHECK-NEXT: vmov q0, q4923; CHECK-NEXT: vpop {d8, d9, d10, d11}924; CHECK-NEXT: pop {r7, pc}925entry:926 %out = frem <2 x double> %in1, %in2927 ret <2 x double> %out928}929 930 931