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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -float-abi=hard -verify-machineinstrs %s -o - | FileCheck %s3 4define float @add_f32(<8 x float> %a, <4 x float> %b) {5; CHECK-LABEL: add_f32:6; CHECK: @ %bb.0:7; CHECK-NEXT: vadd.f32 q0, q0, q18; CHECK-NEXT: vadd.f32 q0, q0, q29; CHECK-NEXT: vadd.f32 s2, s2, s310; CHECK-NEXT: vadd.f32 s0, s0, s111; CHECK-NEXT: vadd.f32 s0, s0, s212; CHECK-NEXT: bx lr13 %r1 = call fast float @llvm.vector.reduce.fadd.f32.v8f32(float -0.0, <8 x float> %a)14 %r2 = call fast float @llvm.vector.reduce.fadd.f32.v4f32(float -0.0, <4 x float> %b)15 %r = fadd fast float %r1, %r216 ret float %r17}18 19define float @fmul_f32(<8 x float> %a, <4 x float> %b) {20; CHECK-LABEL: fmul_f32:21; CHECK: @ %bb.0:22; CHECK-NEXT: vmul.f32 q0, q0, q123; CHECK-NEXT: vmul.f32 q0, q0, q224; CHECK-NEXT: vmul.f32 s2, s2, s325; CHECK-NEXT: vmul.f32 s0, s0, s126; CHECK-NEXT: vmul.f32 s0, s0, s227; CHECK-NEXT: bx lr28 %r1 = call fast float @llvm.vector.reduce.fmul.f32.v8f32(float 1.0, <8 x float> %a)29 %r2 = call fast float @llvm.vector.reduce.fmul.f32.v4f32(float 1.0, <4 x float> %b)30 %r = fmul fast float %r1, %r231 ret float %r32}33 34define float @fmin_f32(<8 x float> %a, <4 x float> %b) {35; CHECK-LABEL: fmin_f32:36; CHECK: @ %bb.0:37; CHECK-NEXT: vminnm.f32 q0, q0, q138; CHECK-NEXT: vminnm.f32 q0, q0, q239; CHECK-NEXT: vminnm.f32 s2, s2, s340; CHECK-NEXT: vminnm.f32 s0, s0, s141; CHECK-NEXT: vminnm.f32 s0, s0, s242; CHECK-NEXT: bx lr43 %r1 = call fast float @llvm.vector.reduce.fmin.v8f32(<8 x float> %a)44 %r2 = call fast float @llvm.vector.reduce.fmin.v4f32(<4 x float> %b)45 %r = call float @llvm.minnum.f32(float %r1, float %r2)46 ret float %r47}48 49define float @fmax_f32(<8 x float> %a, <4 x float> %b) {50; CHECK-LABEL: fmax_f32:51; CHECK: @ %bb.0:52; CHECK-NEXT: vmaxnm.f32 q0, q0, q153; CHECK-NEXT: vmaxnm.f32 q0, q0, q254; CHECK-NEXT: vmaxnm.f32 s2, s2, s355; CHECK-NEXT: vmaxnm.f32 s0, s0, s156; CHECK-NEXT: vmaxnm.f32 s0, s0, s257; CHECK-NEXT: bx lr58 %r1 = call fast float @llvm.vector.reduce.fmax.v8f32(<8 x float> %a)59 %r2 = call fast float @llvm.vector.reduce.fmax.v4f32(<4 x float> %b)60 %r = call float @llvm.maxnum.f32(float %r1, float %r2)61 ret float %r62}63 64 65define i32 @add_i32(<8 x i32> %a, <4 x i32> %b) {66; CHECK-LABEL: add_i32:67; CHECK: @ %bb.0:68; CHECK-NEXT: vaddv.u32 r0, q169; CHECK-NEXT: vaddva.u32 r0, q070; CHECK-NEXT: vaddva.u32 r0, q271; CHECK-NEXT: bx lr72 %r1 = call i32 @llvm.vector.reduce.add.i32.v8i32(<8 x i32> %a)73 %r2 = call i32 @llvm.vector.reduce.add.i32.v4i32(<4 x i32> %b)74 %r = add i32 %r1, %r275 ret i32 %r76}77 78define i16 @add_ext_i16(<16 x i8> %a, <16 x i8> %b) {79; CHECK-LABEL: add_ext_i16:80; CHECK: @ %bb.0:81; CHECK-NEXT: vaddv.u8 r0, q182; CHECK-NEXT: vaddva.u8 r0, q083; CHECK-NEXT: bx lr84 %ae = zext <16 x i8> %a to <16 x i16>85 %be = zext <16 x i8> %b to <16 x i16>86 %r1 = call i16 @llvm.vector.reduce.add.i16.v16i16(<16 x i16> %ae)87 %r2 = call i16 @llvm.vector.reduce.add.i16.v16i16(<16 x i16> %be)88 %r = add i16 %r1, %r289 ret i16 %r90}91 92define i16 @add_ext_v32i16(<32 x i8> %a, <16 x i8> %b) {93; CHECK-LABEL: add_ext_v32i16:94; CHECK: @ %bb.0:95; CHECK-NEXT: .pad #3296; CHECK-NEXT: sub sp, #3297; CHECK-NEXT: mov r1, sp98; CHECK-NEXT: add r2, sp, #1699; CHECK-NEXT: vstrw.32 q0, [r1]100; CHECK-NEXT: vstrw.32 q1, [r2]101; CHECK-NEXT: vldrb.u16 q1, [r2]102; CHECK-NEXT: vldrb.u16 q0, [r1]103; CHECK-NEXT: vaddv.u16 r0, q1104; CHECK-NEXT: vaddva.u16 r0, q0105; CHECK-NEXT: vldrb.u16 q0, [r1, #8]106; CHECK-NEXT: vaddva.u16 r0, q0107; CHECK-NEXT: vldrb.u16 q0, [r2, #8]108; CHECK-NEXT: vaddva.u16 r0, q0109; CHECK-NEXT: vaddva.u8 r0, q2110; CHECK-NEXT: add sp, #32111; CHECK-NEXT: bx lr112 %ae = zext <32 x i8> %a to <32 x i16>113 %be = zext <16 x i8> %b to <16 x i16>114 %r1 = call i16 @llvm.vector.reduce.add.i16.v32i16(<32 x i16> %ae)115 %r2 = call i16 @llvm.vector.reduce.add.i16.v16i16(<16 x i16> %be)116 %r = add i16 %r1, %r2117 ret i16 %r118}119 120define i32 @mul_i32(<8 x i32> %a, <4 x i32> %b) {121; CHECK-LABEL: mul_i32:122; CHECK: @ %bb.0:123; CHECK-NEXT: vmul.i32 q0, q0, q1124; CHECK-NEXT: vmul.i32 q0, q0, q2125; CHECK-NEXT: vmov r0, r1, d1126; CHECK-NEXT: vmov r2, r3, d0127; CHECK-NEXT: muls r0, r1, r0128; CHECK-NEXT: mul r1, r2, r3129; CHECK-NEXT: muls r0, r1, r0130; CHECK-NEXT: bx lr131 %r1 = call i32 @llvm.vector.reduce.mul.i32.v8i32(<8 x i32> %a)132 %r2 = call i32 @llvm.vector.reduce.mul.i32.v4i32(<4 x i32> %b)133 %r = mul i32 %r1, %r2134 ret i32 %r135}136 137define i32 @and_i32(<8 x i32> %a, <4 x i32> %b) {138; CHECK-LABEL: and_i32:139; CHECK: @ %bb.0:140; CHECK-NEXT: vand q0, q0, q1141; CHECK-NEXT: vand q0, q0, q2142; CHECK-NEXT: vmov r0, r1, d1143; CHECK-NEXT: vmov r2, r3, d0144; CHECK-NEXT: ands r0, r1145; CHECK-NEXT: and.w r1, r2, r3146; CHECK-NEXT: ands r0, r1147; CHECK-NEXT: bx lr148 %r1 = call i32 @llvm.vector.reduce.and.i32.v8i32(<8 x i32> %a)149 %r2 = call i32 @llvm.vector.reduce.and.i32.v4i32(<4 x i32> %b)150 %r = and i32 %r1, %r2151 ret i32 %r152}153 154define i32 @or_i32(<8 x i32> %a, <4 x i32> %b) {155; CHECK-LABEL: or_i32:156; CHECK: @ %bb.0:157; CHECK-NEXT: vorr q0, q0, q1158; CHECK-NEXT: vorr q0, q0, q2159; CHECK-NEXT: vmov r0, r1, d1160; CHECK-NEXT: vmov r2, r3, d0161; CHECK-NEXT: orrs r0, r1162; CHECK-NEXT: orr.w r1, r2, r3163; CHECK-NEXT: orrs r0, r1164; CHECK-NEXT: bx lr165 %r1 = call i32 @llvm.vector.reduce.or.i32.v8i32(<8 x i32> %a)166 %r2 = call i32 @llvm.vector.reduce.or.i32.v4i32(<4 x i32> %b)167 %r = or i32 %r1, %r2168 ret i32 %r169}170 171define i32 @xor_i32(<8 x i32> %a, <4 x i32> %b) {172; CHECK-LABEL: xor_i32:173; CHECK: @ %bb.0:174; CHECK-NEXT: veor q0, q0, q1175; CHECK-NEXT: veor q0, q0, q2176; CHECK-NEXT: vmov r0, r1, d1177; CHECK-NEXT: vmov r2, r3, d0178; CHECK-NEXT: eors r0, r1179; CHECK-NEXT: eor.w r1, r2, r3180; CHECK-NEXT: eors r0, r1181; CHECK-NEXT: bx lr182 %r1 = call i32 @llvm.vector.reduce.xor.i32.v8i32(<8 x i32> %a)183 %r2 = call i32 @llvm.vector.reduce.xor.i32.v4i32(<4 x i32> %b)184 %r = xor i32 %r1, %r2185 ret i32 %r186}187 188define i32 @umin_i32(<8 x i32> %a, <4 x i32> %b) {189; CHECK-LABEL: umin_i32:190; CHECK: @ %bb.0:191; CHECK-NEXT: vmin.u32 q0, q0, q1192; CHECK-NEXT: mov.w r0, #-1193; CHECK-NEXT: vmin.u32 q0, q0, q2194; CHECK-NEXT: vminv.u32 r0, q0195; CHECK-NEXT: bx lr196 %r1 = call i32 @llvm.vector.reduce.umin.i32.v8i32(<8 x i32> %a)197 %r2 = call i32 @llvm.vector.reduce.umin.i32.v4i32(<4 x i32> %b)198 %r = call i32 @llvm.umin.i32(i32 %r1, i32 %r2)199 ret i32 %r200}201 202define i32 @umax_i32(<8 x i32> %a, <4 x i32> %b) {203; CHECK-LABEL: umax_i32:204; CHECK: @ %bb.0:205; CHECK-NEXT: vmax.u32 q0, q0, q1206; CHECK-NEXT: movs r0, #0207; CHECK-NEXT: vmax.u32 q0, q0, q2208; CHECK-NEXT: vmaxv.u32 r0, q0209; CHECK-NEXT: bx lr210 %r1 = call i32 @llvm.vector.reduce.umax.i32.v8i32(<8 x i32> %a)211 %r2 = call i32 @llvm.vector.reduce.umax.i32.v4i32(<4 x i32> %b)212 %r = call i32 @llvm.umax.i32(i32 %r1, i32 %r2)213 ret i32 %r214}215 216define i32 @smin_i32(<8 x i32> %a, <4 x i32> %b) {217; CHECK-LABEL: smin_i32:218; CHECK: @ %bb.0:219; CHECK-NEXT: vmin.s32 q0, q0, q1220; CHECK-NEXT: mvn r0, #-2147483648221; CHECK-NEXT: vmin.s32 q0, q0, q2222; CHECK-NEXT: vminv.s32 r0, q0223; CHECK-NEXT: bx lr224 %r1 = call i32 @llvm.vector.reduce.smin.i32.v8i32(<8 x i32> %a)225 %r2 = call i32 @llvm.vector.reduce.smin.i32.v4i32(<4 x i32> %b)226 %r = call i32 @llvm.smin.i32(i32 %r1, i32 %r2)227 ret i32 %r228}229 230define i32 @smax_i32(<8 x i32> %a, <4 x i32> %b) {231; CHECK-LABEL: smax_i32:232; CHECK: @ %bb.0:233; CHECK-NEXT: vmax.s32 q0, q0, q1234; CHECK-NEXT: mov.w r0, #-2147483648235; CHECK-NEXT: vmax.s32 q0, q0, q2236; CHECK-NEXT: vmaxv.s32 r0, q0237; CHECK-NEXT: bx lr238 %r1 = call i32 @llvm.vector.reduce.smax.i32.v8i32(<8 x i32> %a)239 %r2 = call i32 @llvm.vector.reduce.smax.i32.v4i32(<4 x i32> %b)240 %r = call i32 @llvm.smax.i32(i32 %r1, i32 %r2)241 ret i32 %r242}243 244define float @nested_add_f32(<4 x float> %a, <4 x float> %b, float %c, float %d) {245; CHECK-LABEL: nested_add_f32:246; CHECK: @ %bb.0:247; CHECK-NEXT: vadd.f32 q0, q0, q1248; CHECK-NEXT: vadd.f32 s4, s8, s9249; CHECK-NEXT: vadd.f32 s2, s2, s3250; CHECK-NEXT: vadd.f32 s0, s0, s1251; CHECK-NEXT: vadd.f32 s0, s0, s2252; CHECK-NEXT: vadd.f32 s0, s0, s4253; CHECK-NEXT: bx lr254 %r1 = call fast float @llvm.vector.reduce.fadd.f32.v4f32(float -0.0, <4 x float> %a)255 %a1 = fadd fast float %r1, %c256 %r2 = call fast float @llvm.vector.reduce.fadd.f32.v4f32(float -0.0, <4 x float> %b)257 %a2 = fadd fast float %r2, %d258 %r = fadd fast float %a1, %a2259 ret float %r260}261 262define float @nested_mul_f32(<4 x float> %a, <4 x float> %b, float %c, float %d) {263; CHECK-LABEL: nested_mul_f32:264; CHECK: @ %bb.0:265; CHECK-NEXT: vmul.f32 q0, q0, q1266; CHECK-NEXT: vmul.f32 s4, s8, s9267; CHECK-NEXT: vmul.f32 s2, s2, s3268; CHECK-NEXT: vmul.f32 s0, s0, s1269; CHECK-NEXT: vmul.f32 s0, s0, s2270; CHECK-NEXT: vmul.f32 s0, s0, s4271; CHECK-NEXT: bx lr272 %r1 = call fast float @llvm.vector.reduce.fmul.f32.v4f32(float 1.0, <4 x float> %a)273 %a1 = fmul fast float %r1, %c274 %r2 = call fast float @llvm.vector.reduce.fmul.f32.v4f32(float 1.0, <4 x float> %b)275 %a2 = fmul fast float %r2, %d276 %r = fmul fast float %a1, %a2277 ret float %r278}279 280define i32 @nested_add_i32(<4 x i32> %a, <4 x i32> %b, i32 %c, i32 %d) {281; CHECK-LABEL: nested_add_i32:282; CHECK: @ %bb.0:283; CHECK-NEXT: add r0, r1284; CHECK-NEXT: vaddva.u32 r0, q0285; CHECK-NEXT: vaddva.u32 r0, q1286; CHECK-NEXT: bx lr287 %r1 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %a)288 %a1 = add i32 %r1, %c289 %r2 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %b)290 %a2 = add i32 %r2, %d291 %r = add i32 %a1, %a2292 ret i32 %r293}294 295define i32 @nested_mul_i32(<4 x i32> %a, <4 x i32> %b, i32 %c, i32 %d) {296; CHECK-LABEL: nested_mul_i32:297; CHECK: @ %bb.0:298; CHECK-NEXT: .save {r7, lr}299; CHECK-NEXT: push {r7, lr}300; CHECK-NEXT: vmul.i32 q0, q0, q1301; CHECK-NEXT: muls r0, r1, r0302; CHECK-NEXT: vmov r12, lr, d1303; CHECK-NEXT: vmov r2, r3, d0304; CHECK-NEXT: mul r12, r12, lr305; CHECK-NEXT: muls r2, r3, r2306; CHECK-NEXT: mul r1, r2, r12307; CHECK-NEXT: muls r0, r1, r0308; CHECK-NEXT: pop {r7, pc}309 %r1 = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> %a)310 %a1 = mul i32 %r1, %c311 %r2 = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> %b)312 %a2 = mul i32 %r2, %d313 %r = mul i32 %a1, %a2314 ret i32 %r315}316 317define i32 @nested_and_i32(<4 x i32> %a, <4 x i32> %b, i32 %c, i32 %d) {318; CHECK-LABEL: nested_and_i32:319; CHECK: @ %bb.0:320; CHECK-NEXT: .save {r7, lr}321; CHECK-NEXT: push {r7, lr}322; CHECK-NEXT: vand q0, q0, q1323; CHECK-NEXT: ands r0, r1324; CHECK-NEXT: vmov r12, lr, d1325; CHECK-NEXT: vmov r2, r3, d0326; CHECK-NEXT: and.w r12, r12, lr327; CHECK-NEXT: ands r2, r3328; CHECK-NEXT: and.w r2, r2, r12329; CHECK-NEXT: ands r0, r2330; CHECK-NEXT: pop {r7, pc}331 %r1 = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %a)332 %a1 = and i32 %r1, %c333 %r2 = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %b)334 %a2 = and i32 %r2, %d335 %r = and i32 %a1, %a2336 ret i32 %r337}338 339define i32 @nested_or_i32(<4 x i32> %a, <4 x i32> %b, i32 %c, i32 %d) {340; CHECK-LABEL: nested_or_i32:341; CHECK: @ %bb.0:342; CHECK-NEXT: .save {r7, lr}343; CHECK-NEXT: push {r7, lr}344; CHECK-NEXT: vorr q0, q0, q1345; CHECK-NEXT: orrs r0, r1346; CHECK-NEXT: vmov r12, lr, d1347; CHECK-NEXT: vmov r2, r3, d0348; CHECK-NEXT: orr.w r12, r12, lr349; CHECK-NEXT: orrs r2, r3350; CHECK-NEXT: orr.w r2, r2, r12351; CHECK-NEXT: orrs r0, r2352; CHECK-NEXT: pop {r7, pc}353 %r1 = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %a)354 %a1 = or i32 %r1, %c355 %r2 = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %b)356 %a2 = or i32 %r2, %d357 %r = or i32 %a1, %a2358 ret i32 %r359}360 361define i32 @nested_xor_i32(<4 x i32> %a, <4 x i32> %b, i32 %c, i32 %d) {362; CHECK-LABEL: nested_xor_i32:363; CHECK: @ %bb.0:364; CHECK-NEXT: .save {r7, lr}365; CHECK-NEXT: push {r7, lr}366; CHECK-NEXT: veor q0, q0, q1367; CHECK-NEXT: eors r0, r1368; CHECK-NEXT: vmov r12, lr, d1369; CHECK-NEXT: vmov r2, r3, d0370; CHECK-NEXT: eor.w r12, r12, lr371; CHECK-NEXT: eors r2, r3372; CHECK-NEXT: eor.w r2, r2, r12373; CHECK-NEXT: eors r0, r2374; CHECK-NEXT: pop {r7, pc}375 %r1 = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %a)376 %a1 = xor i32 %r1, %c377 %r2 = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %b)378 %a2 = xor i32 %r2, %d379 %r = xor i32 %a1, %a2380 ret i32 %r381}382 383define i32 @nested_smin_i32(<4 x i32> %a, <4 x i32> %b, i32 %c, i32 %d) {384; CHECK-LABEL: nested_smin_i32:385; CHECK: @ %bb.0:386; CHECK-NEXT: cmp r0, r1387; CHECK-NEXT: mvn r2, #-2147483648388; CHECK-NEXT: vmin.s32 q0, q0, q1389; CHECK-NEXT: csel r0, r0, r1, lt390; CHECK-NEXT: vminv.s32 r2, q0391; CHECK-NEXT: cmp r2, r0392; CHECK-NEXT: csel r0, r2, r0, lt393; CHECK-NEXT: bx lr394 %r1 = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %a)395 %a1 = call i32 @llvm.smin.i32(i32 %r1, i32 %c)396 %r2 = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %b)397 %a2 = call i32 @llvm.smin.i32(i32 %r2, i32 %d)398 %r = call i32 @llvm.smin.i32(i32 %a1, i32 %a2)399 ret i32 %r400}401 402define i32 @nested_smax_i32(<4 x i32> %a, <4 x i32> %b, i32 %c, i32 %d) {403; CHECK-LABEL: nested_smax_i32:404; CHECK: @ %bb.0:405; CHECK-NEXT: cmp r0, r1406; CHECK-NEXT: mov.w r2, #-2147483648407; CHECK-NEXT: vmax.s32 q0, q0, q1408; CHECK-NEXT: csel r0, r0, r1, gt409; CHECK-NEXT: vmaxv.s32 r2, q0410; CHECK-NEXT: cmp r2, r0411; CHECK-NEXT: csel r0, r2, r0, gt412; CHECK-NEXT: bx lr413 %r1 = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %a)414 %a1 = call i32 @llvm.smax.i32(i32 %r1, i32 %c)415 %r2 = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %b)416 %a2 = call i32 @llvm.smax.i32(i32 %r2, i32 %d)417 %r = call i32 @llvm.smax.i32(i32 %a1, i32 %a2)418 ret i32 %r419}420 421define i32 @nested_umin_i32(<4 x i32> %a, <4 x i32> %b, i32 %c, i32 %d) {422; CHECK-LABEL: nested_umin_i32:423; CHECK: @ %bb.0:424; CHECK-NEXT: cmp r0, r1425; CHECK-NEXT: mov.w r2, #-1426; CHECK-NEXT: vmin.u32 q0, q0, q1427; CHECK-NEXT: csel r0, r0, r1, lo428; CHECK-NEXT: vminv.u32 r2, q0429; CHECK-NEXT: cmp r2, r0430; CHECK-NEXT: csel r0, r2, r0, lo431; CHECK-NEXT: bx lr432 %r1 = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %a)433 %a1 = call i32 @llvm.umin.i32(i32 %r1, i32 %c)434 %r2 = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %b)435 %a2 = call i32 @llvm.umin.i32(i32 %r2, i32 %d)436 %r = call i32 @llvm.umin.i32(i32 %a1, i32 %a2)437 ret i32 %r438}439 440define i32 @nested_umax_i32(<4 x i32> %a, <4 x i32> %b, i32 %c, i32 %d) {441; CHECK-LABEL: nested_umax_i32:442; CHECK: @ %bb.0:443; CHECK-NEXT: cmp r0, r1444; CHECK-NEXT: mov.w r2, #0445; CHECK-NEXT: vmax.u32 q0, q0, q1446; CHECK-NEXT: csel r0, r0, r1, hi447; CHECK-NEXT: vmaxv.u32 r2, q0448; CHECK-NEXT: cmp r2, r0449; CHECK-NEXT: csel r0, r2, r0, hi450; CHECK-NEXT: bx lr451 %r1 = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %a)452 %a1 = call i32 @llvm.umax.i32(i32 %r1, i32 %c)453 %r2 = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %b)454 %a2 = call i32 @llvm.umax.i32(i32 %r2, i32 %d)455 %r = call i32 @llvm.umax.i32(i32 %a1, i32 %a2)456 ret i32 %r457}458 459define float @nested_fmin_float(<4 x float> %a, <4 x float> %b, float %c, float %d) {460; CHECK-LABEL: nested_fmin_float:461; CHECK: @ %bb.0:462; CHECK-NEXT: vminnm.f32 q0, q0, q1463; CHECK-NEXT: vminnm.f32 s2, s2, s3464; CHECK-NEXT: vminnm.f32 s0, s0, s1465; CHECK-NEXT: vminnm.f32 s0, s0, s2466; CHECK-NEXT: vminnm.f32 s2, s8, s9467; CHECK-NEXT: vminnm.f32 s0, s0, s2468; CHECK-NEXT: bx lr469 %r1 = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> %a)470 %a1 = call float @llvm.minnum.f32(float %r1, float %c)471 %r2 = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> %b)472 %a2 = call float @llvm.minnum.f32(float %r2, float %d)473 %r = call float @llvm.minnum.f32(float %a1, float %a2)474 ret float %r475}476 477define float @nested_fmax_float(<4 x float> %a, <4 x float> %b, float %c, float %d) {478; CHECK-LABEL: nested_fmax_float:479; CHECK: @ %bb.0:480; CHECK-NEXT: vmaxnm.f32 q0, q0, q1481; CHECK-NEXT: vmaxnm.f32 s2, s2, s3482; CHECK-NEXT: vmaxnm.f32 s0, s0, s1483; CHECK-NEXT: vmaxnm.f32 s0, s0, s2484; CHECK-NEXT: vmaxnm.f32 s2, s8, s9485; CHECK-NEXT: vmaxnm.f32 s0, s0, s2486; CHECK-NEXT: bx lr487 %r1 = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> %a)488 %a1 = call float @llvm.maxnum.f32(float %r1, float %c)489 %r2 = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> %b)490 %a2 = call float @llvm.maxnum.f32(float %r2, float %d)491 %r = call float @llvm.maxnum.f32(float %a1, float %a2)492 ret float %r493}494 495declare float @llvm.vector.reduce.fadd.f32.v8f32(float, <8 x float>)496declare float @llvm.vector.reduce.fadd.f32.v4f32(float, <4 x float>)497declare float @llvm.vector.reduce.fmul.f32.v8f32(float, <8 x float>)498declare float @llvm.vector.reduce.fmul.f32.v4f32(float, <4 x float>)499declare float @llvm.vector.reduce.fmin.v8f32(<8 x float>)500declare float @llvm.vector.reduce.fmin.v4f32(<4 x float>)501declare float @llvm.vector.reduce.fmax.v8f32(<8 x float>)502declare float @llvm.vector.reduce.fmax.v4f32(<4 x float>)503declare i32 @llvm.vector.reduce.add.i32.v8i32(<8 x i32>)504declare i32 @llvm.vector.reduce.add.i32.v4i32(<4 x i32>)505declare i16 @llvm.vector.reduce.add.i16.v32i16(<32 x i16>)506declare i16 @llvm.vector.reduce.add.i16.v16i16(<16 x i16>)507declare i32 @llvm.vector.reduce.mul.i32.v8i32(<8 x i32>)508declare i32 @llvm.vector.reduce.mul.i32.v4i32(<4 x i32>)509declare i32 @llvm.vector.reduce.and.i32.v8i32(<8 x i32>)510declare i32 @llvm.vector.reduce.and.i32.v4i32(<4 x i32>)511declare i32 @llvm.vector.reduce.or.i32.v8i32(<8 x i32>)512declare i32 @llvm.vector.reduce.or.i32.v4i32(<4 x i32>)513declare i32 @llvm.vector.reduce.xor.i32.v8i32(<8 x i32>)514declare i32 @llvm.vector.reduce.xor.i32.v4i32(<4 x i32>)515declare i32 @llvm.vector.reduce.umin.i32.v8i32(<8 x i32>)516declare i32 @llvm.vector.reduce.umin.i32.v4i32(<4 x i32>)517declare i32 @llvm.vector.reduce.umax.i32.v8i32(<8 x i32>)518declare i32 @llvm.vector.reduce.umax.i32.v4i32(<4 x i32>)519declare i32 @llvm.vector.reduce.smin.i32.v8i32(<8 x i32>)520declare i32 @llvm.vector.reduce.smin.i32.v4i32(<4 x i32>)521declare i32 @llvm.vector.reduce.smax.i32.v8i32(<8 x i32>)522declare i32 @llvm.vector.reduce.smax.i32.v4i32(<4 x i32>)523declare float @llvm.minnum.f32(float, float)524declare float @llvm.maxnum.f32(float, float)525declare i32 @llvm.umin.i32(i32, i32)526declare i32 @llvm.umax.i32(i32, i32)527declare i32 @llvm.smin.i32(i32, i32)528declare i32 @llvm.smax.i32(i32, i32)529