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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s3 4define half @extret1_f16_sf(<8 x half> %a, <8 x half> %b, ptr nocapture %p) {5; CHECK-LABEL: extret1_f16_sf:6; CHECK: @ %bb.0:7; CHECK-NEXT: vmov d0, r0, r18; CHECK-NEXT: mov r0, sp9; CHECK-NEXT: vldrw.u32 q1, [r0]10; CHECK-NEXT: ldr r0, [sp, #16]11; CHECK-NEXT: vadd.f16 q0, q0, q112; CHECK-NEXT: vmovx.f16 s0, s013; CHECK-NEXT: vstr.16 s0, [r0]14; CHECK-NEXT: vmov r0, s015; CHECK-NEXT: bx lr16 %c = fadd <8 x half> %a, %b17 %e = extractelement <8 x half> %c, i32 118 store half %e, ptr %p, align 219 ret half %e20}21 22define half @extret4_f16_sf(<8 x half> %a, <8 x half> %b, ptr nocapture %p) {23; CHECK-LABEL: extret4_f16_sf:24; CHECK: @ %bb.0:25; CHECK-NEXT: mov r0, sp26; CHECK-NEXT: vmov d1, r2, r327; CHECK-NEXT: vldrw.u32 q1, [r0]28; CHECK-NEXT: ldr r0, [sp, #16]29; CHECK-NEXT: vadd.f16 q0, q0, q130; CHECK-NEXT: vstr.16 s2, [r0]31; CHECK-NEXT: vmov r0, s232; CHECK-NEXT: bx lr33 %c = fadd <8 x half> %a, %b34 %e = extractelement <8 x half> %c, i32 435 store half %e, ptr %p, align 236 ret half %e37}38 39define arm_aapcs_vfpcc half @extret1_f16_hf(<8 x half> %a, <8 x half> %b, ptr nocapture %p) {40; CHECK-LABEL: extret1_f16_hf:41; CHECK: @ %bb.0:42; CHECK-NEXT: vadd.f16 q0, q0, q143; CHECK-NEXT: vmovx.f16 s0, s044; CHECK-NEXT: vstr.16 s0, [r0]45; CHECK-NEXT: bx lr46 %c = fadd <8 x half> %a, %b47 %e = extractelement <8 x half> %c, i32 148 store half %e, ptr %p, align 249 ret half %e50}51 52define arm_aapcs_vfpcc half @extret4_f16_hf(<8 x half> %a, <8 x half> %b, ptr nocapture %p) {53; CHECK-LABEL: extret4_f16_hf:54; CHECK: @ %bb.0:55; CHECK-NEXT: vadd.f16 q0, q0, q156; CHECK-NEXT: vmov.f32 s0, s257; CHECK-NEXT: vstr.16 s2, [r0]58; CHECK-NEXT: bx lr59 %c = fadd <8 x half> %a, %b60 %e = extractelement <8 x half> %c, i32 461 store half %e, ptr %p, align 262 ret half %e63}64 65define arm_aapcs_vfpcc <8 x half> @extret1_v8f16_hf(<8 x half> %a, <8 x half> %b, ptr nocapture %p) {66; CHECK-LABEL: extret1_v8f16_hf:67; CHECK: @ %bb.0:68; CHECK-NEXT: vadd.f16 q0, q0, q169; CHECK-NEXT: vmov.u16 r1, q0[1]70; CHECK-NEXT: vdup.16 q0, r171; CHECK-NEXT: strh r1, [r0]72; CHECK-NEXT: bx lr73 %c = fadd <8 x half> %a, %b74 %e = extractelement <8 x half> %c, i32 175 store half %e, ptr %p, align 276 %i = insertelement <8 x half> undef, half %e, i32 077 %s = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer78 ret <8 x half> %s79}80 81define arm_aapcs_vfpcc <8 x half> @extret4_v8f16_hf(<8 x half> %a, <8 x half> %b, ptr nocapture %p) {82; CHECK-LABEL: extret4_v8f16_hf:83; CHECK: @ %bb.0:84; CHECK-NEXT: vadd.f16 q0, q0, q185; CHECK-NEXT: vmov.u16 r1, q0[4]86; CHECK-NEXT: vdup.16 q0, r187; CHECK-NEXT: strh r1, [r0]88; CHECK-NEXT: bx lr89 %c = fadd <8 x half> %a, %b90 %e = extractelement <8 x half> %c, i32 491 store half %e, ptr %p, align 292 %i = insertelement <8 x half> undef, half %e, i32 093 %s = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer94 ret <8 x half> %s95}96 97 98define float @extret1_f32_sf(<4 x float> %a, <4 x float> %b, ptr nocapture %p) {99; CHECK-LABEL: extret1_f32_sf:100; CHECK: @ %bb.0:101; CHECK-NEXT: vmov d0, r0, r1102; CHECK-NEXT: mov r0, sp103; CHECK-NEXT: vldrw.u32 q1, [r0]104; CHECK-NEXT: ldr r1, [sp, #16]105; CHECK-NEXT: vadd.f32 q0, q0, q1106; CHECK-NEXT: vmov r0, s1107; CHECK-NEXT: vstr s1, [r1]108; CHECK-NEXT: bx lr109 %c = fadd <4 x float> %a, %b110 %e = extractelement <4 x float> %c, i32 1111 store float %e, ptr %p, align 4112 ret float %e113}114 115define float @extret2_f32_sf(<4 x float> %a, <4 x float> %b, ptr nocapture %p) {116; CHECK-LABEL: extret2_f32_sf:117; CHECK: @ %bb.0:118; CHECK-NEXT: mov r0, sp119; CHECK-NEXT: vmov d1, r2, r3120; CHECK-NEXT: vldrw.u32 q1, [r0]121; CHECK-NEXT: ldr r1, [sp, #16]122; CHECK-NEXT: vadd.f32 q0, q0, q1123; CHECK-NEXT: vmov r0, s2124; CHECK-NEXT: vstr s2, [r1]125; CHECK-NEXT: bx lr126 %c = fadd <4 x float> %a, %b127 %e = extractelement <4 x float> %c, i32 2128 store float %e, ptr %p, align 4129 ret float %e130}131 132define arm_aapcs_vfpcc float @extret1_f32_hf(<4 x float> %a, <4 x float> %b, ptr nocapture %p) {133; CHECK-LABEL: extret1_f32_hf:134; CHECK: @ %bb.0:135; CHECK-NEXT: vadd.f32 q0, q0, q1136; CHECK-NEXT: vmov.f32 s0, s1137; CHECK-NEXT: vstr s1, [r0]138; CHECK-NEXT: bx lr139 %c = fadd <4 x float> %a, %b140 %e = extractelement <4 x float> %c, i32 1141 store float %e, ptr %p, align 4142 ret float %e143}144 145 146define arm_aapcs_vfpcc float @extret2_f32_hf(<4 x float> %a, <4 x float> %b, ptr nocapture %p) {147; CHECK-LABEL: extret2_f32_hf:148; CHECK: @ %bb.0:149; CHECK-NEXT: vadd.f32 q0, q0, q1150; CHECK-NEXT: vmov.f32 s0, s2151; CHECK-NEXT: vstr s2, [r0]152; CHECK-NEXT: bx lr153 %c = fadd <4 x float> %a, %b154 %e = extractelement <4 x float> %c, i32 2155 store float %e, ptr %p, align 4156 ret float %e157}158 159define arm_aapcs_vfpcc <4 x float> @extret1_v4f32_hf(<4 x float> %a, <4 x float> %b, ptr nocapture %p) {160; CHECK-LABEL: extret1_v4f32_hf:161; CHECK: @ %bb.0:162; CHECK-NEXT: vadd.f32 q1, q0, q1163; CHECK-NEXT: vmov r1, s5164; CHECK-NEXT: vstr s5, [r0]165; CHECK-NEXT: vdup.32 q0, r1166; CHECK-NEXT: bx lr167 %c = fadd <4 x float> %a, %b168 %e = extractelement <4 x float> %c, i32 1169 store float %e, ptr %p, align 4170 %i = insertelement <4 x float> undef, float %e, i32 0171 %s = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer172 ret <4 x float> %s173}174 175define arm_aapcs_vfpcc <4 x float> @extret2_v4f32_hf(<4 x float> %a, <4 x float> %b, ptr nocapture %p) {176; CHECK-LABEL: extret2_v4f32_hf:177; CHECK: @ %bb.0:178; CHECK-NEXT: vadd.f32 q1, q0, q1179; CHECK-NEXT: vmov r1, s6180; CHECK-NEXT: vstr s6, [r0]181; CHECK-NEXT: vdup.32 q0, r1182; CHECK-NEXT: bx lr183 %c = fadd <4 x float> %a, %b184 %e = extractelement <4 x float> %c, i32 2185 store float %e, ptr %p, align 4186 %i = insertelement <4 x float> undef, float %e, i32 0187 %s = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer188 ret <4 x float> %s189}190