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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi, -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVE-FP3; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi, -mattr=+mve.fp -fp-contract=fast -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVE-VMLA4; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVE5 6define arm_aapcs_vfpcc <8 x half> @vfma16_v1(<8 x half> %src1, <8 x half> %src2, <8 x half> %src3) {7; CHECK-MVE-FP-LABEL: vfma16_v1:8; CHECK-MVE-FP: @ %bb.0: @ %entry9; CHECK-MVE-FP-NEXT: vmul.f16 q1, q1, q210; CHECK-MVE-FP-NEXT: vadd.f16 q0, q0, q111; CHECK-MVE-FP-NEXT: bx lr12;13; CHECK-MVE-VMLA-LABEL: vfma16_v1:14; CHECK-MVE-VMLA: @ %bb.0: @ %entry15; CHECK-MVE-VMLA-NEXT: vfma.f16 q0, q1, q216; CHECK-MVE-VMLA-NEXT: bx lr17;18; CHECK-MVE-LABEL: vfma16_v1:19; CHECK-MVE: @ %bb.0: @ %entry20; CHECK-MVE-NEXT: vmovx.f16 s13, s021; CHECK-MVE-NEXT: vmovx.f16 s12, s822; CHECK-MVE-NEXT: vmovx.f16 s14, s423; CHECK-MVE-NEXT: vmla.f16 s0, s4, s824; CHECK-MVE-NEXT: vmla.f16 s13, s14, s1225; CHECK-MVE-NEXT: vmovx.f16 s12, s126; CHECK-MVE-NEXT: vmovx.f16 s4, s927; CHECK-MVE-NEXT: vmovx.f16 s8, s528; CHECK-MVE-NEXT: vmla.f16 s12, s8, s429; CHECK-MVE-NEXT: vmla.f16 s1, s5, s930; CHECK-MVE-NEXT: vins.f16 s1, s1231; CHECK-MVE-NEXT: vmovx.f16 s12, s232; CHECK-MVE-NEXT: vmovx.f16 s4, s1033; CHECK-MVE-NEXT: vmovx.f16 s8, s634; CHECK-MVE-NEXT: vmla.f16 s12, s8, s435; CHECK-MVE-NEXT: vmla.f16 s2, s6, s1036; CHECK-MVE-NEXT: vmovx.f16 s8, s337; CHECK-MVE-NEXT: vmovx.f16 s4, s1138; CHECK-MVE-NEXT: vmovx.f16 s6, s739; CHECK-MVE-NEXT: vmla.f16 s3, s7, s1140; CHECK-MVE-NEXT: vmla.f16 s8, s6, s441; CHECK-MVE-NEXT: vins.f16 s0, s1342; CHECK-MVE-NEXT: vins.f16 s2, s1243; CHECK-MVE-NEXT: vins.f16 s3, s844; CHECK-MVE-NEXT: bx lr45entry:46 %0 = fmul <8 x half> %src2, %src347 %1 = fadd <8 x half> %src1, %048 ret <8 x half> %149}50 51define arm_aapcs_vfpcc <8 x half> @vfma16_v2(<8 x half> %src1, <8 x half> %src2, <8 x half> %src3) {52; CHECK-MVE-FP-LABEL: vfma16_v2:53; CHECK-MVE-FP: @ %bb.0: @ %entry54; CHECK-MVE-FP-NEXT: vmul.f16 q1, q1, q255; CHECK-MVE-FP-NEXT: vadd.f16 q0, q1, q056; CHECK-MVE-FP-NEXT: bx lr57;58; CHECK-MVE-VMLA-LABEL: vfma16_v2:59; CHECK-MVE-VMLA: @ %bb.0: @ %entry60; CHECK-MVE-VMLA-NEXT: vfma.f16 q0, q1, q261; CHECK-MVE-VMLA-NEXT: bx lr62;63; CHECK-MVE-LABEL: vfma16_v2:64; CHECK-MVE: @ %bb.0: @ %entry65; CHECK-MVE-NEXT: vmovx.f16 s13, s066; CHECK-MVE-NEXT: vmovx.f16 s12, s867; CHECK-MVE-NEXT: vmovx.f16 s14, s468; CHECK-MVE-NEXT: vmla.f16 s0, s4, s869; CHECK-MVE-NEXT: vmla.f16 s13, s14, s1270; CHECK-MVE-NEXT: vmovx.f16 s12, s171; CHECK-MVE-NEXT: vmovx.f16 s4, s972; CHECK-MVE-NEXT: vmovx.f16 s8, s573; CHECK-MVE-NEXT: vmla.f16 s12, s8, s474; CHECK-MVE-NEXT: vmla.f16 s1, s5, s975; CHECK-MVE-NEXT: vins.f16 s1, s1276; CHECK-MVE-NEXT: vmovx.f16 s12, s277; CHECK-MVE-NEXT: vmovx.f16 s4, s1078; CHECK-MVE-NEXT: vmovx.f16 s8, s679; CHECK-MVE-NEXT: vmla.f16 s12, s8, s480; CHECK-MVE-NEXT: vmla.f16 s2, s6, s1081; CHECK-MVE-NEXT: vmovx.f16 s8, s382; CHECK-MVE-NEXT: vmovx.f16 s4, s1183; CHECK-MVE-NEXT: vmovx.f16 s6, s784; CHECK-MVE-NEXT: vmla.f16 s3, s7, s1185; CHECK-MVE-NEXT: vmla.f16 s8, s6, s486; CHECK-MVE-NEXT: vins.f16 s0, s1387; CHECK-MVE-NEXT: vins.f16 s2, s1288; CHECK-MVE-NEXT: vins.f16 s3, s889; CHECK-MVE-NEXT: bx lr90entry:91 %0 = fmul <8 x half> %src2, %src392 %1 = fadd <8 x half> %0, %src193 ret <8 x half> %194}95 96define arm_aapcs_vfpcc <8 x half> @vfms16(<8 x half> %src1, <8 x half> %src2, <8 x half> %src3) {97; CHECK-MVE-FP-LABEL: vfms16:98; CHECK-MVE-FP: @ %bb.0: @ %entry99; CHECK-MVE-FP-NEXT: vmul.f16 q1, q1, q2100; CHECK-MVE-FP-NEXT: vsub.f16 q0, q0, q1101; CHECK-MVE-FP-NEXT: bx lr102;103; CHECK-MVE-VMLA-LABEL: vfms16:104; CHECK-MVE-VMLA: @ %bb.0: @ %entry105; CHECK-MVE-VMLA-NEXT: vfms.f16 q0, q1, q2106; CHECK-MVE-VMLA-NEXT: bx lr107;108; CHECK-MVE-LABEL: vfms16:109; CHECK-MVE: @ %bb.0: @ %entry110; CHECK-MVE-NEXT: vmovx.f16 s13, s0111; CHECK-MVE-NEXT: vmovx.f16 s12, s8112; CHECK-MVE-NEXT: vmovx.f16 s14, s4113; CHECK-MVE-NEXT: vmls.f16 s0, s4, s8114; CHECK-MVE-NEXT: vmls.f16 s13, s14, s12115; CHECK-MVE-NEXT: vmovx.f16 s12, s1116; CHECK-MVE-NEXT: vmovx.f16 s4, s9117; CHECK-MVE-NEXT: vmovx.f16 s8, s5118; CHECK-MVE-NEXT: vmls.f16 s12, s8, s4119; CHECK-MVE-NEXT: vmls.f16 s1, s5, s9120; CHECK-MVE-NEXT: vins.f16 s1, s12121; CHECK-MVE-NEXT: vmovx.f16 s12, s2122; CHECK-MVE-NEXT: vmovx.f16 s4, s10123; CHECK-MVE-NEXT: vmovx.f16 s8, s6124; CHECK-MVE-NEXT: vmls.f16 s12, s8, s4125; CHECK-MVE-NEXT: vmls.f16 s2, s6, s10126; CHECK-MVE-NEXT: vmovx.f16 s8, s3127; CHECK-MVE-NEXT: vmovx.f16 s4, s11128; CHECK-MVE-NEXT: vmovx.f16 s6, s7129; CHECK-MVE-NEXT: vmls.f16 s3, s7, s11130; CHECK-MVE-NEXT: vmls.f16 s8, s6, s4131; CHECK-MVE-NEXT: vins.f16 s0, s13132; CHECK-MVE-NEXT: vins.f16 s2, s12133; CHECK-MVE-NEXT: vins.f16 s3, s8134; CHECK-MVE-NEXT: bx lr135entry:136 %0 = fmul <8 x half> %src2, %src3137 %1 = fsub <8 x half> %src1, %0138 ret <8 x half> %1139}140 141define arm_aapcs_vfpcc <8 x half> @vfmar16(<8 x half> %src1, <8 x half> %src2, float %src3o) {142; CHECK-MVE-FP-LABEL: vfmar16:143; CHECK-MVE-FP: @ %bb.0: @ %entry144; CHECK-MVE-FP-NEXT: vcvtb.f16.f32 s8, s8145; CHECK-MVE-FP-NEXT: vmov.f16 r0, s8146; CHECK-MVE-FP-NEXT: vmul.f16 q1, q1, r0147; CHECK-MVE-FP-NEXT: vadd.f16 q0, q0, q1148; CHECK-MVE-FP-NEXT: bx lr149;150; CHECK-MVE-VMLA-LABEL: vfmar16:151; CHECK-MVE-VMLA: @ %bb.0: @ %entry152; CHECK-MVE-VMLA-NEXT: vcvtb.f16.f32 s8, s8153; CHECK-MVE-VMLA-NEXT: vmov.f16 r0, s8154; CHECK-MVE-VMLA-NEXT: vfma.f16 q0, q1, r0155; CHECK-MVE-VMLA-NEXT: bx lr156;157; CHECK-MVE-LABEL: vfmar16:158; CHECK-MVE: @ %bb.0: @ %entry159; CHECK-MVE-NEXT: vcvtb.f16.f32 s8, s8160; CHECK-MVE-NEXT: vmovx.f16 s12, s0161; CHECK-MVE-NEXT: vmovx.f16 s10, s4162; CHECK-MVE-NEXT: vmla.f16 s0, s4, s8163; CHECK-MVE-NEXT: vmla.f16 s12, s10, s8164; CHECK-MVE-NEXT: vmovx.f16 s10, s1165; CHECK-MVE-NEXT: vmovx.f16 s4, s5166; CHECK-MVE-NEXT: vmla.f16 s1, s5, s8167; CHECK-MVE-NEXT: vmla.f16 s10, s4, s8168; CHECK-MVE-NEXT: vmovx.f16 s4, s6169; CHECK-MVE-NEXT: vins.f16 s1, s10170; CHECK-MVE-NEXT: vmovx.f16 s10, s2171; CHECK-MVE-NEXT: vmla.f16 s10, s4, s8172; CHECK-MVE-NEXT: vmla.f16 s2, s6, s8173; CHECK-MVE-NEXT: vmovx.f16 s6, s3174; CHECK-MVE-NEXT: vmovx.f16 s4, s7175; CHECK-MVE-NEXT: vmla.f16 s6, s4, s8176; CHECK-MVE-NEXT: vmla.f16 s3, s7, s8177; CHECK-MVE-NEXT: vins.f16 s0, s12178; CHECK-MVE-NEXT: vins.f16 s2, s10179; CHECK-MVE-NEXT: vins.f16 s3, s6180; CHECK-MVE-NEXT: bx lr181entry:182 %src3 = fptrunc float %src3o to half183 %i = insertelement <8 x half> undef, half %src3, i32 0184 %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer185 %0 = fmul <8 x half> %src2, %sp186 %1 = fadd <8 x half> %src1, %0187 ret <8 x half> %1188}189 190define arm_aapcs_vfpcc <8 x half> @vfma16(<8 x half> %src1, <8 x half> %src2, float %src3o) {191; CHECK-MVE-FP-LABEL: vfma16:192; CHECK-MVE-FP: @ %bb.0: @ %entry193; CHECK-MVE-FP-NEXT: vcvtb.f16.f32 s8, s8194; CHECK-MVE-FP-NEXT: vmul.f16 q0, q0, q1195; CHECK-MVE-FP-NEXT: vmov.f16 r0, s8196; CHECK-MVE-FP-NEXT: vadd.f16 q0, q0, r0197; CHECK-MVE-FP-NEXT: bx lr198;199; CHECK-MVE-VMLA-LABEL: vfma16:200; CHECK-MVE-VMLA: @ %bb.0: @ %entry201; CHECK-MVE-VMLA-NEXT: vcvtb.f16.f32 s8, s8202; CHECK-MVE-VMLA-NEXT: vmov.f16 r0, s8203; CHECK-MVE-VMLA-NEXT: vfmas.f16 q0, q1, r0204; CHECK-MVE-VMLA-NEXT: bx lr205;206; CHECK-MVE-LABEL: vfma16:207; CHECK-MVE: @ %bb.0: @ %entry208; CHECK-MVE-NEXT: vmov q3, q0209; CHECK-MVE-NEXT: vcvtb.f16.f32 s3, s8210; CHECK-MVE-NEXT: vmovx.f16 s0, s4211; CHECK-MVE-NEXT: vmovx.f16 s2, s12212; CHECK-MVE-NEXT: vmov.f32 s8, s3213; CHECK-MVE-NEXT: vmla.f16 s8, s2, s0214; CHECK-MVE-NEXT: vmov.f32 s0, s3215; CHECK-MVE-NEXT: vmla.f16 s0, s12, s4216; CHECK-MVE-NEXT: vmov.f32 s1, s3217; CHECK-MVE-NEXT: vins.f16 s0, s8218; CHECK-MVE-NEXT: vmovx.f16 s2, s5219; CHECK-MVE-NEXT: vmovx.f16 s4, s13220; CHECK-MVE-NEXT: vmov.f32 s8, s3221; CHECK-MVE-NEXT: vmla.f16 s8, s4, s2222; CHECK-MVE-NEXT: vmla.f16 s1, s13, s5223; CHECK-MVE-NEXT: vins.f16 s1, s8224; CHECK-MVE-NEXT: vmovx.f16 s2, s6225; CHECK-MVE-NEXT: vmovx.f16 s4, s14226; CHECK-MVE-NEXT: vmov.f32 s8, s3227; CHECK-MVE-NEXT: vmla.f16 s8, s4, s2228; CHECK-MVE-NEXT: vmov.f32 s2, s3229; CHECK-MVE-NEXT: vmla.f16 s2, s14, s6230; CHECK-MVE-NEXT: vmovx.f16 s4, s7231; CHECK-MVE-NEXT: vins.f16 s2, s8232; CHECK-MVE-NEXT: vmov.f32 s8, s3233; CHECK-MVE-NEXT: vmovx.f16 s6, s15234; CHECK-MVE-NEXT: vmla.f16 s3, s15, s7235; CHECK-MVE-NEXT: vmla.f16 s8, s6, s4236; CHECK-MVE-NEXT: vins.f16 s3, s8237; CHECK-MVE-NEXT: bx lr238entry:239 %src3 = fptrunc float %src3o to half240 %i = insertelement <8 x half> undef, half %src3, i32 0241 %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer242 %0 = fmul <8 x half> %src1, %src2243 %1 = fadd <8 x half> %sp, %0244 ret <8 x half> %1245}246 247define arm_aapcs_vfpcc <4 x float> @vfma32_v1(<4 x float> %src1, <4 x float> %src2, <4 x float> %src3) {248; CHECK-MVE-FP-LABEL: vfma32_v1:249; CHECK-MVE-FP: @ %bb.0: @ %entry250; CHECK-MVE-FP-NEXT: vmul.f32 q1, q1, q2251; CHECK-MVE-FP-NEXT: vadd.f32 q0, q0, q1252; CHECK-MVE-FP-NEXT: bx lr253;254; CHECK-MVE-VMLA-LABEL: vfma32_v1:255; CHECK-MVE-VMLA: @ %bb.0: @ %entry256; CHECK-MVE-VMLA-NEXT: vfma.f32 q0, q1, q2257; CHECK-MVE-VMLA-NEXT: bx lr258;259; CHECK-MVE-LABEL: vfma32_v1:260; CHECK-MVE: @ %bb.0: @ %entry261; CHECK-MVE-NEXT: vmla.f32 s3, s7, s11262; CHECK-MVE-NEXT: vmla.f32 s2, s6, s10263; CHECK-MVE-NEXT: vmla.f32 s1, s5, s9264; CHECK-MVE-NEXT: vmla.f32 s0, s4, s8265; CHECK-MVE-NEXT: bx lr266entry:267 %0 = fmul <4 x float> %src2, %src3268 %1 = fadd <4 x float> %src1, %0269 ret <4 x float> %1270}271 272define arm_aapcs_vfpcc <4 x float> @vfma32_v2(<4 x float> %src1, <4 x float> %src2, <4 x float> %src3) {273; CHECK-MVE-FP-LABEL: vfma32_v2:274; CHECK-MVE-FP: @ %bb.0: @ %entry275; CHECK-MVE-FP-NEXT: vmul.f32 q1, q1, q2276; CHECK-MVE-FP-NEXT: vadd.f32 q0, q1, q0277; CHECK-MVE-FP-NEXT: bx lr278;279; CHECK-MVE-VMLA-LABEL: vfma32_v2:280; CHECK-MVE-VMLA: @ %bb.0: @ %entry281; CHECK-MVE-VMLA-NEXT: vfma.f32 q0, q1, q2282; CHECK-MVE-VMLA-NEXT: bx lr283;284; CHECK-MVE-LABEL: vfma32_v2:285; CHECK-MVE: @ %bb.0: @ %entry286; CHECK-MVE-NEXT: vmla.f32 s3, s7, s11287; CHECK-MVE-NEXT: vmla.f32 s2, s6, s10288; CHECK-MVE-NEXT: vmla.f32 s1, s5, s9289; CHECK-MVE-NEXT: vmla.f32 s0, s4, s8290; CHECK-MVE-NEXT: bx lr291entry:292 %0 = fmul <4 x float> %src2, %src3293 %1 = fadd <4 x float> %0, %src1294 ret <4 x float> %1295}296 297define arm_aapcs_vfpcc <4 x float> @vfms32(<4 x float> %src1, <4 x float> %src2, <4 x float> %src3) {298; CHECK-MVE-FP-LABEL: vfms32:299; CHECK-MVE-FP: @ %bb.0: @ %entry300; CHECK-MVE-FP-NEXT: vmul.f32 q1, q1, q2301; CHECK-MVE-FP-NEXT: vsub.f32 q0, q0, q1302; CHECK-MVE-FP-NEXT: bx lr303;304; CHECK-MVE-VMLA-LABEL: vfms32:305; CHECK-MVE-VMLA: @ %bb.0: @ %entry306; CHECK-MVE-VMLA-NEXT: vfms.f32 q0, q1, q2307; CHECK-MVE-VMLA-NEXT: bx lr308;309; CHECK-MVE-LABEL: vfms32:310; CHECK-MVE: @ %bb.0: @ %entry311; CHECK-MVE-NEXT: vmls.f32 s3, s7, s11312; CHECK-MVE-NEXT: vmls.f32 s2, s6, s10313; CHECK-MVE-NEXT: vmls.f32 s1, s5, s9314; CHECK-MVE-NEXT: vmls.f32 s0, s4, s8315; CHECK-MVE-NEXT: bx lr316entry:317 %0 = fmul <4 x float> %src2, %src3318 %1 = fsub <4 x float> %src1, %0319 ret <4 x float> %1320}321 322define arm_aapcs_vfpcc <4 x float> @vfmar32(<4 x float> %src1, <4 x float> %src2, float %src3) {323; CHECK-MVE-FP-LABEL: vfmar32:324; CHECK-MVE-FP: @ %bb.0: @ %entry325; CHECK-MVE-FP-NEXT: vmov r0, s8326; CHECK-MVE-FP-NEXT: vmul.f32 q1, q1, r0327; CHECK-MVE-FP-NEXT: vadd.f32 q0, q0, q1328; CHECK-MVE-FP-NEXT: bx lr329;330; CHECK-MVE-VMLA-LABEL: vfmar32:331; CHECK-MVE-VMLA: @ %bb.0: @ %entry332; CHECK-MVE-VMLA-NEXT: vmov r0, s8333; CHECK-MVE-VMLA-NEXT: vfma.f32 q0, q1, r0334; CHECK-MVE-VMLA-NEXT: bx lr335;336; CHECK-MVE-LABEL: vfmar32:337; CHECK-MVE: @ %bb.0: @ %entry338; CHECK-MVE-NEXT: vmla.f32 s3, s7, s8339; CHECK-MVE-NEXT: vmla.f32 s2, s6, s8340; CHECK-MVE-NEXT: vmla.f32 s1, s5, s8341; CHECK-MVE-NEXT: vmla.f32 s0, s4, s8342; CHECK-MVE-NEXT: bx lr343entry:344 %i = insertelement <4 x float> undef, float %src3, i32 0345 %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer346 %0 = fmul <4 x float> %src2, %sp347 %1 = fadd <4 x float> %src1, %0348 ret <4 x float> %1349}350 351define arm_aapcs_vfpcc <4 x float> @vfmas32(<4 x float> %src1, <4 x float> %src2, float %src3) {352; CHECK-MVE-FP-LABEL: vfmas32:353; CHECK-MVE-FP: @ %bb.0: @ %entry354; CHECK-MVE-FP-NEXT: vmov r0, s8355; CHECK-MVE-FP-NEXT: vmul.f32 q0, q0, q1356; CHECK-MVE-FP-NEXT: vadd.f32 q0, q0, r0357; CHECK-MVE-FP-NEXT: bx lr358;359; CHECK-MVE-VMLA-LABEL: vfmas32:360; CHECK-MVE-VMLA: @ %bb.0: @ %entry361; CHECK-MVE-VMLA-NEXT: vmov r0, s8362; CHECK-MVE-VMLA-NEXT: vfmas.f32 q0, q1, r0363; CHECK-MVE-VMLA-NEXT: bx lr364;365; CHECK-MVE-LABEL: vfmas32:366; CHECK-MVE: @ %bb.0: @ %entry367; CHECK-MVE-NEXT: vmov.f32 s11, s8368; CHECK-MVE-NEXT: vmov.f32 s10, s8369; CHECK-MVE-NEXT: vmov.f32 s9, s8370; CHECK-MVE-NEXT: vmla.f32 s8, s0, s4371; CHECK-MVE-NEXT: vmla.f32 s11, s3, s7372; CHECK-MVE-NEXT: vmla.f32 s10, s2, s6373; CHECK-MVE-NEXT: vmla.f32 s9, s1, s5374; CHECK-MVE-NEXT: vmov q0, q2375; CHECK-MVE-NEXT: bx lr376entry:377 %i = insertelement <4 x float> undef, float %src3, i32 0378 %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer379 %0 = fmul <4 x float> %src1, %src2380 %1 = fadd <4 x float> %sp, %0381 ret <4 x float> %1382}383 384 385; Predicated version of the same tests386 387define arm_aapcs_vfpcc <8 x half> @vfma16_v1_pred(<8 x half> %src1, <8 x half> %src2, <8 x half> %src3) {388; CHECK-MVE-FP-LABEL: vfma16_v1_pred:389; CHECK-MVE-FP: @ %bb.0: @ %entry390; CHECK-MVE-FP-NEXT: vmul.f16 q2, q1, q2391; CHECK-MVE-FP-NEXT: vpt.f16 lt, q1, zr392; CHECK-MVE-FP-NEXT: vaddt.f16 q0, q0, q2393; CHECK-MVE-FP-NEXT: bx lr394;395; CHECK-MVE-VMLA-LABEL: vfma16_v1_pred:396; CHECK-MVE-VMLA: @ %bb.0: @ %entry397; CHECK-MVE-VMLA-NEXT: vpt.f16 lt, q1, zr398; CHECK-MVE-VMLA-NEXT: vfmat.f16 q0, q1, q2399; CHECK-MVE-VMLA-NEXT: bx lr400;401; CHECK-MVE-LABEL: vfma16_v1_pred:402; CHECK-MVE: @ %bb.0: @ %entry403; CHECK-MVE-NEXT: vmovx.f16 s14, s4404; CHECK-MVE-NEXT: vmovx.f16 s13, s0405; CHECK-MVE-NEXT: vcmp.f16 s14, #0406; CHECK-MVE-NEXT: vmovx.f16 s12, s8407; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr408; CHECK-MVE-NEXT: vmov.f32 s15, s13409; CHECK-MVE-NEXT: vmla.f16 s15, s14, s12410; CHECK-MVE-NEXT: vcmp.f16 s4, #0411; CHECK-MVE-NEXT: vmov.f32 s14, s0412; CHECK-MVE-NEXT: vmla.f16 s14, s4, s8413; CHECK-MVE-NEXT: vmovx.f16 s8, s5414; CHECK-MVE-NEXT: vmovx.f16 s4, s9415; CHECK-MVE-NEXT: cset r0, mi416; CHECK-MVE-NEXT: cmp r0, #0417; CHECK-MVE-NEXT: vseleq.f16 s12, s13, s15418; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr419; CHECK-MVE-NEXT: vcmp.f16 s8, #0420; CHECK-MVE-NEXT: cset r0, mi421; CHECK-MVE-NEXT: cmp r0, #0422; CHECK-MVE-NEXT: vseleq.f16 s0, s0, s14423; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr424; CHECK-MVE-NEXT: vins.f16 s0, s12425; CHECK-MVE-NEXT: vmovx.f16 s12, s1426; CHECK-MVE-NEXT: vmov.f32 s14, s12427; CHECK-MVE-NEXT: vcmp.f16 s5, #0428; CHECK-MVE-NEXT: vmla.f16 s14, s8, s4429; CHECK-MVE-NEXT: vmov.f32 s8, s1430; CHECK-MVE-NEXT: vmla.f16 s8, s5, s9431; CHECK-MVE-NEXT: cset r0, mi432; CHECK-MVE-NEXT: cmp r0, #0433; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s14434; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr435; CHECK-MVE-NEXT: vmovx.f16 s12, s2436; CHECK-MVE-NEXT: vmov.f32 s14, s12437; CHECK-MVE-NEXT: cset r0, mi438; CHECK-MVE-NEXT: cmp r0, #0439; CHECK-MVE-NEXT: vseleq.f16 s1, s1, s8440; CHECK-MVE-NEXT: vmovx.f16 s8, s6441; CHECK-MVE-NEXT: vcmp.f16 s8, #0442; CHECK-MVE-NEXT: vins.f16 s1, s4443; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr444; CHECK-MVE-NEXT: vmovx.f16 s4, s10445; CHECK-MVE-NEXT: vmla.f16 s14, s8, s4446; CHECK-MVE-NEXT: vcmp.f16 s6, #0447; CHECK-MVE-NEXT: vmov.f32 s8, s2448; CHECK-MVE-NEXT: vmla.f16 s8, s6, s10449; CHECK-MVE-NEXT: vmovx.f16 s6, s7450; CHECK-MVE-NEXT: cset r0, mi451; CHECK-MVE-NEXT: cmp r0, #0452; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s14453; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr454; CHECK-MVE-NEXT: vcmp.f16 s6, #0455; CHECK-MVE-NEXT: cset r0, mi456; CHECK-MVE-NEXT: cmp r0, #0457; CHECK-MVE-NEXT: vseleq.f16 s2, s2, s8458; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr459; CHECK-MVE-NEXT: vmovx.f16 s8, s3460; CHECK-MVE-NEXT: vins.f16 s2, s4461; CHECK-MVE-NEXT: vmovx.f16 s4, s11462; CHECK-MVE-NEXT: vmov.f32 s10, s8463; CHECK-MVE-NEXT: vmla.f16 s10, s6, s4464; CHECK-MVE-NEXT: vcmp.f16 s7, #0465; CHECK-MVE-NEXT: vmov.f32 s6, s3466; CHECK-MVE-NEXT: vmla.f16 s6, s7, s11467; CHECK-MVE-NEXT: cset r0, mi468; CHECK-MVE-NEXT: cmp r0, #0469; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s10470; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr471; CHECK-MVE-NEXT: cset r0, mi472; CHECK-MVE-NEXT: cmp r0, #0473; CHECK-MVE-NEXT: vseleq.f16 s3, s3, s6474; CHECK-MVE-NEXT: vins.f16 s3, s4475; CHECK-MVE-NEXT: bx lr476entry:477 %0 = fmul <8 x half> %src2, %src3478 %1 = fadd <8 x half> %src1, %0479 %c = fcmp olt <8 x half> %src2, zeroinitializer480 %s = select <8 x i1> %c, <8 x half> %1, <8 x half> %src1481 ret <8 x half> %s482}483 484define arm_aapcs_vfpcc <8 x half> @vfma16_v2_pred(<8 x half> %src1, <8 x half> %src2, <8 x half> %src3) {485; CHECK-MVE-FP-LABEL: vfma16_v2_pred:486; CHECK-MVE-FP: @ %bb.0: @ %entry487; CHECK-MVE-FP-NEXT: vmul.f16 q2, q1, q2488; CHECK-MVE-FP-NEXT: vpt.f16 lt, q1, zr489; CHECK-MVE-FP-NEXT: vaddt.f16 q0, q2, q0490; CHECK-MVE-FP-NEXT: bx lr491;492; CHECK-MVE-VMLA-LABEL: vfma16_v2_pred:493; CHECK-MVE-VMLA: @ %bb.0: @ %entry494; CHECK-MVE-VMLA-NEXT: vpt.f16 lt, q1, zr495; CHECK-MVE-VMLA-NEXT: vfmat.f16 q0, q1, q2496; CHECK-MVE-VMLA-NEXT: bx lr497;498; CHECK-MVE-LABEL: vfma16_v2_pred:499; CHECK-MVE: @ %bb.0: @ %entry500; CHECK-MVE-NEXT: vmovx.f16 s14, s4501; CHECK-MVE-NEXT: vmovx.f16 s13, s0502; CHECK-MVE-NEXT: vcmp.f16 s14, #0503; CHECK-MVE-NEXT: vmovx.f16 s12, s8504; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr505; CHECK-MVE-NEXT: vmov.f32 s15, s13506; CHECK-MVE-NEXT: vmla.f16 s15, s14, s12507; CHECK-MVE-NEXT: vcmp.f16 s4, #0508; CHECK-MVE-NEXT: vmov.f32 s14, s0509; CHECK-MVE-NEXT: vmla.f16 s14, s4, s8510; CHECK-MVE-NEXT: vmovx.f16 s8, s5511; CHECK-MVE-NEXT: vmovx.f16 s4, s9512; CHECK-MVE-NEXT: cset r0, mi513; CHECK-MVE-NEXT: cmp r0, #0514; CHECK-MVE-NEXT: vseleq.f16 s12, s13, s15515; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr516; CHECK-MVE-NEXT: vcmp.f16 s8, #0517; CHECK-MVE-NEXT: cset r0, mi518; CHECK-MVE-NEXT: cmp r0, #0519; CHECK-MVE-NEXT: vseleq.f16 s0, s0, s14520; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr521; CHECK-MVE-NEXT: vins.f16 s0, s12522; CHECK-MVE-NEXT: vmovx.f16 s12, s1523; CHECK-MVE-NEXT: vmov.f32 s14, s12524; CHECK-MVE-NEXT: vcmp.f16 s5, #0525; CHECK-MVE-NEXT: vmla.f16 s14, s8, s4526; CHECK-MVE-NEXT: vmov.f32 s8, s1527; CHECK-MVE-NEXT: vmla.f16 s8, s5, s9528; CHECK-MVE-NEXT: cset r0, mi529; CHECK-MVE-NEXT: cmp r0, #0530; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s14531; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr532; CHECK-MVE-NEXT: vmovx.f16 s12, s2533; CHECK-MVE-NEXT: vmov.f32 s14, s12534; CHECK-MVE-NEXT: cset r0, mi535; CHECK-MVE-NEXT: cmp r0, #0536; CHECK-MVE-NEXT: vseleq.f16 s1, s1, s8537; CHECK-MVE-NEXT: vmovx.f16 s8, s6538; CHECK-MVE-NEXT: vcmp.f16 s8, #0539; CHECK-MVE-NEXT: vins.f16 s1, s4540; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr541; CHECK-MVE-NEXT: vmovx.f16 s4, s10542; CHECK-MVE-NEXT: vmla.f16 s14, s8, s4543; CHECK-MVE-NEXT: vcmp.f16 s6, #0544; CHECK-MVE-NEXT: vmov.f32 s8, s2545; CHECK-MVE-NEXT: vmla.f16 s8, s6, s10546; CHECK-MVE-NEXT: vmovx.f16 s6, s7547; CHECK-MVE-NEXT: cset r0, mi548; CHECK-MVE-NEXT: cmp r0, #0549; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s14550; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr551; CHECK-MVE-NEXT: vcmp.f16 s6, #0552; CHECK-MVE-NEXT: cset r0, mi553; CHECK-MVE-NEXT: cmp r0, #0554; CHECK-MVE-NEXT: vseleq.f16 s2, s2, s8555; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr556; CHECK-MVE-NEXT: vmovx.f16 s8, s3557; CHECK-MVE-NEXT: vins.f16 s2, s4558; CHECK-MVE-NEXT: vmovx.f16 s4, s11559; CHECK-MVE-NEXT: vmov.f32 s10, s8560; CHECK-MVE-NEXT: vmla.f16 s10, s6, s4561; CHECK-MVE-NEXT: vcmp.f16 s7, #0562; CHECK-MVE-NEXT: vmov.f32 s6, s3563; CHECK-MVE-NEXT: vmla.f16 s6, s7, s11564; CHECK-MVE-NEXT: cset r0, mi565; CHECK-MVE-NEXT: cmp r0, #0566; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s10567; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr568; CHECK-MVE-NEXT: cset r0, mi569; CHECK-MVE-NEXT: cmp r0, #0570; CHECK-MVE-NEXT: vseleq.f16 s3, s3, s6571; CHECK-MVE-NEXT: vins.f16 s3, s4572; CHECK-MVE-NEXT: bx lr573entry:574 %0 = fmul <8 x half> %src2, %src3575 %1 = fadd <8 x half> %0, %src1576 %c = fcmp olt <8 x half> %src2, zeroinitializer577 %s = select <8 x i1> %c, <8 x half> %1, <8 x half> %src1578 ret <8 x half> %s579}580 581define arm_aapcs_vfpcc <8 x half> @vfms16_pred(<8 x half> %src1, <8 x half> %src2, <8 x half> %src3) {582; CHECK-MVE-FP-LABEL: vfms16_pred:583; CHECK-MVE-FP: @ %bb.0: @ %entry584; CHECK-MVE-FP-NEXT: vmul.f16 q2, q1, q2585; CHECK-MVE-FP-NEXT: vpt.f16 lt, q1, zr586; CHECK-MVE-FP-NEXT: vsubt.f16 q0, q0, q2587; CHECK-MVE-FP-NEXT: bx lr588;589; CHECK-MVE-VMLA-LABEL: vfms16_pred:590; CHECK-MVE-VMLA: @ %bb.0: @ %entry591; CHECK-MVE-VMLA-NEXT: vpt.f16 lt, q1, zr592; CHECK-MVE-VMLA-NEXT: vfmst.f16 q0, q1, q2593; CHECK-MVE-VMLA-NEXT: bx lr594;595; CHECK-MVE-LABEL: vfms16_pred:596; CHECK-MVE: @ %bb.0: @ %entry597; CHECK-MVE-NEXT: vmovx.f16 s14, s4598; CHECK-MVE-NEXT: vmovx.f16 s13, s0599; CHECK-MVE-NEXT: vcmp.f16 s14, #0600; CHECK-MVE-NEXT: vmovx.f16 s12, s8601; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr602; CHECK-MVE-NEXT: vmov.f32 s15, s13603; CHECK-MVE-NEXT: vmls.f16 s15, s14, s12604; CHECK-MVE-NEXT: vcmp.f16 s4, #0605; CHECK-MVE-NEXT: vmov.f32 s14, s0606; CHECK-MVE-NEXT: vmls.f16 s14, s4, s8607; CHECK-MVE-NEXT: vmovx.f16 s8, s5608; CHECK-MVE-NEXT: vmovx.f16 s4, s9609; CHECK-MVE-NEXT: cset r0, mi610; CHECK-MVE-NEXT: cmp r0, #0611; CHECK-MVE-NEXT: vseleq.f16 s12, s13, s15612; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr613; CHECK-MVE-NEXT: vcmp.f16 s8, #0614; CHECK-MVE-NEXT: cset r0, mi615; CHECK-MVE-NEXT: cmp r0, #0616; CHECK-MVE-NEXT: vseleq.f16 s0, s0, s14617; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr618; CHECK-MVE-NEXT: vins.f16 s0, s12619; CHECK-MVE-NEXT: vmovx.f16 s12, s1620; CHECK-MVE-NEXT: vmov.f32 s14, s12621; CHECK-MVE-NEXT: vcmp.f16 s5, #0622; CHECK-MVE-NEXT: vmls.f16 s14, s8, s4623; CHECK-MVE-NEXT: vmov.f32 s8, s1624; CHECK-MVE-NEXT: vmls.f16 s8, s5, s9625; CHECK-MVE-NEXT: cset r0, mi626; CHECK-MVE-NEXT: cmp r0, #0627; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s14628; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr629; CHECK-MVE-NEXT: vmovx.f16 s12, s2630; CHECK-MVE-NEXT: vmov.f32 s14, s12631; CHECK-MVE-NEXT: cset r0, mi632; CHECK-MVE-NEXT: cmp r0, #0633; CHECK-MVE-NEXT: vseleq.f16 s1, s1, s8634; CHECK-MVE-NEXT: vmovx.f16 s8, s6635; CHECK-MVE-NEXT: vcmp.f16 s8, #0636; CHECK-MVE-NEXT: vins.f16 s1, s4637; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr638; CHECK-MVE-NEXT: vmovx.f16 s4, s10639; CHECK-MVE-NEXT: vmls.f16 s14, s8, s4640; CHECK-MVE-NEXT: vcmp.f16 s6, #0641; CHECK-MVE-NEXT: vmov.f32 s8, s2642; CHECK-MVE-NEXT: vmls.f16 s8, s6, s10643; CHECK-MVE-NEXT: vmovx.f16 s6, s7644; CHECK-MVE-NEXT: cset r0, mi645; CHECK-MVE-NEXT: cmp r0, #0646; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s14647; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr648; CHECK-MVE-NEXT: vcmp.f16 s6, #0649; CHECK-MVE-NEXT: cset r0, mi650; CHECK-MVE-NEXT: cmp r0, #0651; CHECK-MVE-NEXT: vseleq.f16 s2, s2, s8652; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr653; CHECK-MVE-NEXT: vmovx.f16 s8, s3654; CHECK-MVE-NEXT: vins.f16 s2, s4655; CHECK-MVE-NEXT: vmovx.f16 s4, s11656; CHECK-MVE-NEXT: vmov.f32 s10, s8657; CHECK-MVE-NEXT: vmls.f16 s10, s6, s4658; CHECK-MVE-NEXT: vcmp.f16 s7, #0659; CHECK-MVE-NEXT: vmov.f32 s6, s3660; CHECK-MVE-NEXT: vmls.f16 s6, s7, s11661; CHECK-MVE-NEXT: cset r0, mi662; CHECK-MVE-NEXT: cmp r0, #0663; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s10664; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr665; CHECK-MVE-NEXT: cset r0, mi666; CHECK-MVE-NEXT: cmp r0, #0667; CHECK-MVE-NEXT: vseleq.f16 s3, s3, s6668; CHECK-MVE-NEXT: vins.f16 s3, s4669; CHECK-MVE-NEXT: bx lr670entry:671 %0 = fmul <8 x half> %src2, %src3672 %1 = fsub <8 x half> %src1, %0673 %c = fcmp olt <8 x half> %src2, zeroinitializer674 %s = select <8 x i1> %c, <8 x half> %1, <8 x half> %src1675 ret <8 x half> %s676}677 678define arm_aapcs_vfpcc <8 x half> @vfmar16_pred(<8 x half> %src1, <8 x half> %src2, float %src3o) {679; CHECK-MVE-FP-LABEL: vfmar16_pred:680; CHECK-MVE-FP: @ %bb.0: @ %entry681; CHECK-MVE-FP-NEXT: vcvtb.f16.f32 s8, s8682; CHECK-MVE-FP-NEXT: vcmp.f16 lt, q1, zr683; CHECK-MVE-FP-NEXT: vmov.f16 r0, s8684; CHECK-MVE-FP-NEXT: vmul.f16 q1, q1, r0685; CHECK-MVE-FP-NEXT: vpst686; CHECK-MVE-FP-NEXT: vaddt.f16 q0, q0, q1687; CHECK-MVE-FP-NEXT: bx lr688;689; CHECK-MVE-VMLA-LABEL: vfmar16_pred:690; CHECK-MVE-VMLA: @ %bb.0: @ %entry691; CHECK-MVE-VMLA-NEXT: vcvtb.f16.f32 s8, s8692; CHECK-MVE-VMLA-NEXT: vmov.f16 r0, s8693; CHECK-MVE-VMLA-NEXT: vpt.f16 lt, q1, zr694; CHECK-MVE-VMLA-NEXT: vfmat.f16 q0, q1, r0695; CHECK-MVE-VMLA-NEXT: bx lr696;697; CHECK-MVE-LABEL: vfmar16_pred:698; CHECK-MVE: @ %bb.0: @ %entry699; CHECK-MVE-NEXT: vmovx.f16 s10, s4700; CHECK-MVE-NEXT: vmovx.f16 s12, s0701; CHECK-MVE-NEXT: vcmp.f16 s10, #0702; CHECK-MVE-NEXT: vcvtb.f16.f32 s8, s8703; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr704; CHECK-MVE-NEXT: vmov.f32 s14, s12705; CHECK-MVE-NEXT: vmla.f16 s14, s10, s8706; CHECK-MVE-NEXT: vcmp.f16 s4, #0707; CHECK-MVE-NEXT: cset r0, mi708; CHECK-MVE-NEXT: cmp r0, #0709; CHECK-MVE-NEXT: vseleq.f16 s10, s12, s14710; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr711; CHECK-MVE-NEXT: vmov.f32 s12, s0712; CHECK-MVE-NEXT: vmla.f16 s12, s4, s8713; CHECK-MVE-NEXT: vmovx.f16 s4, s5714; CHECK-MVE-NEXT: vcmp.f16 s4, #0715; CHECK-MVE-NEXT: cset r0, mi716; CHECK-MVE-NEXT: cmp r0, #0717; CHECK-MVE-NEXT: vseleq.f16 s0, s0, s12718; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr719; CHECK-MVE-NEXT: vins.f16 s0, s10720; CHECK-MVE-NEXT: vmovx.f16 s10, s1721; CHECK-MVE-NEXT: vmov.f32 s12, s10722; CHECK-MVE-NEXT: vcmp.f16 s5, #0723; CHECK-MVE-NEXT: vmla.f16 s12, s4, s8724; CHECK-MVE-NEXT: cset r0, mi725; CHECK-MVE-NEXT: cmp r0, #0726; CHECK-MVE-NEXT: vseleq.f16 s4, s10, s12727; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr728; CHECK-MVE-NEXT: vmov.f32 s10, s1729; CHECK-MVE-NEXT: vmla.f16 s10, s5, s8730; CHECK-MVE-NEXT: cset r0, mi731; CHECK-MVE-NEXT: cmp r0, #0732; CHECK-MVE-NEXT: vseleq.f16 s1, s1, s10733; CHECK-MVE-NEXT: vmovx.f16 s10, s2734; CHECK-MVE-NEXT: vins.f16 s1, s4735; CHECK-MVE-NEXT: vmovx.f16 s4, s6736; CHECK-MVE-NEXT: vcmp.f16 s4, #0737; CHECK-MVE-NEXT: vmov.f32 s12, s10738; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr739; CHECK-MVE-NEXT: vmla.f16 s12, s4, s8740; CHECK-MVE-NEXT: vcmp.f16 s6, #0741; CHECK-MVE-NEXT: cset r0, mi742; CHECK-MVE-NEXT: cmp r0, #0743; CHECK-MVE-NEXT: vseleq.f16 s4, s10, s12744; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr745; CHECK-MVE-NEXT: vmov.f32 s10, s2746; CHECK-MVE-NEXT: vmla.f16 s10, s6, s8747; CHECK-MVE-NEXT: vmovx.f16 s6, s3748; CHECK-MVE-NEXT: cset r0, mi749; CHECK-MVE-NEXT: cmp r0, #0750; CHECK-MVE-NEXT: vseleq.f16 s2, s2, s10751; CHECK-MVE-NEXT: vmov.f32 s10, s6752; CHECK-MVE-NEXT: vins.f16 s2, s4753; CHECK-MVE-NEXT: vmovx.f16 s4, s7754; CHECK-MVE-NEXT: vcmp.f16 s4, #0755; CHECK-MVE-NEXT: vmla.f16 s10, s4, s8756; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr757; CHECK-MVE-NEXT: vcmp.f16 s7, #0758; CHECK-MVE-NEXT: cset r0, mi759; CHECK-MVE-NEXT: cmp r0, #0760; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s10761; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr762; CHECK-MVE-NEXT: vmov.f32 s6, s3763; CHECK-MVE-NEXT: vmla.f16 s6, s7, s8764; CHECK-MVE-NEXT: cset r0, mi765; CHECK-MVE-NEXT: cmp r0, #0766; CHECK-MVE-NEXT: vseleq.f16 s3, s3, s6767; CHECK-MVE-NEXT: vins.f16 s3, s4768; CHECK-MVE-NEXT: bx lr769entry:770 %src3 = fptrunc float %src3o to half771 %i = insertelement <8 x half> undef, half %src3, i32 0772 %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer773 %0 = fmul <8 x half> %src2, %sp774 %1 = fadd <8 x half> %src1, %0775 %c = fcmp olt <8 x half> %src2, zeroinitializer776 %s = select <8 x i1> %c, <8 x half> %1, <8 x half> %src1777 ret <8 x half> %s778}779 780define arm_aapcs_vfpcc <8 x half> @vfma16_pred(<8 x half> %src1, <8 x half> %src2, float %src3o) {781; CHECK-MVE-FP-LABEL: vfma16_pred:782; CHECK-MVE-FP: @ %bb.0: @ %entry783; CHECK-MVE-FP-NEXT: vcvtb.f16.f32 s8, s8784; CHECK-MVE-FP-NEXT: vmov.f16 r0, s8785; CHECK-MVE-FP-NEXT: vmul.f16 q2, q0, q1786; CHECK-MVE-FP-NEXT: vpt.f16 lt, q1, zr787; CHECK-MVE-FP-NEXT: vaddt.f16 q0, q2, r0788; CHECK-MVE-FP-NEXT: bx lr789;790; CHECK-MVE-VMLA-LABEL: vfma16_pred:791; CHECK-MVE-VMLA: @ %bb.0: @ %entry792; CHECK-MVE-VMLA-NEXT: vcvtb.f16.f32 s8, s8793; CHECK-MVE-VMLA-NEXT: vmov.f16 r0, s8794; CHECK-MVE-VMLA-NEXT: vpt.f16 lt, q1, zr795; CHECK-MVE-VMLA-NEXT: vfmast.f16 q0, q1, r0796; CHECK-MVE-VMLA-NEXT: bx lr797;798; CHECK-MVE-LABEL: vfma16_pred:799; CHECK-MVE: @ %bb.0: @ %entry800; CHECK-MVE-NEXT: vmovx.f16 s10, s4801; CHECK-MVE-NEXT: vcvtb.f16.f32 s8, s8802; CHECK-MVE-NEXT: vcmp.f16 s10, #0803; CHECK-MVE-NEXT: vmovx.f16 s12, s0804; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr805; CHECK-MVE-NEXT: vmov.f32 s14, s8806; CHECK-MVE-NEXT: vmla.f16 s14, s12, s10807; CHECK-MVE-NEXT: vcmp.f16 s4, #0808; CHECK-MVE-NEXT: cset r0, mi809; CHECK-MVE-NEXT: cmp r0, #0810; CHECK-MVE-NEXT: vseleq.f16 s10, s12, s14811; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr812; CHECK-MVE-NEXT: vmov.f32 s12, s8813; CHECK-MVE-NEXT: vmla.f16 s12, s0, s4814; CHECK-MVE-NEXT: vmovx.f16 s4, s5815; CHECK-MVE-NEXT: vcmp.f16 s4, #0816; CHECK-MVE-NEXT: cset r0, mi817; CHECK-MVE-NEXT: cmp r0, #0818; CHECK-MVE-NEXT: vseleq.f16 s0, s0, s12819; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr820; CHECK-MVE-NEXT: vins.f16 s0, s10821; CHECK-MVE-NEXT: vmovx.f16 s10, s1822; CHECK-MVE-NEXT: vmov.f32 s12, s8823; CHECK-MVE-NEXT: vcmp.f16 s5, #0824; CHECK-MVE-NEXT: vmla.f16 s12, s10, s4825; CHECK-MVE-NEXT: cset r0, mi826; CHECK-MVE-NEXT: cmp r0, #0827; CHECK-MVE-NEXT: vseleq.f16 s4, s10, s12828; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr829; CHECK-MVE-NEXT: vmov.f32 s10, s8830; CHECK-MVE-NEXT: vmla.f16 s10, s1, s5831; CHECK-MVE-NEXT: vmov.f32 s12, s8832; CHECK-MVE-NEXT: cset r0, mi833; CHECK-MVE-NEXT: cmp r0, #0834; CHECK-MVE-NEXT: vseleq.f16 s1, s1, s10835; CHECK-MVE-NEXT: vmovx.f16 s10, s2836; CHECK-MVE-NEXT: vins.f16 s1, s4837; CHECK-MVE-NEXT: vmovx.f16 s4, s6838; CHECK-MVE-NEXT: vcmp.f16 s4, #0839; CHECK-MVE-NEXT: vmla.f16 s12, s10, s4840; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr841; CHECK-MVE-NEXT: vcmp.f16 s6, #0842; CHECK-MVE-NEXT: cset r0, mi843; CHECK-MVE-NEXT: cmp r0, #0844; CHECK-MVE-NEXT: vseleq.f16 s4, s10, s12845; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr846; CHECK-MVE-NEXT: vmov.f32 s10, s8847; CHECK-MVE-NEXT: vmla.f16 s10, s2, s6848; CHECK-MVE-NEXT: vmovx.f16 s6, s3849; CHECK-MVE-NEXT: cset r0, mi850; CHECK-MVE-NEXT: cmp r0, #0851; CHECK-MVE-NEXT: vseleq.f16 s2, s2, s10852; CHECK-MVE-NEXT: vmov.f32 s10, s8853; CHECK-MVE-NEXT: vins.f16 s2, s4854; CHECK-MVE-NEXT: vmovx.f16 s4, s7855; CHECK-MVE-NEXT: vcmp.f16 s4, #0856; CHECK-MVE-NEXT: vmla.f16 s10, s6, s4857; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr858; CHECK-MVE-NEXT: vcmp.f16 s7, #0859; CHECK-MVE-NEXT: vmla.f16 s8, s3, s7860; CHECK-MVE-NEXT: cset r0, mi861; CHECK-MVE-NEXT: cmp r0, #0862; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s10863; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr864; CHECK-MVE-NEXT: cset r0, mi865; CHECK-MVE-NEXT: cmp r0, #0866; CHECK-MVE-NEXT: vseleq.f16 s3, s3, s8867; CHECK-MVE-NEXT: vins.f16 s3, s4868; CHECK-MVE-NEXT: bx lr869entry:870 %src3 = fptrunc float %src3o to half871 %i = insertelement <8 x half> undef, half %src3, i32 0872 %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer873 %0 = fmul <8 x half> %src1, %src2874 %1 = fadd <8 x half> %sp, %0875 %c = fcmp olt <8 x half> %src2, zeroinitializer876 %s = select <8 x i1> %c, <8 x half> %1, <8 x half> %src1877 ret <8 x half> %s878}879 880define arm_aapcs_vfpcc <4 x float> @vfma32_v1_pred(<4 x float> %src1, <4 x float> %src2, <4 x float> %src3) {881; CHECK-MVE-FP-LABEL: vfma32_v1_pred:882; CHECK-MVE-FP: @ %bb.0: @ %entry883; CHECK-MVE-FP-NEXT: vmul.f32 q2, q1, q2884; CHECK-MVE-FP-NEXT: vpt.f32 lt, q1, zr885; CHECK-MVE-FP-NEXT: vaddt.f32 q0, q0, q2886; CHECK-MVE-FP-NEXT: bx lr887;888; CHECK-MVE-VMLA-LABEL: vfma32_v1_pred:889; CHECK-MVE-VMLA: @ %bb.0: @ %entry890; CHECK-MVE-VMLA-NEXT: vpt.f32 lt, q1, zr891; CHECK-MVE-VMLA-NEXT: vfmat.f32 q0, q1, q2892; CHECK-MVE-VMLA-NEXT: bx lr893;894; CHECK-MVE-LABEL: vfma32_v1_pred:895; CHECK-MVE: @ %bb.0: @ %entry896; CHECK-MVE-NEXT: vcmp.f32 s4, #0897; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr898; CHECK-MVE-NEXT: vcmp.f32 s7, #0899; CHECK-MVE-NEXT: vmov.f32 s12, s2900; CHECK-MVE-NEXT: vmov.f32 s14, s3901; CHECK-MVE-NEXT: vmla.f32 s12, s6, s10902; CHECK-MVE-NEXT: vmov.f32 s10, s1903; CHECK-MVE-NEXT: vmla.f32 s14, s7, s11904; CHECK-MVE-NEXT: vmla.f32 s10, s5, s9905; CHECK-MVE-NEXT: vmov.f32 s9, s0906; CHECK-MVE-NEXT: cset r0, mi907; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr908; CHECK-MVE-NEXT: vcmp.f32 s5, #0909; CHECK-MVE-NEXT: vmla.f32 s9, s4, s8910; CHECK-MVE-NEXT: cset r1, mi911; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr912; CHECK-MVE-NEXT: vcmp.f32 s6, #0913; CHECK-MVE-NEXT: cset r2, mi914; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr915; CHECK-MVE-NEXT: cset r3, mi916; CHECK-MVE-NEXT: cmp r3, #0917; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s12918; CHECK-MVE-NEXT: cmp r2, #0919; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s10920; CHECK-MVE-NEXT: cmp r1, #0921; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s14922; CHECK-MVE-NEXT: cmp r0, #0923; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s9924; CHECK-MVE-NEXT: bx lr925entry:926 %0 = fmul <4 x float> %src2, %src3927 %1 = fadd <4 x float> %src1, %0928 %c = fcmp olt <4 x float> %src2, zeroinitializer929 %s = select <4 x i1> %c, <4 x float> %1, <4 x float> %src1930 ret <4 x float> %s931}932 933define arm_aapcs_vfpcc <4 x float> @vfma32_v2_pred(<4 x float> %src1, <4 x float> %src2, <4 x float> %src3) {934; CHECK-MVE-FP-LABEL: vfma32_v2_pred:935; CHECK-MVE-FP: @ %bb.0: @ %entry936; CHECK-MVE-FP-NEXT: vmul.f32 q2, q1, q2937; CHECK-MVE-FP-NEXT: vpt.f32 lt, q1, zr938; CHECK-MVE-FP-NEXT: vaddt.f32 q0, q2, q0939; CHECK-MVE-FP-NEXT: bx lr940;941; CHECK-MVE-VMLA-LABEL: vfma32_v2_pred:942; CHECK-MVE-VMLA: @ %bb.0: @ %entry943; CHECK-MVE-VMLA-NEXT: vpt.f32 lt, q1, zr944; CHECK-MVE-VMLA-NEXT: vfmat.f32 q0, q1, q2945; CHECK-MVE-VMLA-NEXT: bx lr946;947; CHECK-MVE-LABEL: vfma32_v2_pred:948; CHECK-MVE: @ %bb.0: @ %entry949; CHECK-MVE-NEXT: vcmp.f32 s4, #0950; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr951; CHECK-MVE-NEXT: vcmp.f32 s7, #0952; CHECK-MVE-NEXT: vmov.f32 s12, s2953; CHECK-MVE-NEXT: vmov.f32 s14, s3954; CHECK-MVE-NEXT: vmla.f32 s12, s6, s10955; CHECK-MVE-NEXT: vmov.f32 s10, s1956; CHECK-MVE-NEXT: vmla.f32 s14, s7, s11957; CHECK-MVE-NEXT: vmla.f32 s10, s5, s9958; CHECK-MVE-NEXT: vmov.f32 s9, s0959; CHECK-MVE-NEXT: cset r0, mi960; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr961; CHECK-MVE-NEXT: vcmp.f32 s5, #0962; CHECK-MVE-NEXT: vmla.f32 s9, s4, s8963; CHECK-MVE-NEXT: cset r1, mi964; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr965; CHECK-MVE-NEXT: vcmp.f32 s6, #0966; CHECK-MVE-NEXT: cset r2, mi967; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr968; CHECK-MVE-NEXT: cset r3, mi969; CHECK-MVE-NEXT: cmp r3, #0970; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s12971; CHECK-MVE-NEXT: cmp r2, #0972; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s10973; CHECK-MVE-NEXT: cmp r1, #0974; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s14975; CHECK-MVE-NEXT: cmp r0, #0976; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s9977; CHECK-MVE-NEXT: bx lr978entry:979 %0 = fmul <4 x float> %src2, %src3980 %1 = fadd <4 x float> %0, %src1981 %c = fcmp olt <4 x float> %src2, zeroinitializer982 %s = select <4 x i1> %c, <4 x float> %1, <4 x float> %src1983 ret <4 x float> %s984}985 986define arm_aapcs_vfpcc <4 x float> @vfms32_pred(<4 x float> %src1, <4 x float> %src2, <4 x float> %src3) {987; CHECK-MVE-FP-LABEL: vfms32_pred:988; CHECK-MVE-FP: @ %bb.0: @ %entry989; CHECK-MVE-FP-NEXT: vmul.f32 q2, q1, q2990; CHECK-MVE-FP-NEXT: vpt.f32 lt, q1, zr991; CHECK-MVE-FP-NEXT: vsubt.f32 q0, q0, q2992; CHECK-MVE-FP-NEXT: bx lr993;994; CHECK-MVE-VMLA-LABEL: vfms32_pred:995; CHECK-MVE-VMLA: @ %bb.0: @ %entry996; CHECK-MVE-VMLA-NEXT: vpt.f32 lt, q1, zr997; CHECK-MVE-VMLA-NEXT: vfmst.f32 q0, q1, q2998; CHECK-MVE-VMLA-NEXT: bx lr999;1000; CHECK-MVE-LABEL: vfms32_pred:1001; CHECK-MVE: @ %bb.0: @ %entry1002; CHECK-MVE-NEXT: vcmp.f32 s4, #01003; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr1004; CHECK-MVE-NEXT: vcmp.f32 s7, #01005; CHECK-MVE-NEXT: vmov.f32 s12, s21006; CHECK-MVE-NEXT: vmov.f32 s14, s31007; CHECK-MVE-NEXT: vmls.f32 s12, s6, s101008; CHECK-MVE-NEXT: vmov.f32 s10, s11009; CHECK-MVE-NEXT: vmls.f32 s14, s7, s111010; CHECK-MVE-NEXT: vmls.f32 s10, s5, s91011; CHECK-MVE-NEXT: vmov.f32 s9, s01012; CHECK-MVE-NEXT: cset r0, mi1013; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr1014; CHECK-MVE-NEXT: vcmp.f32 s5, #01015; CHECK-MVE-NEXT: vmls.f32 s9, s4, s81016; CHECK-MVE-NEXT: cset r1, mi1017; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr1018; CHECK-MVE-NEXT: vcmp.f32 s6, #01019; CHECK-MVE-NEXT: cset r2, mi1020; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr1021; CHECK-MVE-NEXT: cset r3, mi1022; CHECK-MVE-NEXT: cmp r3, #01023; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s121024; CHECK-MVE-NEXT: cmp r2, #01025; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s101026; CHECK-MVE-NEXT: cmp r1, #01027; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s141028; CHECK-MVE-NEXT: cmp r0, #01029; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s91030; CHECK-MVE-NEXT: bx lr1031entry:1032 %0 = fmul <4 x float> %src2, %src31033 %1 = fsub <4 x float> %src1, %01034 %c = fcmp olt <4 x float> %src2, zeroinitializer1035 %s = select <4 x i1> %c, <4 x float> %1, <4 x float> %src11036 ret <4 x float> %s1037}1038 1039define arm_aapcs_vfpcc <4 x float> @vfmar32_pred(<4 x float> %src1, <4 x float> %src2, float %src3) {1040; CHECK-MVE-FP-LABEL: vfmar32_pred:1041; CHECK-MVE-FP: @ %bb.0: @ %entry1042; CHECK-MVE-FP-NEXT: vmov r0, s81043; CHECK-MVE-FP-NEXT: vcmp.f32 lt, q1, zr1044; CHECK-MVE-FP-NEXT: vmul.f32 q1, q1, r01045; CHECK-MVE-FP-NEXT: vpst1046; CHECK-MVE-FP-NEXT: vaddt.f32 q0, q0, q11047; CHECK-MVE-FP-NEXT: bx lr1048;1049; CHECK-MVE-VMLA-LABEL: vfmar32_pred:1050; CHECK-MVE-VMLA: @ %bb.0: @ %entry1051; CHECK-MVE-VMLA-NEXT: vmov r0, s81052; CHECK-MVE-VMLA-NEXT: vpt.f32 lt, q1, zr1053; CHECK-MVE-VMLA-NEXT: vfmat.f32 q0, q1, r01054; CHECK-MVE-VMLA-NEXT: bx lr1055;1056; CHECK-MVE-LABEL: vfmar32_pred:1057; CHECK-MVE: @ %bb.0: @ %entry1058; CHECK-MVE-NEXT: vcmp.f32 s4, #01059; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr1060; CHECK-MVE-NEXT: vcmp.f32 s7, #01061; CHECK-MVE-NEXT: vmov.f32 s10, s21062; CHECK-MVE-NEXT: vmov.f32 s12, s11063; CHECK-MVE-NEXT: vmov.f32 s14, s31064; CHECK-MVE-NEXT: vmov.f32 s9, s01065; CHECK-MVE-NEXT: vmla.f32 s10, s6, s81066; CHECK-MVE-NEXT: vmla.f32 s12, s5, s81067; CHECK-MVE-NEXT: vmla.f32 s14, s7, s81068; CHECK-MVE-NEXT: vmla.f32 s9, s4, s81069; CHECK-MVE-NEXT: cset r0, mi1070; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr1071; CHECK-MVE-NEXT: vcmp.f32 s5, #01072; CHECK-MVE-NEXT: cset r1, mi1073; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr1074; CHECK-MVE-NEXT: vcmp.f32 s6, #01075; CHECK-MVE-NEXT: cset r2, mi1076; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr1077; CHECK-MVE-NEXT: cset r3, mi1078; CHECK-MVE-NEXT: cmp r3, #01079; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s101080; CHECK-MVE-NEXT: cmp r2, #01081; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s121082; CHECK-MVE-NEXT: cmp r1, #01083; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s141084; CHECK-MVE-NEXT: cmp r0, #01085; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s91086; CHECK-MVE-NEXT: bx lr1087entry:1088 %i = insertelement <4 x float> undef, float %src3, i32 01089 %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer1090 %0 = fmul <4 x float> %src2, %sp1091 %1 = fadd <4 x float> %src1, %01092 %c = fcmp olt <4 x float> %src2, zeroinitializer1093 %s = select <4 x i1> %c, <4 x float> %1, <4 x float> %src11094 ret <4 x float> %s1095}1096 1097define arm_aapcs_vfpcc <4 x float> @vfmas32_pred(<4 x float> %src1, <4 x float> %src2, float %src3) {1098; CHECK-MVE-FP-LABEL: vfmas32_pred:1099; CHECK-MVE-FP: @ %bb.0: @ %entry1100; CHECK-MVE-FP-NEXT: vmov r0, s81101; CHECK-MVE-FP-NEXT: vmul.f32 q2, q0, q11102; CHECK-MVE-FP-NEXT: vpt.f32 lt, q1, zr1103; CHECK-MVE-FP-NEXT: vaddt.f32 q0, q2, r01104; CHECK-MVE-FP-NEXT: bx lr1105;1106; CHECK-MVE-VMLA-LABEL: vfmas32_pred:1107; CHECK-MVE-VMLA: @ %bb.0: @ %entry1108; CHECK-MVE-VMLA-NEXT: vmov r0, s81109; CHECK-MVE-VMLA-NEXT: vpt.f32 lt, q1, zr1110; CHECK-MVE-VMLA-NEXT: vfmast.f32 q0, q1, r01111; CHECK-MVE-VMLA-NEXT: bx lr1112;1113; CHECK-MVE-LABEL: vfmas32_pred:1114; CHECK-MVE: @ %bb.0: @ %entry1115; CHECK-MVE-NEXT: vcmp.f32 s4, #01116; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr1117; CHECK-MVE-NEXT: vcmp.f32 s7, #01118; CHECK-MVE-NEXT: vmov.f32 s10, s81119; CHECK-MVE-NEXT: vmov.f32 s12, s81120; CHECK-MVE-NEXT: vmov.f32 s14, s81121; CHECK-MVE-NEXT: vmla.f32 s8, s0, s41122; CHECK-MVE-NEXT: vmla.f32 s10, s2, s61123; CHECK-MVE-NEXT: vmla.f32 s12, s1, s51124; CHECK-MVE-NEXT: vmla.f32 s14, s3, s71125; CHECK-MVE-NEXT: cset r0, mi1126; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr1127; CHECK-MVE-NEXT: vcmp.f32 s5, #01128; CHECK-MVE-NEXT: cset r1, mi1129; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr1130; CHECK-MVE-NEXT: vcmp.f32 s6, #01131; CHECK-MVE-NEXT: cset r2, mi1132; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr1133; CHECK-MVE-NEXT: cset r3, mi1134; CHECK-MVE-NEXT: cmp r3, #01135; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s101136; CHECK-MVE-NEXT: cmp r2, #01137; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s121138; CHECK-MVE-NEXT: cmp r1, #01139; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s141140; CHECK-MVE-NEXT: cmp r0, #01141; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s81142; CHECK-MVE-NEXT: bx lr1143entry:1144 %i = insertelement <4 x float> undef, float %src3, i32 01145 %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer1146 %0 = fmul <4 x float> %src1, %src21147 %1 = fadd <4 x float> %sp, %01148 %c = fcmp olt <4 x float> %src2, zeroinitializer1149 %s = select <4 x i1> %c, <4 x float> %1, <4 x float> %src11150 ret <4 x float> %s1151}1152