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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,FULLFP163; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,MVEFP4; RUN: llc -early-live-intervals -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,FULLFP165; RUN: llc -early-live-intervals -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,MVEFP6 7define arm_aapcs_vfpcc <4 x float> @sqrt_float32_t(<4 x float> %src) {8; CHECK-LABEL: sqrt_float32_t:9; CHECK: @ %bb.0: @ %entry10; CHECK-NEXT: vsqrt.f32 s3, s311; CHECK-NEXT: vsqrt.f32 s2, s212; CHECK-NEXT: vsqrt.f32 s1, s113; CHECK-NEXT: vsqrt.f32 s0, s014; CHECK-NEXT: bx lr15entry:16 %0 = call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> %src)17 ret <4 x float> %018}19 20define arm_aapcs_vfpcc <8 x half> @sqrt_float16_t(<8 x half> %src) {21; CHECK-LABEL: sqrt_float16_t:22; CHECK: @ %bb.0: @ %entry23; CHECK-NEXT: vmovx.f16 s4, s024; CHECK-NEXT: vsqrt.f16 s0, s025; CHECK-NEXT: vsqrt.f16 s4, s426; CHECK-NEXT: vins.f16 s0, s427; CHECK-NEXT: vmovx.f16 s4, s128; CHECK-NEXT: vsqrt.f16 s4, s429; CHECK-NEXT: vsqrt.f16 s1, s130; CHECK-NEXT: vins.f16 s1, s431; CHECK-NEXT: vmovx.f16 s4, s232; CHECK-NEXT: vsqrt.f16 s4, s433; CHECK-NEXT: vsqrt.f16 s2, s234; CHECK-NEXT: vins.f16 s2, s435; CHECK-NEXT: vmovx.f16 s4, s336; CHECK-NEXT: vsqrt.f16 s4, s437; CHECK-NEXT: vsqrt.f16 s3, s338; CHECK-NEXT: vins.f16 s3, s439; CHECK-NEXT: bx lr40entry:41 %0 = call fast <8 x half> @llvm.sqrt.v8f16(<8 x half> %src)42 ret <8 x half> %043}44 45define arm_aapcs_vfpcc <2 x double> @sqrt_float64_t(<2 x double> %src) {46; CHECK-LABEL: sqrt_float64_t:47; CHECK: @ %bb.0: @ %entry48; CHECK-NEXT: .save {r7, lr}49; CHECK-NEXT: push {r7, lr}50; CHECK-NEXT: .vsave {d8, d9}51; CHECK-NEXT: vpush {d8, d9}52; CHECK-NEXT: vmov q4, q053; CHECK-NEXT: vmov r0, r1, d954; CHECK-NEXT: bl sqrt55; CHECK-NEXT: vmov r2, r3, d856; CHECK-NEXT: vmov d9, r0, r157; CHECK-NEXT: mov r0, r258; CHECK-NEXT: mov r1, r359; CHECK-NEXT: bl sqrt60; CHECK-NEXT: vmov d8, r0, r161; CHECK-NEXT: vmov q0, q462; CHECK-NEXT: vpop {d8, d9}63; CHECK-NEXT: pop {r7, pc}64entry:65 %0 = call fast <2 x double> @llvm.sqrt.v2f64(<2 x double> %src)66 ret <2 x double> %067}68 69define arm_aapcs_vfpcc <4 x float> @cos_float32_t(<4 x float> %src) {70; CHECK-LABEL: cos_float32_t:71; CHECK: @ %bb.0: @ %entry72; CHECK-NEXT: .save {r4, r5, r7, lr}73; CHECK-NEXT: push {r4, r5, r7, lr}74; CHECK-NEXT: .vsave {d8, d9}75; CHECK-NEXT: vpush {d8, d9}76; CHECK-NEXT: vmov q4, q077; CHECK-NEXT: vmov r0, r4, d978; CHECK-NEXT: bl cosf79; CHECK-NEXT: mov r5, r080; CHECK-NEXT: mov r0, r481; CHECK-NEXT: bl cosf82; CHECK-NEXT: vmov r4, r1, d883; CHECK-NEXT: vmov s19, r084; CHECK-NEXT: vmov s18, r585; CHECK-NEXT: mov r0, r186; CHECK-NEXT: bl cosf87; CHECK-NEXT: vmov s17, r088; CHECK-NEXT: mov r0, r489; CHECK-NEXT: bl cosf90; CHECK-NEXT: vmov s16, r091; CHECK-NEXT: vmov q0, q492; CHECK-NEXT: vpop {d8, d9}93; CHECK-NEXT: pop {r4, r5, r7, pc}94entry:95 %0 = call fast <4 x float> @llvm.cos.v4f32(<4 x float> %src)96 ret <4 x float> %097}98 99define arm_aapcs_vfpcc <8 x half> @cos_float16_t(<8 x half> %src) {100; CHECK-LABEL: cos_float16_t:101; CHECK: @ %bb.0: @ %entry102; CHECK-NEXT: .save {r7, lr}103; CHECK-NEXT: push {r7, lr}104; CHECK-NEXT: .vsave {d8, d9, d10, d11}105; CHECK-NEXT: vpush {d8, d9, d10, d11}106; CHECK-NEXT: vmov q4, q0107; CHECK-NEXT: vcvtb.f32.f16 s0, s16108; CHECK-NEXT: vmov r0, s0109; CHECK-NEXT: bl cosf110; CHECK-NEXT: vcvtt.f32.f16 s0, s16111; CHECK-NEXT: vmov s16, r0112; CHECK-NEXT: vmov r1, s0113; CHECK-NEXT: mov r0, r1114; CHECK-NEXT: bl cosf115; CHECK-NEXT: vmov s0, r0116; CHECK-NEXT: vcvtb.f16.f32 s20, s16117; CHECK-NEXT: vcvtt.f16.f32 s20, s0118; CHECK-NEXT: vcvtb.f32.f16 s0, s17119; CHECK-NEXT: vmov r0, s0120; CHECK-NEXT: bl cosf121; CHECK-NEXT: vmov s0, r0122; CHECK-NEXT: vcvtb.f16.f32 s21, s0123; CHECK-NEXT: vcvtt.f32.f16 s0, s17124; CHECK-NEXT: vmov r0, s0125; CHECK-NEXT: bl cosf126; CHECK-NEXT: vmov s0, r0127; CHECK-NEXT: vcvtt.f16.f32 s21, s0128; CHECK-NEXT: vcvtb.f32.f16 s0, s18129; CHECK-NEXT: vmov r0, s0130; CHECK-NEXT: bl cosf131; CHECK-NEXT: vmov s0, r0132; CHECK-NEXT: vcvtb.f16.f32 s22, s0133; CHECK-NEXT: vcvtt.f32.f16 s0, s18134; CHECK-NEXT: vmov r0, s0135; CHECK-NEXT: bl cosf136; CHECK-NEXT: vmov s0, r0137; CHECK-NEXT: vcvtt.f16.f32 s22, s0138; CHECK-NEXT: vcvtb.f32.f16 s0, s19139; CHECK-NEXT: vmov r0, s0140; CHECK-NEXT: bl cosf141; CHECK-NEXT: vmov s0, r0142; CHECK-NEXT: vcvtb.f16.f32 s23, s0143; CHECK-NEXT: vcvtt.f32.f16 s0, s19144; CHECK-NEXT: vmov r0, s0145; CHECK-NEXT: bl cosf146; CHECK-NEXT: vmov s0, r0147; CHECK-NEXT: vcvtt.f16.f32 s23, s0148; CHECK-NEXT: vmov q0, q5149; CHECK-NEXT: vpop {d8, d9, d10, d11}150; CHECK-NEXT: pop {r7, pc}151entry:152 %0 = call fast <8 x half> @llvm.cos.v8f16(<8 x half> %src)153 ret <8 x half> %0154}155 156define arm_aapcs_vfpcc <2 x double> @cos_float64_t(<2 x double> %src) {157; CHECK-LABEL: cos_float64_t:158; CHECK: @ %bb.0: @ %entry159; CHECK-NEXT: .save {r7, lr}160; CHECK-NEXT: push {r7, lr}161; CHECK-NEXT: .vsave {d8, d9}162; CHECK-NEXT: vpush {d8, d9}163; CHECK-NEXT: vmov q4, q0164; CHECK-NEXT: vmov r0, r1, d9165; CHECK-NEXT: bl cos166; CHECK-NEXT: vmov r2, r3, d8167; CHECK-NEXT: vmov d9, r0, r1168; CHECK-NEXT: mov r0, r2169; CHECK-NEXT: mov r1, r3170; CHECK-NEXT: bl cos171; CHECK-NEXT: vmov d8, r0, r1172; CHECK-NEXT: vmov q0, q4173; CHECK-NEXT: vpop {d8, d9}174; CHECK-NEXT: pop {r7, pc}175entry:176 %0 = call fast <2 x double> @llvm.cos.v2f64(<2 x double> %src)177 ret <2 x double> %0178}179 180define arm_aapcs_vfpcc <4 x float> @sin_float32_t(<4 x float> %src) {181; CHECK-LABEL: sin_float32_t:182; CHECK: @ %bb.0: @ %entry183; CHECK-NEXT: .save {r4, r5, r7, lr}184; CHECK-NEXT: push {r4, r5, r7, lr}185; CHECK-NEXT: .vsave {d8, d9}186; CHECK-NEXT: vpush {d8, d9}187; CHECK-NEXT: vmov q4, q0188; CHECK-NEXT: vmov r0, r4, d9189; CHECK-NEXT: bl sinf190; CHECK-NEXT: mov r5, r0191; CHECK-NEXT: mov r0, r4192; CHECK-NEXT: bl sinf193; CHECK-NEXT: vmov r4, r1, d8194; CHECK-NEXT: vmov s19, r0195; CHECK-NEXT: vmov s18, r5196; CHECK-NEXT: mov r0, r1197; CHECK-NEXT: bl sinf198; CHECK-NEXT: vmov s17, r0199; CHECK-NEXT: mov r0, r4200; CHECK-NEXT: bl sinf201; CHECK-NEXT: vmov s16, r0202; CHECK-NEXT: vmov q0, q4203; CHECK-NEXT: vpop {d8, d9}204; CHECK-NEXT: pop {r4, r5, r7, pc}205entry:206 %0 = call fast <4 x float> @llvm.sin.v4f32(<4 x float> %src)207 ret <4 x float> %0208}209 210define arm_aapcs_vfpcc <8 x half> @sin_float16_t(<8 x half> %src) {211; CHECK-LABEL: sin_float16_t:212; CHECK: @ %bb.0: @ %entry213; CHECK-NEXT: .save {r7, lr}214; CHECK-NEXT: push {r7, lr}215; CHECK-NEXT: .vsave {d8, d9, d10, d11}216; CHECK-NEXT: vpush {d8, d9, d10, d11}217; CHECK-NEXT: vmov q4, q0218; CHECK-NEXT: vcvtb.f32.f16 s0, s16219; CHECK-NEXT: vmov r0, s0220; CHECK-NEXT: bl sinf221; CHECK-NEXT: vcvtt.f32.f16 s0, s16222; CHECK-NEXT: vmov s16, r0223; CHECK-NEXT: vmov r1, s0224; CHECK-NEXT: mov r0, r1225; CHECK-NEXT: bl sinf226; CHECK-NEXT: vmov s0, r0227; CHECK-NEXT: vcvtb.f16.f32 s20, s16228; CHECK-NEXT: vcvtt.f16.f32 s20, s0229; CHECK-NEXT: vcvtb.f32.f16 s0, s17230; CHECK-NEXT: vmov r0, s0231; CHECK-NEXT: bl sinf232; CHECK-NEXT: vmov s0, r0233; CHECK-NEXT: vcvtb.f16.f32 s21, s0234; CHECK-NEXT: vcvtt.f32.f16 s0, s17235; CHECK-NEXT: vmov r0, s0236; CHECK-NEXT: bl sinf237; CHECK-NEXT: vmov s0, r0238; CHECK-NEXT: vcvtt.f16.f32 s21, s0239; CHECK-NEXT: vcvtb.f32.f16 s0, s18240; CHECK-NEXT: vmov r0, s0241; CHECK-NEXT: bl sinf242; CHECK-NEXT: vmov s0, r0243; CHECK-NEXT: vcvtb.f16.f32 s22, s0244; CHECK-NEXT: vcvtt.f32.f16 s0, s18245; CHECK-NEXT: vmov r0, s0246; CHECK-NEXT: bl sinf247; CHECK-NEXT: vmov s0, r0248; CHECK-NEXT: vcvtt.f16.f32 s22, s0249; CHECK-NEXT: vcvtb.f32.f16 s0, s19250; CHECK-NEXT: vmov r0, s0251; CHECK-NEXT: bl sinf252; CHECK-NEXT: vmov s0, r0253; CHECK-NEXT: vcvtb.f16.f32 s23, s0254; CHECK-NEXT: vcvtt.f32.f16 s0, s19255; CHECK-NEXT: vmov r0, s0256; CHECK-NEXT: bl sinf257; CHECK-NEXT: vmov s0, r0258; CHECK-NEXT: vcvtt.f16.f32 s23, s0259; CHECK-NEXT: vmov q0, q5260; CHECK-NEXT: vpop {d8, d9, d10, d11}261; CHECK-NEXT: pop {r7, pc}262entry:263 %0 = call fast <8 x half> @llvm.sin.v8f16(<8 x half> %src)264 ret <8 x half> %0265}266 267define arm_aapcs_vfpcc <2 x double> @sin_float64_t(<2 x double> %src) {268; CHECK-LABEL: sin_float64_t:269; CHECK: @ %bb.0: @ %entry270; CHECK-NEXT: .save {r7, lr}271; CHECK-NEXT: push {r7, lr}272; CHECK-NEXT: .vsave {d8, d9}273; CHECK-NEXT: vpush {d8, d9}274; CHECK-NEXT: vmov q4, q0275; CHECK-NEXT: vmov r0, r1, d9276; CHECK-NEXT: bl sin277; CHECK-NEXT: vmov r2, r3, d8278; CHECK-NEXT: vmov d9, r0, r1279; CHECK-NEXT: mov r0, r2280; CHECK-NEXT: mov r1, r3281; CHECK-NEXT: bl sin282; CHECK-NEXT: vmov d8, r0, r1283; CHECK-NEXT: vmov q0, q4284; CHECK-NEXT: vpop {d8, d9}285; CHECK-NEXT: pop {r7, pc}286entry:287 %0 = call fast <2 x double> @llvm.sin.v2f64(<2 x double> %src)288 ret <2 x double> %0289}290 291define arm_aapcs_vfpcc <4 x float> @tan_float32_t(<4 x float> %src) {292; CHECK-LABEL: tan_float32_t:293; CHECK: @ %bb.0: @ %entry294; CHECK-NEXT: .save {r4, r5, r7, lr}295; CHECK-NEXT: push {r4, r5, r7, lr}296; CHECK-NEXT: .vsave {d8, d9}297; CHECK-NEXT: vpush {d8, d9}298; CHECK-NEXT: vmov q4, q0299; CHECK-NEXT: vmov r0, r4, d9300; CHECK-NEXT: bl tanf301; CHECK-NEXT: mov r5, r0302; CHECK-NEXT: mov r0, r4303; CHECK-NEXT: bl tanf304; CHECK-NEXT: vmov r4, r1, d8305; CHECK-NEXT: vmov s19, r0306; CHECK-NEXT: vmov s18, r5307; CHECK-NEXT: mov r0, r1308; CHECK-NEXT: bl tanf309; CHECK-NEXT: vmov s17, r0310; CHECK-NEXT: mov r0, r4311; CHECK-NEXT: bl tanf312; CHECK-NEXT: vmov s16, r0313; CHECK-NEXT: vmov q0, q4314; CHECK-NEXT: vpop {d8, d9}315; CHECK-NEXT: pop {r4, r5, r7, pc}316entry:317 %0 = call fast <4 x float> @llvm.tan.v4f32(<4 x float> %src)318 ret <4 x float> %0319}320 321define arm_aapcs_vfpcc <8 x half> @tan_float16_t(<8 x half> %src) {322; CHECK-LABEL: tan_float16_t:323; CHECK: @ %bb.0: @ %entry324; CHECK-NEXT: .save {r7, lr}325; CHECK-NEXT: push {r7, lr}326; CHECK-NEXT: .vsave {d8, d9, d10, d11}327; CHECK-NEXT: vpush {d8, d9, d10, d11}328; CHECK-NEXT: vmov q4, q0329; CHECK-NEXT: vcvtb.f32.f16 s0, s16330; CHECK-NEXT: vmov r0, s0331; CHECK-NEXT: bl tanf332; CHECK-NEXT: vcvtt.f32.f16 s0, s16333; CHECK-NEXT: vmov s16, r0334; CHECK-NEXT: vmov r1, s0335; CHECK-NEXT: mov r0, r1336; CHECK-NEXT: bl tanf337; CHECK-NEXT: vmov s0, r0338; CHECK-NEXT: vcvtb.f16.f32 s20, s16339; CHECK-NEXT: vcvtt.f16.f32 s20, s0340; CHECK-NEXT: vcvtb.f32.f16 s0, s17341; CHECK-NEXT: vmov r0, s0342; CHECK-NEXT: bl tanf343; CHECK-NEXT: vmov s0, r0344; CHECK-NEXT: vcvtb.f16.f32 s21, s0345; CHECK-NEXT: vcvtt.f32.f16 s0, s17346; CHECK-NEXT: vmov r0, s0347; CHECK-NEXT: bl tanf348; CHECK-NEXT: vmov s0, r0349; CHECK-NEXT: vcvtt.f16.f32 s21, s0350; CHECK-NEXT: vcvtb.f32.f16 s0, s18351; CHECK-NEXT: vmov r0, s0352; CHECK-NEXT: bl tanf353; CHECK-NEXT: vmov s0, r0354; CHECK-NEXT: vcvtb.f16.f32 s22, s0355; CHECK-NEXT: vcvtt.f32.f16 s0, s18356; CHECK-NEXT: vmov r0, s0357; CHECK-NEXT: bl tanf358; CHECK-NEXT: vmov s0, r0359; CHECK-NEXT: vcvtt.f16.f32 s22, s0360; CHECK-NEXT: vcvtb.f32.f16 s0, s19361; CHECK-NEXT: vmov r0, s0362; CHECK-NEXT: bl tanf363; CHECK-NEXT: vmov s0, r0364; CHECK-NEXT: vcvtb.f16.f32 s23, s0365; CHECK-NEXT: vcvtt.f32.f16 s0, s19366; CHECK-NEXT: vmov r0, s0367; CHECK-NEXT: bl tanf368; CHECK-NEXT: vmov s0, r0369; CHECK-NEXT: vcvtt.f16.f32 s23, s0370; CHECK-NEXT: vmov q0, q5371; CHECK-NEXT: vpop {d8, d9, d10, d11}372; CHECK-NEXT: pop {r7, pc}373entry:374 %0 = call fast <8 x half> @llvm.tan.v8f16(<8 x half> %src)375 ret <8 x half> %0376}377 378define arm_aapcs_vfpcc <2 x double> @tan_float64_t(<2 x double> %src) {379; CHECK-LABEL: tan_float64_t:380; CHECK: @ %bb.0: @ %entry381; CHECK-NEXT: .save {r7, lr}382; CHECK-NEXT: push {r7, lr}383; CHECK-NEXT: .vsave {d8, d9}384; CHECK-NEXT: vpush {d8, d9}385; CHECK-NEXT: vmov q4, q0386; CHECK-NEXT: vmov r0, r1, d9387; CHECK-NEXT: bl tan388; CHECK-NEXT: vmov r2, r3, d8389; CHECK-NEXT: vmov d9, r0, r1390; CHECK-NEXT: mov r0, r2391; CHECK-NEXT: mov r1, r3392; CHECK-NEXT: bl tan393; CHECK-NEXT: vmov d8, r0, r1394; CHECK-NEXT: vmov q0, q4395; CHECK-NEXT: vpop {d8, d9}396; CHECK-NEXT: pop {r7, pc}397entry:398 %0 = call fast <2 x double> @llvm.tan.v2f64(<2 x double> %src)399 ret <2 x double> %0400}401 402define arm_aapcs_vfpcc <4 x float> @exp_float32_t(<4 x float> %src) {403; CHECK-LABEL: exp_float32_t:404; CHECK: @ %bb.0: @ %entry405; CHECK-NEXT: .save {r4, r5, r7, lr}406; CHECK-NEXT: push {r4, r5, r7, lr}407; CHECK-NEXT: .vsave {d8, d9}408; CHECK-NEXT: vpush {d8, d9}409; CHECK-NEXT: vmov q4, q0410; CHECK-NEXT: vmov r0, r4, d9411; CHECK-NEXT: bl expf412; CHECK-NEXT: mov r5, r0413; CHECK-NEXT: mov r0, r4414; CHECK-NEXT: bl expf415; CHECK-NEXT: vmov r4, r1, d8416; CHECK-NEXT: vmov s19, r0417; CHECK-NEXT: vmov s18, r5418; CHECK-NEXT: mov r0, r1419; CHECK-NEXT: bl expf420; CHECK-NEXT: vmov s17, r0421; CHECK-NEXT: mov r0, r4422; CHECK-NEXT: bl expf423; CHECK-NEXT: vmov s16, r0424; CHECK-NEXT: vmov q0, q4425; CHECK-NEXT: vpop {d8, d9}426; CHECK-NEXT: pop {r4, r5, r7, pc}427entry:428 %0 = call fast <4 x float> @llvm.exp.v4f32(<4 x float> %src)429 ret <4 x float> %0430}431 432define arm_aapcs_vfpcc <8 x half> @exp_float16_t(<8 x half> %src) {433; CHECK-LABEL: exp_float16_t:434; CHECK: @ %bb.0: @ %entry435; CHECK-NEXT: .save {r7, lr}436; CHECK-NEXT: push {r7, lr}437; CHECK-NEXT: .vsave {d8, d9, d10, d11}438; CHECK-NEXT: vpush {d8, d9, d10, d11}439; CHECK-NEXT: vmov q4, q0440; CHECK-NEXT: vcvtb.f32.f16 s0, s16441; CHECK-NEXT: vmov r0, s0442; CHECK-NEXT: bl expf443; CHECK-NEXT: vcvtt.f32.f16 s0, s16444; CHECK-NEXT: vmov s16, r0445; CHECK-NEXT: vmov r1, s0446; CHECK-NEXT: mov r0, r1447; CHECK-NEXT: bl expf448; CHECK-NEXT: vmov s0, r0449; CHECK-NEXT: vcvtb.f16.f32 s20, s16450; CHECK-NEXT: vcvtt.f16.f32 s20, s0451; CHECK-NEXT: vcvtb.f32.f16 s0, s17452; CHECK-NEXT: vmov r0, s0453; CHECK-NEXT: bl expf454; CHECK-NEXT: vmov s0, r0455; CHECK-NEXT: vcvtb.f16.f32 s21, s0456; CHECK-NEXT: vcvtt.f32.f16 s0, s17457; CHECK-NEXT: vmov r0, s0458; CHECK-NEXT: bl expf459; CHECK-NEXT: vmov s0, r0460; CHECK-NEXT: vcvtt.f16.f32 s21, s0461; CHECK-NEXT: vcvtb.f32.f16 s0, s18462; CHECK-NEXT: vmov r0, s0463; CHECK-NEXT: bl expf464; CHECK-NEXT: vmov s0, r0465; CHECK-NEXT: vcvtb.f16.f32 s22, s0466; CHECK-NEXT: vcvtt.f32.f16 s0, s18467; CHECK-NEXT: vmov r0, s0468; CHECK-NEXT: bl expf469; CHECK-NEXT: vmov s0, r0470; CHECK-NEXT: vcvtt.f16.f32 s22, s0471; CHECK-NEXT: vcvtb.f32.f16 s0, s19472; CHECK-NEXT: vmov r0, s0473; CHECK-NEXT: bl expf474; CHECK-NEXT: vmov s0, r0475; CHECK-NEXT: vcvtb.f16.f32 s23, s0476; CHECK-NEXT: vcvtt.f32.f16 s0, s19477; CHECK-NEXT: vmov r0, s0478; CHECK-NEXT: bl expf479; CHECK-NEXT: vmov s0, r0480; CHECK-NEXT: vcvtt.f16.f32 s23, s0481; CHECK-NEXT: vmov q0, q5482; CHECK-NEXT: vpop {d8, d9, d10, d11}483; CHECK-NEXT: pop {r7, pc}484entry:485 %0 = call fast <8 x half> @llvm.exp.v8f16(<8 x half> %src)486 ret <8 x half> %0487}488 489define arm_aapcs_vfpcc <2 x double> @exp_float64_t(<2 x double> %src) {490; CHECK-LABEL: exp_float64_t:491; CHECK: @ %bb.0: @ %entry492; CHECK-NEXT: .save {r7, lr}493; CHECK-NEXT: push {r7, lr}494; CHECK-NEXT: .vsave {d8, d9}495; CHECK-NEXT: vpush {d8, d9}496; CHECK-NEXT: vmov q4, q0497; CHECK-NEXT: vmov r0, r1, d9498; CHECK-NEXT: bl exp499; CHECK-NEXT: vmov r2, r3, d8500; CHECK-NEXT: vmov d9, r0, r1501; CHECK-NEXT: mov r0, r2502; CHECK-NEXT: mov r1, r3503; CHECK-NEXT: bl exp504; CHECK-NEXT: vmov d8, r0, r1505; CHECK-NEXT: vmov q0, q4506; CHECK-NEXT: vpop {d8, d9}507; CHECK-NEXT: pop {r7, pc}508entry:509 %0 = call fast <2 x double> @llvm.exp.v2f64(<2 x double> %src)510 ret <2 x double> %0511}512 513define arm_aapcs_vfpcc <4 x float> @exp2_float32_t(<4 x float> %src) {514; CHECK-LABEL: exp2_float32_t:515; CHECK: @ %bb.0: @ %entry516; CHECK-NEXT: .save {r4, r5, r7, lr}517; CHECK-NEXT: push {r4, r5, r7, lr}518; CHECK-NEXT: .vsave {d8, d9}519; CHECK-NEXT: vpush {d8, d9}520; CHECK-NEXT: vmov q4, q0521; CHECK-NEXT: vmov r0, r4, d9522; CHECK-NEXT: bl exp2f523; CHECK-NEXT: mov r5, r0524; CHECK-NEXT: mov r0, r4525; CHECK-NEXT: bl exp2f526; CHECK-NEXT: vmov r4, r1, d8527; CHECK-NEXT: vmov s19, r0528; CHECK-NEXT: vmov s18, r5529; CHECK-NEXT: mov r0, r1530; CHECK-NEXT: bl exp2f531; CHECK-NEXT: vmov s17, r0532; CHECK-NEXT: mov r0, r4533; CHECK-NEXT: bl exp2f534; CHECK-NEXT: vmov s16, r0535; CHECK-NEXT: vmov q0, q4536; CHECK-NEXT: vpop {d8, d9}537; CHECK-NEXT: pop {r4, r5, r7, pc}538entry:539 %0 = call fast <4 x float> @llvm.exp2.v4f32(<4 x float> %src)540 ret <4 x float> %0541}542 543define arm_aapcs_vfpcc <8 x half> @exp2_float16_t(<8 x half> %src) {544; CHECK-LABEL: exp2_float16_t:545; CHECK: @ %bb.0: @ %entry546; CHECK-NEXT: .save {r7, lr}547; CHECK-NEXT: push {r7, lr}548; CHECK-NEXT: .vsave {d8, d9, d10, d11}549; CHECK-NEXT: vpush {d8, d9, d10, d11}550; CHECK-NEXT: vmov q4, q0551; CHECK-NEXT: vcvtb.f32.f16 s0, s16552; CHECK-NEXT: vmov r0, s0553; CHECK-NEXT: bl exp2f554; CHECK-NEXT: vcvtt.f32.f16 s0, s16555; CHECK-NEXT: vmov s16, r0556; CHECK-NEXT: vmov r1, s0557; CHECK-NEXT: mov r0, r1558; CHECK-NEXT: bl exp2f559; CHECK-NEXT: vmov s0, r0560; CHECK-NEXT: vcvtb.f16.f32 s20, s16561; CHECK-NEXT: vcvtt.f16.f32 s20, s0562; CHECK-NEXT: vcvtb.f32.f16 s0, s17563; CHECK-NEXT: vmov r0, s0564; CHECK-NEXT: bl exp2f565; CHECK-NEXT: vmov s0, r0566; CHECK-NEXT: vcvtb.f16.f32 s21, s0567; CHECK-NEXT: vcvtt.f32.f16 s0, s17568; CHECK-NEXT: vmov r0, s0569; CHECK-NEXT: bl exp2f570; CHECK-NEXT: vmov s0, r0571; CHECK-NEXT: vcvtt.f16.f32 s21, s0572; CHECK-NEXT: vcvtb.f32.f16 s0, s18573; CHECK-NEXT: vmov r0, s0574; CHECK-NEXT: bl exp2f575; CHECK-NEXT: vmov s0, r0576; CHECK-NEXT: vcvtb.f16.f32 s22, s0577; CHECK-NEXT: vcvtt.f32.f16 s0, s18578; CHECK-NEXT: vmov r0, s0579; CHECK-NEXT: bl exp2f580; CHECK-NEXT: vmov s0, r0581; CHECK-NEXT: vcvtt.f16.f32 s22, s0582; CHECK-NEXT: vcvtb.f32.f16 s0, s19583; CHECK-NEXT: vmov r0, s0584; CHECK-NEXT: bl exp2f585; CHECK-NEXT: vmov s0, r0586; CHECK-NEXT: vcvtb.f16.f32 s23, s0587; CHECK-NEXT: vcvtt.f32.f16 s0, s19588; CHECK-NEXT: vmov r0, s0589; CHECK-NEXT: bl exp2f590; CHECK-NEXT: vmov s0, r0591; CHECK-NEXT: vcvtt.f16.f32 s23, s0592; CHECK-NEXT: vmov q0, q5593; CHECK-NEXT: vpop {d8, d9, d10, d11}594; CHECK-NEXT: pop {r7, pc}595entry:596 %0 = call fast <8 x half> @llvm.exp2.v8f16(<8 x half> %src)597 ret <8 x half> %0598}599 600define arm_aapcs_vfpcc <2 x double> @exp2_float64_t(<2 x double> %src) {601; CHECK-LABEL: exp2_float64_t:602; CHECK: @ %bb.0: @ %entry603; CHECK-NEXT: .save {r7, lr}604; CHECK-NEXT: push {r7, lr}605; CHECK-NEXT: .vsave {d8, d9}606; CHECK-NEXT: vpush {d8, d9}607; CHECK-NEXT: vmov q4, q0608; CHECK-NEXT: vmov r0, r1, d9609; CHECK-NEXT: bl exp2610; CHECK-NEXT: vmov r2, r3, d8611; CHECK-NEXT: vmov d9, r0, r1612; CHECK-NEXT: mov r0, r2613; CHECK-NEXT: mov r1, r3614; CHECK-NEXT: bl exp2615; CHECK-NEXT: vmov d8, r0, r1616; CHECK-NEXT: vmov q0, q4617; CHECK-NEXT: vpop {d8, d9}618; CHECK-NEXT: pop {r7, pc}619entry:620 %0 = call fast <2 x double> @llvm.exp2.v2f64(<2 x double> %src)621 ret <2 x double> %0622}623 624define arm_aapcs_vfpcc <4 x float> @log_float32_t(<4 x float> %src) {625; CHECK-LABEL: log_float32_t:626; CHECK: @ %bb.0: @ %entry627; CHECK-NEXT: .save {r4, r5, r7, lr}628; CHECK-NEXT: push {r4, r5, r7, lr}629; CHECK-NEXT: .vsave {d8, d9}630; CHECK-NEXT: vpush {d8, d9}631; CHECK-NEXT: vmov q4, q0632; CHECK-NEXT: vmov r0, r4, d9633; CHECK-NEXT: bl logf634; CHECK-NEXT: mov r5, r0635; CHECK-NEXT: mov r0, r4636; CHECK-NEXT: bl logf637; CHECK-NEXT: vmov r4, r1, d8638; CHECK-NEXT: vmov s19, r0639; CHECK-NEXT: vmov s18, r5640; CHECK-NEXT: mov r0, r1641; CHECK-NEXT: bl logf642; CHECK-NEXT: vmov s17, r0643; CHECK-NEXT: mov r0, r4644; CHECK-NEXT: bl logf645; CHECK-NEXT: vmov s16, r0646; CHECK-NEXT: vmov q0, q4647; CHECK-NEXT: vpop {d8, d9}648; CHECK-NEXT: pop {r4, r5, r7, pc}649entry:650 %0 = call fast <4 x float> @llvm.log.v4f32(<4 x float> %src)651 ret <4 x float> %0652}653 654define arm_aapcs_vfpcc <8 x half> @log_float16_t(<8 x half> %src) {655; CHECK-LABEL: log_float16_t:656; CHECK: @ %bb.0: @ %entry657; CHECK-NEXT: .save {r7, lr}658; CHECK-NEXT: push {r7, lr}659; CHECK-NEXT: .vsave {d8, d9, d10, d11}660; CHECK-NEXT: vpush {d8, d9, d10, d11}661; CHECK-NEXT: vmov q4, q0662; CHECK-NEXT: vcvtb.f32.f16 s0, s16663; CHECK-NEXT: vmov r0, s0664; CHECK-NEXT: bl logf665; CHECK-NEXT: vcvtt.f32.f16 s0, s16666; CHECK-NEXT: vmov s16, r0667; CHECK-NEXT: vmov r1, s0668; CHECK-NEXT: mov r0, r1669; CHECK-NEXT: bl logf670; CHECK-NEXT: vmov s0, r0671; CHECK-NEXT: vcvtb.f16.f32 s20, s16672; CHECK-NEXT: vcvtt.f16.f32 s20, s0673; CHECK-NEXT: vcvtb.f32.f16 s0, s17674; CHECK-NEXT: vmov r0, s0675; CHECK-NEXT: bl logf676; CHECK-NEXT: vmov s0, r0677; CHECK-NEXT: vcvtb.f16.f32 s21, s0678; CHECK-NEXT: vcvtt.f32.f16 s0, s17679; CHECK-NEXT: vmov r0, s0680; CHECK-NEXT: bl logf681; CHECK-NEXT: vmov s0, r0682; CHECK-NEXT: vcvtt.f16.f32 s21, s0683; CHECK-NEXT: vcvtb.f32.f16 s0, s18684; CHECK-NEXT: vmov r0, s0685; CHECK-NEXT: bl logf686; CHECK-NEXT: vmov s0, r0687; CHECK-NEXT: vcvtb.f16.f32 s22, s0688; CHECK-NEXT: vcvtt.f32.f16 s0, s18689; CHECK-NEXT: vmov r0, s0690; CHECK-NEXT: bl logf691; CHECK-NEXT: vmov s0, r0692; CHECK-NEXT: vcvtt.f16.f32 s22, s0693; CHECK-NEXT: vcvtb.f32.f16 s0, s19694; CHECK-NEXT: vmov r0, s0695; CHECK-NEXT: bl logf696; CHECK-NEXT: vmov s0, r0697; CHECK-NEXT: vcvtb.f16.f32 s23, s0698; CHECK-NEXT: vcvtt.f32.f16 s0, s19699; CHECK-NEXT: vmov r0, s0700; CHECK-NEXT: bl logf701; CHECK-NEXT: vmov s0, r0702; CHECK-NEXT: vcvtt.f16.f32 s23, s0703; CHECK-NEXT: vmov q0, q5704; CHECK-NEXT: vpop {d8, d9, d10, d11}705; CHECK-NEXT: pop {r7, pc}706entry:707 %0 = call fast <8 x half> @llvm.log.v8f16(<8 x half> %src)708 ret <8 x half> %0709}710 711define arm_aapcs_vfpcc <2 x double> @log_float64_t(<2 x double> %src) {712; CHECK-LABEL: log_float64_t:713; CHECK: @ %bb.0: @ %entry714; CHECK-NEXT: .save {r7, lr}715; CHECK-NEXT: push {r7, lr}716; CHECK-NEXT: .vsave {d8, d9}717; CHECK-NEXT: vpush {d8, d9}718; CHECK-NEXT: vmov q4, q0719; CHECK-NEXT: vmov r0, r1, d9720; CHECK-NEXT: bl log721; CHECK-NEXT: vmov r2, r3, d8722; CHECK-NEXT: vmov d9, r0, r1723; CHECK-NEXT: mov r0, r2724; CHECK-NEXT: mov r1, r3725; CHECK-NEXT: bl log726; CHECK-NEXT: vmov d8, r0, r1727; CHECK-NEXT: vmov q0, q4728; CHECK-NEXT: vpop {d8, d9}729; CHECK-NEXT: pop {r7, pc}730entry:731 %0 = call fast <2 x double> @llvm.log.v2f64(<2 x double> %src)732 ret <2 x double> %0733}734 735define arm_aapcs_vfpcc <4 x float> @log2_float32_t(<4 x float> %src) {736; CHECK-LABEL: log2_float32_t:737; CHECK: @ %bb.0: @ %entry738; CHECK-NEXT: .save {r4, r5, r7, lr}739; CHECK-NEXT: push {r4, r5, r7, lr}740; CHECK-NEXT: .vsave {d8, d9}741; CHECK-NEXT: vpush {d8, d9}742; CHECK-NEXT: vmov q4, q0743; CHECK-NEXT: vmov r0, r4, d9744; CHECK-NEXT: bl log2f745; CHECK-NEXT: mov r5, r0746; CHECK-NEXT: mov r0, r4747; CHECK-NEXT: bl log2f748; CHECK-NEXT: vmov r4, r1, d8749; CHECK-NEXT: vmov s19, r0750; CHECK-NEXT: vmov s18, r5751; CHECK-NEXT: mov r0, r1752; CHECK-NEXT: bl log2f753; CHECK-NEXT: vmov s17, r0754; CHECK-NEXT: mov r0, r4755; CHECK-NEXT: bl log2f756; CHECK-NEXT: vmov s16, r0757; CHECK-NEXT: vmov q0, q4758; CHECK-NEXT: vpop {d8, d9}759; CHECK-NEXT: pop {r4, r5, r7, pc}760entry:761 %0 = call fast <4 x float> @llvm.log2.v4f32(<4 x float> %src)762 ret <4 x float> %0763}764 765define arm_aapcs_vfpcc <8 x half> @log2_float16_t(<8 x half> %src) {766; CHECK-LABEL: log2_float16_t:767; CHECK: @ %bb.0: @ %entry768; CHECK-NEXT: .save {r7, lr}769; CHECK-NEXT: push {r7, lr}770; CHECK-NEXT: .vsave {d8, d9, d10, d11}771; CHECK-NEXT: vpush {d8, d9, d10, d11}772; CHECK-NEXT: vmov q4, q0773; CHECK-NEXT: vcvtb.f32.f16 s0, s16774; CHECK-NEXT: vmov r0, s0775; CHECK-NEXT: bl log2f776; CHECK-NEXT: vcvtt.f32.f16 s0, s16777; CHECK-NEXT: vmov s16, r0778; CHECK-NEXT: vmov r1, s0779; CHECK-NEXT: mov r0, r1780; CHECK-NEXT: bl log2f781; CHECK-NEXT: vmov s0, r0782; CHECK-NEXT: vcvtb.f16.f32 s20, s16783; CHECK-NEXT: vcvtt.f16.f32 s20, s0784; CHECK-NEXT: vcvtb.f32.f16 s0, s17785; CHECK-NEXT: vmov r0, s0786; CHECK-NEXT: bl log2f787; CHECK-NEXT: vmov s0, r0788; CHECK-NEXT: vcvtb.f16.f32 s21, s0789; CHECK-NEXT: vcvtt.f32.f16 s0, s17790; CHECK-NEXT: vmov r0, s0791; CHECK-NEXT: bl log2f792; CHECK-NEXT: vmov s0, r0793; CHECK-NEXT: vcvtt.f16.f32 s21, s0794; CHECK-NEXT: vcvtb.f32.f16 s0, s18795; CHECK-NEXT: vmov r0, s0796; CHECK-NEXT: bl log2f797; CHECK-NEXT: vmov s0, r0798; CHECK-NEXT: vcvtb.f16.f32 s22, s0799; CHECK-NEXT: vcvtt.f32.f16 s0, s18800; CHECK-NEXT: vmov r0, s0801; CHECK-NEXT: bl log2f802; CHECK-NEXT: vmov s0, r0803; CHECK-NEXT: vcvtt.f16.f32 s22, s0804; CHECK-NEXT: vcvtb.f32.f16 s0, s19805; CHECK-NEXT: vmov r0, s0806; CHECK-NEXT: bl log2f807; CHECK-NEXT: vmov s0, r0808; CHECK-NEXT: vcvtb.f16.f32 s23, s0809; CHECK-NEXT: vcvtt.f32.f16 s0, s19810; CHECK-NEXT: vmov r0, s0811; CHECK-NEXT: bl log2f812; CHECK-NEXT: vmov s0, r0813; CHECK-NEXT: vcvtt.f16.f32 s23, s0814; CHECK-NEXT: vmov q0, q5815; CHECK-NEXT: vpop {d8, d9, d10, d11}816; CHECK-NEXT: pop {r7, pc}817entry:818 %0 = call fast <8 x half> @llvm.log2.v8f16(<8 x half> %src)819 ret <8 x half> %0820}821 822define arm_aapcs_vfpcc <2 x double> @log2_float64_t(<2 x double> %src) {823; CHECK-LABEL: log2_float64_t:824; CHECK: @ %bb.0: @ %entry825; CHECK-NEXT: .save {r7, lr}826; CHECK-NEXT: push {r7, lr}827; CHECK-NEXT: .vsave {d8, d9}828; CHECK-NEXT: vpush {d8, d9}829; CHECK-NEXT: vmov q4, q0830; CHECK-NEXT: vmov r0, r1, d9831; CHECK-NEXT: bl log2832; CHECK-NEXT: vmov r2, r3, d8833; CHECK-NEXT: vmov d9, r0, r1834; CHECK-NEXT: mov r0, r2835; CHECK-NEXT: mov r1, r3836; CHECK-NEXT: bl log2837; CHECK-NEXT: vmov d8, r0, r1838; CHECK-NEXT: vmov q0, q4839; CHECK-NEXT: vpop {d8, d9}840; CHECK-NEXT: pop {r7, pc}841entry:842 %0 = call fast <2 x double> @llvm.log2.v2f64(<2 x double> %src)843 ret <2 x double> %0844}845 846define arm_aapcs_vfpcc <4 x float> @log10_float32_t(<4 x float> %src) {847; CHECK-LABEL: log10_float32_t:848; CHECK: @ %bb.0: @ %entry849; CHECK-NEXT: .save {r4, r5, r7, lr}850; CHECK-NEXT: push {r4, r5, r7, lr}851; CHECK-NEXT: .vsave {d8, d9}852; CHECK-NEXT: vpush {d8, d9}853; CHECK-NEXT: vmov q4, q0854; CHECK-NEXT: vmov r0, r4, d9855; CHECK-NEXT: bl log10f856; CHECK-NEXT: mov r5, r0857; CHECK-NEXT: mov r0, r4858; CHECK-NEXT: bl log10f859; CHECK-NEXT: vmov r4, r1, d8860; CHECK-NEXT: vmov s19, r0861; CHECK-NEXT: vmov s18, r5862; CHECK-NEXT: mov r0, r1863; CHECK-NEXT: bl log10f864; CHECK-NEXT: vmov s17, r0865; CHECK-NEXT: mov r0, r4866; CHECK-NEXT: bl log10f867; CHECK-NEXT: vmov s16, r0868; CHECK-NEXT: vmov q0, q4869; CHECK-NEXT: vpop {d8, d9}870; CHECK-NEXT: pop {r4, r5, r7, pc}871entry:872 %0 = call fast <4 x float> @llvm.log10.v4f32(<4 x float> %src)873 ret <4 x float> %0874}875 876define arm_aapcs_vfpcc <8 x half> @log10_float16_t(<8 x half> %src) {877; CHECK-LABEL: log10_float16_t:878; CHECK: @ %bb.0: @ %entry879; CHECK-NEXT: .save {r7, lr}880; CHECK-NEXT: push {r7, lr}881; CHECK-NEXT: .vsave {d8, d9, d10, d11}882; CHECK-NEXT: vpush {d8, d9, d10, d11}883; CHECK-NEXT: vmov q4, q0884; CHECK-NEXT: vcvtb.f32.f16 s0, s16885; CHECK-NEXT: vmov r0, s0886; CHECK-NEXT: bl log10f887; CHECK-NEXT: vcvtt.f32.f16 s0, s16888; CHECK-NEXT: vmov s16, r0889; CHECK-NEXT: vmov r1, s0890; CHECK-NEXT: mov r0, r1891; CHECK-NEXT: bl log10f892; CHECK-NEXT: vmov s0, r0893; CHECK-NEXT: vcvtb.f16.f32 s20, s16894; CHECK-NEXT: vcvtt.f16.f32 s20, s0895; CHECK-NEXT: vcvtb.f32.f16 s0, s17896; CHECK-NEXT: vmov r0, s0897; CHECK-NEXT: bl log10f898; CHECK-NEXT: vmov s0, r0899; CHECK-NEXT: vcvtb.f16.f32 s21, s0900; CHECK-NEXT: vcvtt.f32.f16 s0, s17901; CHECK-NEXT: vmov r0, s0902; CHECK-NEXT: bl log10f903; CHECK-NEXT: vmov s0, r0904; CHECK-NEXT: vcvtt.f16.f32 s21, s0905; CHECK-NEXT: vcvtb.f32.f16 s0, s18906; CHECK-NEXT: vmov r0, s0907; CHECK-NEXT: bl log10f908; CHECK-NEXT: vmov s0, r0909; CHECK-NEXT: vcvtb.f16.f32 s22, s0910; CHECK-NEXT: vcvtt.f32.f16 s0, s18911; CHECK-NEXT: vmov r0, s0912; CHECK-NEXT: bl log10f913; CHECK-NEXT: vmov s0, r0914; CHECK-NEXT: vcvtt.f16.f32 s22, s0915; CHECK-NEXT: vcvtb.f32.f16 s0, s19916; CHECK-NEXT: vmov r0, s0917; CHECK-NEXT: bl log10f918; CHECK-NEXT: vmov s0, r0919; CHECK-NEXT: vcvtb.f16.f32 s23, s0920; CHECK-NEXT: vcvtt.f32.f16 s0, s19921; CHECK-NEXT: vmov r0, s0922; CHECK-NEXT: bl log10f923; CHECK-NEXT: vmov s0, r0924; CHECK-NEXT: vcvtt.f16.f32 s23, s0925; CHECK-NEXT: vmov q0, q5926; CHECK-NEXT: vpop {d8, d9, d10, d11}927; CHECK-NEXT: pop {r7, pc}928entry:929 %0 = call fast <8 x half> @llvm.log10.v8f16(<8 x half> %src)930 ret <8 x half> %0931}932 933define arm_aapcs_vfpcc <2 x double> @log10_float64_t(<2 x double> %src) {934; CHECK-LABEL: log10_float64_t:935; CHECK: @ %bb.0: @ %entry936; CHECK-NEXT: .save {r7, lr}937; CHECK-NEXT: push {r7, lr}938; CHECK-NEXT: .vsave {d8, d9}939; CHECK-NEXT: vpush {d8, d9}940; CHECK-NEXT: vmov q4, q0941; CHECK-NEXT: vmov r0, r1, d9942; CHECK-NEXT: bl log10943; CHECK-NEXT: vmov r2, r3, d8944; CHECK-NEXT: vmov d9, r0, r1945; CHECK-NEXT: mov r0, r2946; CHECK-NEXT: mov r1, r3947; CHECK-NEXT: bl log10948; CHECK-NEXT: vmov d8, r0, r1949; CHECK-NEXT: vmov q0, q4950; CHECK-NEXT: vpop {d8, d9}951; CHECK-NEXT: pop {r7, pc}952entry:953 %0 = call fast <2 x double> @llvm.log10.v2f64(<2 x double> %src)954 ret <2 x double> %0955}956 957define arm_aapcs_vfpcc <4 x float> @pow_float32_t(<4 x float> %src1, <4 x float> %src2) {958; CHECK-LABEL: pow_float32_t:959; CHECK: @ %bb.0: @ %entry960; CHECK-NEXT: .save {r4, r5, r6, lr}961; CHECK-NEXT: push {r4, r5, r6, lr}962; CHECK-NEXT: .vsave {d8, d9, d10, d11}963; CHECK-NEXT: vpush {d8, d9, d10, d11}964; CHECK-NEXT: vmov q4, q1965; CHECK-NEXT: vmov q5, q0966; CHECK-NEXT: vmov r0, r4, d11967; CHECK-NEXT: vmov r1, r5, d9968; CHECK-NEXT: bl powf969; CHECK-NEXT: mov r6, r0970; CHECK-NEXT: mov r0, r4971; CHECK-NEXT: mov r1, r5972; CHECK-NEXT: bl powf973; CHECK-NEXT: vmov r4, r2, d10974; CHECK-NEXT: vmov r5, r1, d8975; CHECK-NEXT: vmov s19, r0976; CHECK-NEXT: vmov s18, r6977; CHECK-NEXT: mov r0, r2978; CHECK-NEXT: bl powf979; CHECK-NEXT: vmov s17, r0980; CHECK-NEXT: mov r0, r4981; CHECK-NEXT: mov r1, r5982; CHECK-NEXT: bl powf983; CHECK-NEXT: vmov s16, r0984; CHECK-NEXT: vmov q0, q4985; CHECK-NEXT: vpop {d8, d9, d10, d11}986; CHECK-NEXT: pop {r4, r5, r6, pc}987entry:988 %0 = call fast <4 x float> @llvm.pow.v4f32(<4 x float> %src1, <4 x float> %src2)989 ret <4 x float> %0990}991 992define arm_aapcs_vfpcc <8 x half> @pow_float16_t(<8 x half> %src1, <8 x half> %src2) {993; CHECK-LABEL: pow_float16_t:994; CHECK: @ %bb.0: @ %entry995; CHECK-NEXT: .save {r7, lr}996; CHECK-NEXT: push {r7, lr}997; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}998; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}999; CHECK-NEXT: vmov q5, q01000; CHECK-NEXT: vmov q4, q11001; CHECK-NEXT: vcvtb.f32.f16 s0, s201002; CHECK-NEXT: vmov r0, s01003; CHECK-NEXT: vcvtb.f32.f16 s0, s161004; CHECK-NEXT: vmov r1, s01005; CHECK-NEXT: bl powf1006; CHECK-NEXT: vcvtt.f32.f16 s0, s201007; CHECK-NEXT: vmov r2, s01008; CHECK-NEXT: vcvtt.f32.f16 s0, s161009; CHECK-NEXT: vmov r1, s01010; CHECK-NEXT: vmov s16, r01011; CHECK-NEXT: mov r0, r21012; CHECK-NEXT: bl powf1013; CHECK-NEXT: vmov s0, r01014; CHECK-NEXT: vcvtb.f16.f32 s24, s161015; CHECK-NEXT: vcvtt.f16.f32 s24, s01016; CHECK-NEXT: vcvtb.f32.f16 s0, s211017; CHECK-NEXT: vmov r0, s01018; CHECK-NEXT: vcvtb.f32.f16 s0, s171019; CHECK-NEXT: vmov r1, s01020; CHECK-NEXT: bl powf1021; CHECK-NEXT: vmov s0, r01022; CHECK-NEXT: vcvtb.f16.f32 s25, s01023; CHECK-NEXT: vcvtt.f32.f16 s0, s211024; CHECK-NEXT: vmov r0, s01025; CHECK-NEXT: vcvtt.f32.f16 s0, s171026; CHECK-NEXT: vmov r1, s01027; CHECK-NEXT: bl powf1028; CHECK-NEXT: vmov s0, r01029; CHECK-NEXT: vcvtt.f16.f32 s25, s01030; CHECK-NEXT: vcvtb.f32.f16 s0, s221031; CHECK-NEXT: vmov r0, s01032; CHECK-NEXT: vcvtb.f32.f16 s0, s181033; CHECK-NEXT: vmov r1, s01034; CHECK-NEXT: bl powf1035; CHECK-NEXT: vmov s0, r01036; CHECK-NEXT: vcvtb.f16.f32 s26, s01037; CHECK-NEXT: vcvtt.f32.f16 s0, s221038; CHECK-NEXT: vmov r0, s01039; CHECK-NEXT: vcvtt.f32.f16 s0, s181040; CHECK-NEXT: vmov r1, s01041; CHECK-NEXT: bl powf1042; CHECK-NEXT: vmov s0, r01043; CHECK-NEXT: vcvtt.f16.f32 s26, s01044; CHECK-NEXT: vcvtb.f32.f16 s0, s231045; CHECK-NEXT: vmov r0, s01046; CHECK-NEXT: vcvtb.f32.f16 s0, s191047; CHECK-NEXT: vmov r1, s01048; CHECK-NEXT: bl powf1049; CHECK-NEXT: vmov s0, r01050; CHECK-NEXT: vcvtb.f16.f32 s27, s01051; CHECK-NEXT: vcvtt.f32.f16 s0, s231052; CHECK-NEXT: vmov r0, s01053; CHECK-NEXT: vcvtt.f32.f16 s0, s191054; CHECK-NEXT: vmov r1, s01055; CHECK-NEXT: bl powf1056; CHECK-NEXT: vmov s0, r01057; CHECK-NEXT: vcvtt.f16.f32 s27, s01058; CHECK-NEXT: vmov q0, q61059; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}1060; CHECK-NEXT: pop {r7, pc}1061entry:1062 %0 = call fast <8 x half> @llvm.pow.v8f16(<8 x half> %src1, <8 x half> %src2)1063 ret <8 x half> %01064}1065 1066define arm_aapcs_vfpcc <2 x double> @pow_float64_t(<2 x double> %src1, <2 x double> %src2) {1067; CHECK-LABEL: pow_float64_t:1068; CHECK: @ %bb.0: @ %entry1069; CHECK-NEXT: .save {r7, lr}1070; CHECK-NEXT: push {r7, lr}1071; CHECK-NEXT: .vsave {d8, d9, d10, d11}1072; CHECK-NEXT: vpush {d8, d9, d10, d11}1073; CHECK-NEXT: vmov q4, q11074; CHECK-NEXT: vmov q5, q01075; CHECK-NEXT: vmov r0, r1, d111076; CHECK-NEXT: vmov r2, r3, d91077; CHECK-NEXT: bl pow1078; CHECK-NEXT: vmov lr, r12, d101079; CHECK-NEXT: vmov r2, r3, d81080; CHECK-NEXT: vmov d9, r0, r11081; CHECK-NEXT: mov r0, lr1082; CHECK-NEXT: mov r1, r121083; CHECK-NEXT: bl pow1084; CHECK-NEXT: vmov d8, r0, r11085; CHECK-NEXT: vmov q0, q41086; CHECK-NEXT: vpop {d8, d9, d10, d11}1087; CHECK-NEXT: pop {r7, pc}1088entry:1089 %0 = call fast <2 x double> @llvm.pow.v2f64(<2 x double> %src1, <2 x double> %src2)1090 ret <2 x double> %01091}1092 1093define arm_aapcs_vfpcc <4 x float> @copysign_float32_t(<4 x float> %src1, <4 x float> %src2) {1094; FULLFP16-LABEL: copysign_float32_t:1095; FULLFP16: @ %bb.0: @ %entry1096; FULLFP16-NEXT: .save {r4, r5, r7, lr}1097; FULLFP16-NEXT: push {r4, r5, r7, lr}1098; FULLFP16-NEXT: vmov r12, r1, d21099; FULLFP16-NEXT: vmov r2, lr, d31100; FULLFP16-NEXT: vmov r3, r0, d01101; FULLFP16-NEXT: vmov r4, r5, d11102; FULLFP16-NEXT: lsrs r1, r1, #311103; FULLFP16-NEXT: bfi r0, r1, #31, #11104; FULLFP16-NEXT: lsrs r1, r2, #311105; FULLFP16-NEXT: bfi r4, r1, #31, #11106; FULLFP16-NEXT: lsr.w r1, lr, #311107; FULLFP16-NEXT: bfi r5, r1, #31, #11108; FULLFP16-NEXT: lsr.w r1, r12, #311109; FULLFP16-NEXT: bfi r3, r1, #31, #11110; FULLFP16-NEXT: vmov s2, r41111; FULLFP16-NEXT: vmov s3, r51112; FULLFP16-NEXT: vmov s1, r01113; FULLFP16-NEXT: vmov s0, r31114; FULLFP16-NEXT: pop {r4, r5, r7, pc}1115;1116; MVEFP-LABEL: copysign_float32_t:1117; MVEFP: @ %bb.0: @ %entry1118; MVEFP-NEXT: vmov.i32 q2, #0x800000001119; MVEFP-NEXT: vbic.i32 q0, #0x800000001120; MVEFP-NEXT: vand q1, q1, q21121; MVEFP-NEXT: vorr q0, q0, q11122; MVEFP-NEXT: bx lr1123entry:1124 %0 = call fast <4 x float> @llvm.copysign.v4f32(<4 x float> %src1, <4 x float> %src2)1125 ret <4 x float> %01126}1127 1128define arm_aapcs_vfpcc <8 x half> @copysign_float16_t(<8 x half> %src1, <8 x half> %src2) {1129; FULLFP16-LABEL: copysign_float16_t:1130; FULLFP16: @ %bb.0: @ %entry1131; FULLFP16-NEXT: .pad #321132; FULLFP16-NEXT: sub sp, #321133; FULLFP16-NEXT: vmovx.f16 s8, s41134; FULLFP16-NEXT: vstr.16 s8, [sp, #24]1135; FULLFP16-NEXT: vstr.16 s4, [sp, #28]1136; FULLFP16-NEXT: vmovx.f16 s4, s51137; FULLFP16-NEXT: vstr.16 s4, [sp, #16]1138; FULLFP16-NEXT: vmovx.f16 s4, s61139; FULLFP16-NEXT: vstr.16 s5, [sp, #20]1140; FULLFP16-NEXT: vstr.16 s4, [sp, #8]1141; FULLFP16-NEXT: vmovx.f16 s4, s71142; FULLFP16-NEXT: vstr.16 s6, [sp, #12]1143; FULLFP16-NEXT: vstr.16 s4, [sp]1144; FULLFP16-NEXT: vstr.16 s7, [sp, #4]1145; FULLFP16-NEXT: ldrb.w r0, [sp, #25]1146; FULLFP16-NEXT: vmovx.f16 s4, s01147; FULLFP16-NEXT: vabs.f16 s4, s41148; FULLFP16-NEXT: vneg.f16 s6, s41149; FULLFP16-NEXT: lsls r0, r0, #241150; FULLFP16-NEXT: it pl1151; FULLFP16-NEXT: vmovpl.f32 s6, s41152; FULLFP16-NEXT: ldrb.w r0, [sp, #29]1153; FULLFP16-NEXT: vabs.f16 s4, s01154; FULLFP16-NEXT: vneg.f16 s0, s41155; FULLFP16-NEXT: lsls r0, r0, #241156; FULLFP16-NEXT: it pl1157; FULLFP16-NEXT: vmovpl.f32 s0, s41158; FULLFP16-NEXT: ldrb.w r0, [sp, #17]1159; FULLFP16-NEXT: vmovx.f16 s4, s11160; FULLFP16-NEXT: vabs.f16 s4, s41161; FULLFP16-NEXT: vins.f16 s0, s61162; FULLFP16-NEXT: vneg.f16 s6, s41163; FULLFP16-NEXT: lsls r0, r0, #241164; FULLFP16-NEXT: it pl1165; FULLFP16-NEXT: vmovpl.f32 s6, s41166; FULLFP16-NEXT: ldrb.w r0, [sp, #21]1167; FULLFP16-NEXT: vabs.f16 s4, s11168; FULLFP16-NEXT: vneg.f16 s1, s41169; FULLFP16-NEXT: lsls r0, r0, #241170; FULLFP16-NEXT: it pl1171; FULLFP16-NEXT: vmovpl.f32 s1, s41172; FULLFP16-NEXT: ldrb.w r0, [sp, #9]1173; FULLFP16-NEXT: vmovx.f16 s4, s21174; FULLFP16-NEXT: vabs.f16 s4, s41175; FULLFP16-NEXT: vins.f16 s1, s61176; FULLFP16-NEXT: vneg.f16 s6, s41177; FULLFP16-NEXT: lsls r0, r0, #241178; FULLFP16-NEXT: it pl1179; FULLFP16-NEXT: vmovpl.f32 s6, s41180; FULLFP16-NEXT: ldrb.w r0, [sp, #13]1181; FULLFP16-NEXT: vabs.f16 s4, s21182; FULLFP16-NEXT: vneg.f16 s2, s41183; FULLFP16-NEXT: lsls r0, r0, #241184; FULLFP16-NEXT: it pl1185; FULLFP16-NEXT: vmovpl.f32 s2, s41186; FULLFP16-NEXT: ldrb.w r0, [sp, #1]1187; FULLFP16-NEXT: vmovx.f16 s4, s31188; FULLFP16-NEXT: vabs.f16 s4, s41189; FULLFP16-NEXT: vins.f16 s2, s61190; FULLFP16-NEXT: vneg.f16 s6, s41191; FULLFP16-NEXT: lsls r0, r0, #241192; FULLFP16-NEXT: it pl1193; FULLFP16-NEXT: vmovpl.f32 s6, s41194; FULLFP16-NEXT: ldrb.w r0, [sp, #5]1195; FULLFP16-NEXT: vabs.f16 s4, s31196; FULLFP16-NEXT: vneg.f16 s3, s41197; FULLFP16-NEXT: lsls r0, r0, #241198; FULLFP16-NEXT: it pl1199; FULLFP16-NEXT: vmovpl.f32 s3, s41200; FULLFP16-NEXT: vins.f16 s3, s61201; FULLFP16-NEXT: add sp, #321202; FULLFP16-NEXT: bx lr1203;1204; MVEFP-LABEL: copysign_float16_t:1205; MVEFP: @ %bb.0: @ %entry1206; MVEFP-NEXT: vmov.i16 q2, #0x80001207; MVEFP-NEXT: vbic.i16 q0, #0x80001208; MVEFP-NEXT: vand q1, q1, q21209; MVEFP-NEXT: vorr q0, q0, q11210; MVEFP-NEXT: bx lr1211entry:1212 %0 = call fast <8 x half> @llvm.copysign.v8f16(<8 x half> %src1, <8 x half> %src2)1213 ret <8 x half> %01214}1215 1216define arm_aapcs_vfpcc <2 x double> @copysign_float64_t(<2 x double> %src1, <2 x double> %src2) {1217; CHECK-LABEL: copysign_float64_t:1218; CHECK: @ %bb.0: @ %entry1219; CHECK-NEXT: .save {r7, lr}1220; CHECK-NEXT: push {r7, lr}1221; CHECK-NEXT: vmov r0, r1, d31222; CHECK-NEXT: vmov r0, lr, d21223; CHECK-NEXT: vmov r0, r3, d11224; CHECK-NEXT: vmov r12, r2, d01225; CHECK-NEXT: lsrs r1, r1, #311226; CHECK-NEXT: bfi r3, r1, #31, #11227; CHECK-NEXT: lsr.w r1, lr, #311228; CHECK-NEXT: bfi r2, r1, #31, #11229; CHECK-NEXT: vmov d1, r0, r31230; CHECK-NEXT: vmov d0, r12, r21231; CHECK-NEXT: pop {r7, pc}1232entry:1233 %0 = call fast <2 x double> @llvm.copysign.v2f64(<2 x double> %src1, <2 x double> %src2)1234 ret <2 x double> %01235}1236 1237declare <4 x float> @llvm.sqrt.v4f32(<4 x float>)1238declare <4 x float> @llvm.cos.v4f32(<4 x float>)1239declare <4 x float> @llvm.sin.v4f32(<4 x float>)1240declare <4 x float> @llvm.exp.v4f32(<4 x float>)1241declare <4 x float> @llvm.exp2.v4f32(<4 x float>)1242declare <4 x float> @llvm.log.v4f32(<4 x float>)1243declare <4 x float> @llvm.log2.v4f32(<4 x float>)1244declare <4 x float> @llvm.log10.v4f32(<4 x float>)1245declare <4 x float> @llvm.pow.v4f32(<4 x float>, <4 x float>)1246declare <4 x float> @llvm.copysign.v4f32(<4 x float>, <4 x float>)1247declare <8 x half> @llvm.sqrt.v8f16(<8 x half>)1248declare <8 x half> @llvm.cos.v8f16(<8 x half>)1249declare <8 x half> @llvm.sin.v8f16(<8 x half>)1250declare <8 x half> @llvm.exp.v8f16(<8 x half>)1251declare <8 x half> @llvm.exp2.v8f16(<8 x half>)1252declare <8 x half> @llvm.log.v8f16(<8 x half>)1253declare <8 x half> @llvm.log2.v8f16(<8 x half>)1254declare <8 x half> @llvm.log10.v8f16(<8 x half>)1255declare <8 x half> @llvm.pow.v8f16(<8 x half>, <8 x half>)1256declare <8 x half> @llvm.copysign.v8f16(<8 x half>, <8 x half>)1257declare <2 x double> @llvm.sqrt.v2f64(<2 x double>)1258declare <2 x double> @llvm.cos.v2f64(<2 x double>)1259declare <2 x double> @llvm.sin.v2f64(<2 x double>)1260declare <2 x double> @llvm.exp.v2f64(<2 x double>)1261declare <2 x double> @llvm.exp2.v2f64(<2 x double>)1262declare <2 x double> @llvm.log.v2f64(<2 x double>)1263declare <2 x double> @llvm.log2.v2f64(<2 x double>)1264declare <2 x double> @llvm.log10.v2f64(<2 x double>)1265declare <2 x double> @llvm.pow.v2f64(<2 x double>, <2 x double>)1266declare <2 x double> @llvm.copysign.v2f64(<2 x double>, <2 x double>)1267