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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE3; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP4 5define arm_aapcs_vfpcc <8 x half> @fneg_float16_t(<8 x half> %src) {6; CHECK-MVE-LABEL: fneg_float16_t:7; CHECK-MVE: @ %bb.0: @ %entry8; CHECK-MVE-NEXT: vmovx.f16 s4, s09; CHECK-MVE-NEXT: vneg.f16 s0, s010; CHECK-MVE-NEXT: vneg.f16 s4, s411; CHECK-MVE-NEXT: vins.f16 s0, s412; CHECK-MVE-NEXT: vmovx.f16 s4, s113; CHECK-MVE-NEXT: vneg.f16 s4, s414; CHECK-MVE-NEXT: vneg.f16 s1, s115; CHECK-MVE-NEXT: vins.f16 s1, s416; CHECK-MVE-NEXT: vmovx.f16 s4, s217; CHECK-MVE-NEXT: vneg.f16 s4, s418; CHECK-MVE-NEXT: vneg.f16 s2, s219; CHECK-MVE-NEXT: vins.f16 s2, s420; CHECK-MVE-NEXT: vmovx.f16 s4, s321; CHECK-MVE-NEXT: vneg.f16 s4, s422; CHECK-MVE-NEXT: vneg.f16 s3, s323; CHECK-MVE-NEXT: vins.f16 s3, s424; CHECK-MVE-NEXT: bx lr25;26; CHECK-MVEFP-LABEL: fneg_float16_t:27; CHECK-MVEFP: @ %bb.0: @ %entry28; CHECK-MVEFP-NEXT: vneg.f16 q0, q029; CHECK-MVEFP-NEXT: bx lr30entry:31 %0 = fsub nnan ninf nsz <8 x half> <half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0>, %src32 ret <8 x half> %033}34 35define arm_aapcs_vfpcc <4 x float> @fneg_float32_t(<4 x float> %src) {36; CHECK-MVE-LABEL: fneg_float32_t:37; CHECK-MVE: @ %bb.0: @ %entry38; CHECK-MVE-NEXT: vneg.f32 s3, s339; CHECK-MVE-NEXT: vneg.f32 s2, s240; CHECK-MVE-NEXT: vneg.f32 s1, s141; CHECK-MVE-NEXT: vneg.f32 s0, s042; CHECK-MVE-NEXT: bx lr43;44; CHECK-MVEFP-LABEL: fneg_float32_t:45; CHECK-MVEFP: @ %bb.0: @ %entry46; CHECK-MVEFP-NEXT: vneg.f32 q0, q047; CHECK-MVEFP-NEXT: bx lr48entry:49 %0 = fsub nnan ninf nsz <4 x float> <float 0.0e0, float 0.0e0, float 0.0e0, float 0.0e0>, %src50 ret <4 x float> %051}52 53define arm_aapcs_vfpcc <2 x double> @fneg_float64_t(<2 x double> %src) {54; CHECK-LABEL: fneg_float64_t:55; CHECK: @ %bb.0: @ %entry56; CHECK-NEXT: .pad #1657; CHECK-NEXT: sub sp, #1658; CHECK-NEXT: vstr d1, [sp]59; CHECK-NEXT: ldrb.w r0, [sp, #7]60; CHECK-NEXT: vstr d0, [sp, #8]61; CHECK-NEXT: ldrb.w r1, [sp, #15]62; CHECK-NEXT: eor r0, r0, #12863; CHECK-NEXT: strb.w r0, [sp, #7]64; CHECK-NEXT: vldr d1, [sp]65; CHECK-NEXT: eor r0, r1, #12866; CHECK-NEXT: strb.w r0, [sp, #15]67; CHECK-NEXT: vldr d0, [sp, #8]68; CHECK-NEXT: add sp, #1669; CHECK-NEXT: bx lr70entry:71 %0 = fsub nnan ninf nsz <2 x double> <double 0.0e0, double 0.0e0>, %src72 ret <2 x double> %073}74 75define arm_aapcs_vfpcc <8 x half> @fabs_float16_t(<8 x half> %src) {76; CHECK-MVE-LABEL: fabs_float16_t:77; CHECK-MVE: @ %bb.0: @ %entry78; CHECK-MVE-NEXT: vmovx.f16 s4, s079; CHECK-MVE-NEXT: vabs.f16 s0, s080; CHECK-MVE-NEXT: vabs.f16 s4, s481; CHECK-MVE-NEXT: vins.f16 s0, s482; CHECK-MVE-NEXT: vmovx.f16 s4, s183; CHECK-MVE-NEXT: vabs.f16 s4, s484; CHECK-MVE-NEXT: vabs.f16 s1, s185; CHECK-MVE-NEXT: vins.f16 s1, s486; CHECK-MVE-NEXT: vmovx.f16 s4, s287; CHECK-MVE-NEXT: vabs.f16 s4, s488; CHECK-MVE-NEXT: vabs.f16 s2, s289; CHECK-MVE-NEXT: vins.f16 s2, s490; CHECK-MVE-NEXT: vmovx.f16 s4, s391; CHECK-MVE-NEXT: vabs.f16 s4, s492; CHECK-MVE-NEXT: vabs.f16 s3, s393; CHECK-MVE-NEXT: vins.f16 s3, s494; CHECK-MVE-NEXT: bx lr95;96; CHECK-MVEFP-LABEL: fabs_float16_t:97; CHECK-MVEFP: @ %bb.0: @ %entry98; CHECK-MVEFP-NEXT: vabs.f16 q0, q099; CHECK-MVEFP-NEXT: bx lr100entry:101 %0 = call nnan ninf nsz <8 x half> @llvm.fabs.v8f16(<8 x half> %src)102 ret <8 x half> %0103}104 105define arm_aapcs_vfpcc <4 x float> @fabs_float32_t(<4 x float> %src) {106; CHECK-MVE-LABEL: fabs_float32_t:107; CHECK-MVE: @ %bb.0: @ %entry108; CHECK-MVE-NEXT: vabs.f32 s3, s3109; CHECK-MVE-NEXT: vabs.f32 s2, s2110; CHECK-MVE-NEXT: vabs.f32 s1, s1111; CHECK-MVE-NEXT: vabs.f32 s0, s0112; CHECK-MVE-NEXT: bx lr113;114; CHECK-MVEFP-LABEL: fabs_float32_t:115; CHECK-MVEFP: @ %bb.0: @ %entry116; CHECK-MVEFP-NEXT: vabs.f32 q0, q0117; CHECK-MVEFP-NEXT: bx lr118entry:119 %0 = call nnan ninf nsz <4 x float> @llvm.fabs.v4f32(<4 x float> %src)120 ret <4 x float> %0121}122 123define arm_aapcs_vfpcc <2 x double> @fabs_float64_t(<2 x double> %src) {124; CHECK-LABEL: fabs_float64_t:125; CHECK: @ %bb.0: @ %entry126; CHECK-NEXT: vldr d2, .LCPI5_0127; CHECK-NEXT: vmov r12, r3, d0128; CHECK-NEXT: vmov r0, r1, d2129; CHECK-NEXT: vmov r0, r2, d1130; CHECK-NEXT: lsrs r1, r1, #31131; CHECK-NEXT: bfi r2, r1, #31, #1132; CHECK-NEXT: bfi r3, r1, #31, #1133; CHECK-NEXT: vmov d1, r0, r2134; CHECK-NEXT: vmov d0, r12, r3135; CHECK-NEXT: bx lr136; CHECK-NEXT: .p2align 3137; CHECK-NEXT: @ %bb.1:138; CHECK-NEXT: .LCPI5_0:139; CHECK-NEXT: .long 0 @ double 0140; CHECK-NEXT: .long 0141entry:142 %0 = call nnan ninf nsz <2 x double> @llvm.fabs.v2f64(<2 x double> %src)143 ret <2 x double> %0144}145 146declare <4 x float> @llvm.fabs.v4f32(<4 x float>)147declare <8 x half> @llvm.fabs.v8f16(<8 x half>)148declare <2 x double> @llvm.fabs.v2f64(<2 x double>)149 150