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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp | FileCheck %s3 4; i32 saturate5 6define arm_aapcs_vfpcc <2 x i32> @stest_f64i32(<2 x double> %x) {7; CHECK-LABEL: stest_f64i32:8; CHECK: @ %bb.0: @ %entry9; CHECK-NEXT: .save {r4, r5, r7, lr}10; CHECK-NEXT: push {r4, r5, r7, lr}11; CHECK-NEXT: .vsave {d8, d9}12; CHECK-NEXT: vpush {d8, d9}13; CHECK-NEXT: vmov q4, q014; CHECK-NEXT: vmov r0, r1, d815; CHECK-NEXT: bl __aeabi_d2lz16; CHECK-NEXT: mov r4, r017; CHECK-NEXT: mov r5, r118; CHECK-NEXT: vmov r0, r1, d919; CHECK-NEXT: bl __aeabi_d2lz20; CHECK-NEXT: adr r3, .LCPI0_021; CHECK-NEXT: mvn r12, #-214748364822; CHECK-NEXT: vldrw.u32 q0, [r3]23; CHECK-NEXT: subs.w r3, r4, r1224; CHECK-NEXT: sbcs r3, r5, #025; CHECK-NEXT: vmov q1[2], q1[0], r4, r026; CHECK-NEXT: csetm r3, lt27; CHECK-NEXT: subs.w r0, r0, r1228; CHECK-NEXT: sbcs r0, r1, #029; CHECK-NEXT: vmov q1[3], q1[1], r5, r130; CHECK-NEXT: mov.w r5, #031; CHECK-NEXT: csetm r0, lt32; CHECK-NEXT: bfi r5, r3, #0, #833; CHECK-NEXT: mov.w r12, #-134; CHECK-NEXT: bfi r5, r0, #8, #835; CHECK-NEXT: movs r2, #036; CHECK-NEXT: vmsr p0, r537; CHECK-NEXT: adr r4, .LCPI0_138; CHECK-NEXT: vpsel q0, q1, q039; CHECK-NEXT: vldrw.u32 q1, [r4]40; CHECK-NEXT: vmov r0, r1, d041; CHECK-NEXT: vmov r3, r5, d142; CHECK-NEXT: rsbs.w r0, r0, #-214748364843; CHECK-NEXT: sbcs.w r0, r12, r144; CHECK-NEXT: csetm r0, lt45; CHECK-NEXT: bfi r2, r0, #0, #846; CHECK-NEXT: rsbs.w r0, r3, #-214748364847; CHECK-NEXT: sbcs.w r0, r12, r548; CHECK-NEXT: csetm r0, lt49; CHECK-NEXT: bfi r2, r0, #8, #850; CHECK-NEXT: vmsr p0, r251; CHECK-NEXT: vpsel q0, q0, q152; CHECK-NEXT: vpop {d8, d9}53; CHECK-NEXT: pop {r4, r5, r7, pc}54; CHECK-NEXT: .p2align 455; CHECK-NEXT: @ %bb.1:56; CHECK-NEXT: .LCPI0_0:57; CHECK-NEXT: .long 2147483647 @ 0x7fffffff58; CHECK-NEXT: .long 0 @ 0x059; CHECK-NEXT: .long 2147483647 @ 0x7fffffff60; CHECK-NEXT: .long 0 @ 0x061; CHECK-NEXT: .LCPI0_1:62; CHECK-NEXT: .long 2147483648 @ 0x8000000063; CHECK-NEXT: .long 4294967295 @ 0xffffffff64; CHECK-NEXT: .long 2147483648 @ 0x8000000065; CHECK-NEXT: .long 4294967295 @ 0xffffffff66entry:67 %conv = fptosi <2 x double> %x to <2 x i64>68 %0 = icmp slt <2 x i64> %conv, <i64 2147483647, i64 2147483647>69 %spec.store.select = select <2 x i1> %0, <2 x i64> %conv, <2 x i64> <i64 2147483647, i64 2147483647>70 %1 = icmp sgt <2 x i64> %spec.store.select, <i64 -2147483648, i64 -2147483648>71 %spec.store.select7 = select <2 x i1> %1, <2 x i64> %spec.store.select, <2 x i64> <i64 -2147483648, i64 -2147483648>72 %conv6 = trunc <2 x i64> %spec.store.select7 to <2 x i32>73 ret <2 x i32> %conv674}75 76define arm_aapcs_vfpcc <2 x i32> @utest_f64i32(<2 x double> %x) {77; CHECK-LABEL: utest_f64i32:78; CHECK: @ %bb.0: @ %entry79; CHECK-NEXT: .save {r4, r5, r7, lr}80; CHECK-NEXT: push {r4, r5, r7, lr}81; CHECK-NEXT: .vsave {d8, d9}82; CHECK-NEXT: vpush {d8, d9}83; CHECK-NEXT: vmov q4, q084; CHECK-NEXT: vmov r0, r1, d885; CHECK-NEXT: bl __aeabi_d2ulz86; CHECK-NEXT: mov r4, r087; CHECK-NEXT: mov r5, r188; CHECK-NEXT: vmov r0, r1, d989; CHECK-NEXT: bl __aeabi_d2ulz90; CHECK-NEXT: subs.w r3, r4, #-191; CHECK-NEXT: vmov q1[2], q1[0], r4, r092; CHECK-NEXT: sbcs r3, r5, #093; CHECK-NEXT: mov.w r2, #094; CHECK-NEXT: csetm r3, lo95; CHECK-NEXT: subs.w r0, r0, #-196; CHECK-NEXT: sbcs r0, r1, #097; CHECK-NEXT: bfi r2, r3, #0, #898; CHECK-NEXT: csetm r0, lo99; CHECK-NEXT: vmov.i64 q0, #0xffffffff100; CHECK-NEXT: bfi r2, r0, #8, #8101; CHECK-NEXT: vmov q1[3], q1[1], r5, r1102; CHECK-NEXT: vmsr p0, r2103; CHECK-NEXT: vpsel q0, q1, q0104; CHECK-NEXT: vpop {d8, d9}105; CHECK-NEXT: pop {r4, r5, r7, pc}106entry:107 %conv = fptoui <2 x double> %x to <2 x i64>108 %0 = icmp ult <2 x i64> %conv, <i64 4294967295, i64 4294967295>109 %spec.store.select = select <2 x i1> %0, <2 x i64> %conv, <2 x i64> <i64 4294967295, i64 4294967295>110 %conv6 = trunc <2 x i64> %spec.store.select to <2 x i32>111 ret <2 x i32> %conv6112}113 114define arm_aapcs_vfpcc <2 x i32> @ustest_f64i32(<2 x double> %x) {115; CHECK-LABEL: ustest_f64i32:116; CHECK: @ %bb.0: @ %entry117; CHECK-NEXT: .save {r4, r5, r7, lr}118; CHECK-NEXT: push {r4, r5, r7, lr}119; CHECK-NEXT: .vsave {d8, d9}120; CHECK-NEXT: vpush {d8, d9}121; CHECK-NEXT: vmov q4, q0122; CHECK-NEXT: vmov r0, r1, d8123; CHECK-NEXT: bl __aeabi_d2lz124; CHECK-NEXT: mov r4, r0125; CHECK-NEXT: mov r5, r1126; CHECK-NEXT: vmov r0, r1, d9127; CHECK-NEXT: bl __aeabi_d2lz128; CHECK-NEXT: subs.w r3, r4, #-1129; CHECK-NEXT: vmov q1[2], q1[0], r4, r0130; CHECK-NEXT: sbcs r3, r5, #0131; CHECK-NEXT: vmov q1[3], q1[1], r5, r1132; CHECK-NEXT: csetm r3, lt133; CHECK-NEXT: subs.w r0, r0, #-1134; CHECK-NEXT: mov.w r5, #0135; CHECK-NEXT: sbcs r0, r1, #0136; CHECK-NEXT: bfi r5, r3, #0, #8137; CHECK-NEXT: csetm r0, lt138; CHECK-NEXT: bfi r5, r0, #8, #8139; CHECK-NEXT: vmov.i64 q0, #0xffffffff140; CHECK-NEXT: vmsr p0, r5141; CHECK-NEXT: movs r2, #0142; CHECK-NEXT: vpsel q0, q1, q0143; CHECK-NEXT: vmov.i32 q1, #0x0144; CHECK-NEXT: vmov r0, r1, d0145; CHECK-NEXT: vmov r3, r5, d1146; CHECK-NEXT: rsbs r0, r0, #0147; CHECK-NEXT: sbcs.w r0, r2, r1148; CHECK-NEXT: csetm r0, lt149; CHECK-NEXT: rsbs r1, r3, #0150; CHECK-NEXT: sbcs.w r1, r2, r5151; CHECK-NEXT: bfi r2, r0, #0, #8152; CHECK-NEXT: csetm r0, lt153; CHECK-NEXT: bfi r2, r0, #8, #8154; CHECK-NEXT: vmsr p0, r2155; CHECK-NEXT: vpsel q0, q0, q1156; CHECK-NEXT: vpop {d8, d9}157; CHECK-NEXT: pop {r4, r5, r7, pc}158entry:159 %conv = fptosi <2 x double> %x to <2 x i64>160 %0 = icmp slt <2 x i64> %conv, <i64 4294967295, i64 4294967295>161 %spec.store.select = select <2 x i1> %0, <2 x i64> %conv, <2 x i64> <i64 4294967295, i64 4294967295>162 %1 = icmp sgt <2 x i64> %spec.store.select, zeroinitializer163 %spec.store.select7 = select <2 x i1> %1, <2 x i64> %spec.store.select, <2 x i64> zeroinitializer164 %conv6 = trunc <2 x i64> %spec.store.select7 to <2 x i32>165 ret <2 x i32> %conv6166}167 168define arm_aapcs_vfpcc <4 x i32> @stest_f32i32(<4 x float> %x) {169; CHECK-LABEL: stest_f32i32:170; CHECK: @ %bb.0: @ %entry171; CHECK-NEXT: vcvt.s32.f32 q0, q0172; CHECK-NEXT: bx lr173entry:174 %conv = fptosi <4 x float> %x to <4 x i64>175 %0 = icmp slt <4 x i64> %conv, <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>176 %spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>177 %1 = icmp sgt <4 x i64> %spec.store.select, <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>178 %spec.store.select7 = select <4 x i1> %1, <4 x i64> %spec.store.select, <4 x i64> <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>179 %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>180 ret <4 x i32> %conv6181}182 183define arm_aapcs_vfpcc <4 x i32> @utest_f32i32(<4 x float> %x) {184; CHECK-LABEL: utest_f32i32:185; CHECK: @ %bb.0: @ %entry186; CHECK-NEXT: vcvt.u32.f32 q0, q0187; CHECK-NEXT: bx lr188entry:189 %conv = fptoui <4 x float> %x to <4 x i64>190 %0 = icmp ult <4 x i64> %conv, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>191 %spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>192 %conv6 = trunc <4 x i64> %spec.store.select to <4 x i32>193 ret <4 x i32> %conv6194}195 196define arm_aapcs_vfpcc <4 x i32> @ustest_f32i32(<4 x float> %x) {197; CHECK-LABEL: ustest_f32i32:198; CHECK: @ %bb.0: @ %entry199; CHECK-NEXT: vcvt.u32.f32 q0, q0200; CHECK-NEXT: bx lr201entry:202 %conv = fptosi <4 x float> %x to <4 x i64>203 %0 = icmp slt <4 x i64> %conv, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>204 %spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>205 %1 = icmp sgt <4 x i64> %spec.store.select, zeroinitializer206 %spec.store.select7 = select <4 x i1> %1, <4 x i64> %spec.store.select, <4 x i64> zeroinitializer207 %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>208 ret <4 x i32> %conv6209}210 211define arm_aapcs_vfpcc <4 x i32> @stest_f16i32(<4 x half> %x) {212; CHECK-LABEL: stest_f16i32:213; CHECK: @ %bb.0: @ %entry214; CHECK-NEXT: .save {r4, r5, r7, lr}215; CHECK-NEXT: push {r4, r5, r7, lr}216; CHECK-NEXT: .vsave {d8, d9, d10, d11}217; CHECK-NEXT: vpush {d8, d9, d10, d11}218; CHECK-NEXT: vmov.u16 r0, q0[3]219; CHECK-NEXT: vmov q4, q0220; CHECK-NEXT: bl __fixhfdi221; CHECK-NEXT: mov r4, r0222; CHECK-NEXT: vmov.u16 r0, q4[0]223; CHECK-NEXT: bl __fixhfdi224; CHECK-NEXT: mov r5, r0225; CHECK-NEXT: vmov.u16 r0, q4[2]226; CHECK-NEXT: bl __fixhfdi227; CHECK-NEXT: vmov q5[2], q5[0], r5, r0228; CHECK-NEXT: vmov.u16 r0, q4[1]229; CHECK-NEXT: bl __fixhfdi230; CHECK-NEXT: vmov q5[3], q5[1], r0, r4231; CHECK-NEXT: vmov q0, q5232; CHECK-NEXT: vpop {d8, d9, d10, d11}233; CHECK-NEXT: pop {r4, r5, r7, pc}234entry:235 %conv = fptosi <4 x half> %x to <4 x i64>236 %0 = icmp slt <4 x i64> %conv, <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>237 %spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>238 %1 = icmp sgt <4 x i64> %spec.store.select, <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>239 %spec.store.select7 = select <4 x i1> %1, <4 x i64> %spec.store.select, <4 x i64> <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>240 %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>241 ret <4 x i32> %conv6242}243 244define arm_aapcs_vfpcc <4 x i32> @utesth_f16i32(<4 x half> %x) {245; CHECK-LABEL: utesth_f16i32:246; CHECK: @ %bb.0: @ %entry247; CHECK-NEXT: .save {r4, r5, r7, lr}248; CHECK-NEXT: push {r4, r5, r7, lr}249; CHECK-NEXT: .vsave {d8, d9, d10, d11}250; CHECK-NEXT: vpush {d8, d9, d10, d11}251; CHECK-NEXT: vmov.u16 r0, q0[3]252; CHECK-NEXT: vmov q4, q0253; CHECK-NEXT: bl __fixunshfdi254; CHECK-NEXT: mov r4, r0255; CHECK-NEXT: vmov.u16 r0, q4[0]256; CHECK-NEXT: bl __fixunshfdi257; CHECK-NEXT: mov r5, r0258; CHECK-NEXT: vmov.u16 r0, q4[2]259; CHECK-NEXT: bl __fixunshfdi260; CHECK-NEXT: vmov q5[2], q5[0], r5, r0261; CHECK-NEXT: vmov.u16 r0, q4[1]262; CHECK-NEXT: bl __fixunshfdi263; CHECK-NEXT: vmov q5[3], q5[1], r0, r4264; CHECK-NEXT: vmov q0, q5265; CHECK-NEXT: vpop {d8, d9, d10, d11}266; CHECK-NEXT: pop {r4, r5, r7, pc}267entry:268 %conv = fptoui <4 x half> %x to <4 x i64>269 %0 = icmp ult <4 x i64> %conv, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>270 %spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>271 %conv6 = trunc <4 x i64> %spec.store.select to <4 x i32>272 ret <4 x i32> %conv6273}274 275define arm_aapcs_vfpcc <4 x i32> @ustest_f16i32(<4 x half> %x) {276; CHECK-LABEL: ustest_f16i32:277; CHECK: @ %bb.0: @ %entry278; CHECK-NEXT: .save {r4, r5, r6, lr}279; CHECK-NEXT: push {r4, r5, r6, lr}280; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}281; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}282; CHECK-NEXT: vmov.u16 r0, q0[3]283; CHECK-NEXT: vmov q4, q0284; CHECK-NEXT: bl __fixhfdi285; CHECK-NEXT: mov r4, r0286; CHECK-NEXT: vmov.u16 r0, q4[2]287; CHECK-NEXT: mov r5, r1288; CHECK-NEXT: bl __fixhfdi289; CHECK-NEXT: rsbs r2, r0, #0290; CHECK-NEXT: mov.w r6, #0291; CHECK-NEXT: vmov q0[2], q0[0], r0, r4292; CHECK-NEXT: sbcs.w r0, r6, r1293; CHECK-NEXT: csetm r0, lt294; CHECK-NEXT: movs r1, #0295; CHECK-NEXT: bfi r1, r0, #0, #8296; CHECK-NEXT: rsbs r0, r4, #0297; CHECK-NEXT: sbcs.w r0, r6, r5298; CHECK-NEXT: vmov.i32 q5, #0x0299; CHECK-NEXT: csetm r0, lt300; CHECK-NEXT: bfi r1, r0, #8, #8301; CHECK-NEXT: vmov.u16 r0, q4[1]302; CHECK-NEXT: vmsr p0, r1303; CHECK-NEXT: vpsel q6, q0, q5304; CHECK-NEXT: bl __fixhfdi305; CHECK-NEXT: mov r4, r0306; CHECK-NEXT: vmov.u16 r0, q4[0]307; CHECK-NEXT: mov r5, r1308; CHECK-NEXT: bl __fixhfdi309; CHECK-NEXT: rsbs r2, r0, #0310; CHECK-NEXT: vmov q0[2], q0[0], r0, r4311; CHECK-NEXT: sbcs.w r0, r6, r1312; CHECK-NEXT: csetm r0, lt313; CHECK-NEXT: rsbs r1, r4, #0314; CHECK-NEXT: sbcs.w r1, r6, r5315; CHECK-NEXT: bfi r6, r0, #0, #8316; CHECK-NEXT: csetm r0, lt317; CHECK-NEXT: bfi r6, r0, #8, #8318; CHECK-NEXT: vmsr p0, r6319; CHECK-NEXT: vpsel q0, q0, q5320; CHECK-NEXT: vmov.f32 s1, s2321; CHECK-NEXT: vmov.f32 s2, s24322; CHECK-NEXT: vmov.f32 s3, s26323; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}324; CHECK-NEXT: pop {r4, r5, r6, pc}325entry:326 %conv = fptosi <4 x half> %x to <4 x i64>327 %0 = icmp slt <4 x i64> %conv, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>328 %spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>329 %1 = icmp sgt <4 x i64> %spec.store.select, zeroinitializer330 %spec.store.select7 = select <4 x i1> %1, <4 x i64> %spec.store.select, <4 x i64> zeroinitializer331 %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>332 ret <4 x i32> %conv6333}334 335; i16 saturate336 337define arm_aapcs_vfpcc <2 x i16> @stest_f64i16(<2 x double> %x) {338; CHECK-LABEL: stest_f64i16:339; CHECK: @ %bb.0: @ %entry340; CHECK-NEXT: .save {r4, r5, r7, lr}341; CHECK-NEXT: push {r4, r5, r7, lr}342; CHECK-NEXT: .vsave {d8, d9}343; CHECK-NEXT: vpush {d8, d9}344; CHECK-NEXT: vmov q4, q0345; CHECK-NEXT: vmov r0, r1, d9346; CHECK-NEXT: bl __aeabi_d2lz347; CHECK-NEXT: mov r4, r0348; CHECK-NEXT: mov r5, r1349; CHECK-NEXT: vmov r0, r1, d8350; CHECK-NEXT: bl __aeabi_d2lz351; CHECK-NEXT: vmov q0[2], q0[0], r0, r4352; CHECK-NEXT: movw r4, #32767353; CHECK-NEXT: vmov q0[3], q0[1], r1, r5354; CHECK-NEXT: adr.w r12, .LCPI9_0355; CHECK-NEXT: vmov r1, r2, d0356; CHECK-NEXT: vldrw.u32 q1, [r12]357; CHECK-NEXT: vmov r3, r5, d1358; CHECK-NEXT: movw lr, #32768359; CHECK-NEXT: movt lr, #65535360; CHECK-NEXT: mov.w r12, #-1361; CHECK-NEXT: movs r0, #0362; CHECK-NEXT: subs r1, r1, r4363; CHECK-NEXT: sbcs r1, r2, #0364; CHECK-NEXT: mov.w r2, #0365; CHECK-NEXT: csetm r1, lt366; CHECK-NEXT: bfi r2, r1, #0, #8367; CHECK-NEXT: subs r1, r3, r4368; CHECK-NEXT: sbcs r1, r5, #0369; CHECK-NEXT: adr r4, .LCPI9_1370; CHECK-NEXT: csetm r1, lt371; CHECK-NEXT: bfi r2, r1, #8, #8372; CHECK-NEXT: vmsr p0, r2373; CHECK-NEXT: vpsel q0, q0, q1374; CHECK-NEXT: vldrw.u32 q1, [r4]375; CHECK-NEXT: vmov r1, r2, d0376; CHECK-NEXT: vmov r3, r5, d1377; CHECK-NEXT: subs.w r1, lr, r1378; CHECK-NEXT: sbcs.w r1, r12, r2379; CHECK-NEXT: csetm r1, lt380; CHECK-NEXT: bfi r0, r1, #0, #8381; CHECK-NEXT: subs.w r1, lr, r3382; CHECK-NEXT: sbcs.w r1, r12, r5383; CHECK-NEXT: csetm r1, lt384; CHECK-NEXT: bfi r0, r1, #8, #8385; CHECK-NEXT: vmsr p0, r0386; CHECK-NEXT: vpsel q0, q0, q1387; CHECK-NEXT: vpop {d8, d9}388; CHECK-NEXT: pop {r4, r5, r7, pc}389; CHECK-NEXT: .p2align 4390; CHECK-NEXT: @ %bb.1:391; CHECK-NEXT: .LCPI9_0:392; CHECK-NEXT: .long 32767 @ 0x7fff393; CHECK-NEXT: .long 0 @ 0x0394; CHECK-NEXT: .long 32767 @ 0x7fff395; CHECK-NEXT: .long 0 @ 0x0396; CHECK-NEXT: .LCPI9_1:397; CHECK-NEXT: .long 4294934528 @ 0xffff8000398; CHECK-NEXT: .long 0 @ 0x0399; CHECK-NEXT: .long 4294934528 @ 0xffff8000400; CHECK-NEXT: .long 0 @ 0x0401entry:402 %conv = fptosi <2 x double> %x to <2 x i32>403 %0 = icmp slt <2 x i32> %conv, <i32 32767, i32 32767>404 %spec.store.select = select <2 x i1> %0, <2 x i32> %conv, <2 x i32> <i32 32767, i32 32767>405 %1 = icmp sgt <2 x i32> %spec.store.select, <i32 -32768, i32 -32768>406 %spec.store.select7 = select <2 x i1> %1, <2 x i32> %spec.store.select, <2 x i32> <i32 -32768, i32 -32768>407 %conv6 = trunc <2 x i32> %spec.store.select7 to <2 x i16>408 ret <2 x i16> %conv6409}410 411define arm_aapcs_vfpcc <2 x i16> @utest_f64i16(<2 x double> %x) {412; CHECK-LABEL: utest_f64i16:413; CHECK: @ %bb.0: @ %entry414; CHECK-NEXT: .save {r4, r5, r7, lr}415; CHECK-NEXT: push {r4, r5, r7, lr}416; CHECK-NEXT: .vsave {d8, d9}417; CHECK-NEXT: vpush {d8, d9}418; CHECK-NEXT: vmov q4, q0419; CHECK-NEXT: vmov r0, r1, d9420; CHECK-NEXT: bl __aeabi_d2ulz421; CHECK-NEXT: mov r4, r0422; CHECK-NEXT: mov r5, r1423; CHECK-NEXT: vmov r0, r1, d8424; CHECK-NEXT: bl __aeabi_d2ulz425; CHECK-NEXT: vmov q0[2], q0[0], r0, r4426; CHECK-NEXT: movw r4, #65535427; CHECK-NEXT: vmov q0[3], q0[1], r1, r5428; CHECK-NEXT: movs r5, #0429; CHECK-NEXT: vmov r0, r1, d0430; CHECK-NEXT: vmov.i64 q1, #0xffff431; CHECK-NEXT: vmov r2, r3, d1432; CHECK-NEXT: subs r0, r0, r4433; CHECK-NEXT: sbcs r0, r1, #0434; CHECK-NEXT: csetm r0, lo435; CHECK-NEXT: bfi r5, r0, #0, #8436; CHECK-NEXT: subs r0, r2, r4437; CHECK-NEXT: sbcs r0, r3, #0438; CHECK-NEXT: csetm r0, lo439; CHECK-NEXT: bfi r5, r0, #8, #8440; CHECK-NEXT: vmsr p0, r5441; CHECK-NEXT: vpsel q0, q0, q1442; CHECK-NEXT: vpop {d8, d9}443; CHECK-NEXT: pop {r4, r5, r7, pc}444entry:445 %conv = fptoui <2 x double> %x to <2 x i32>446 %0 = icmp ult <2 x i32> %conv, <i32 65535, i32 65535>447 %spec.store.select = select <2 x i1> %0, <2 x i32> %conv, <2 x i32> <i32 65535, i32 65535>448 %conv6 = trunc <2 x i32> %spec.store.select to <2 x i16>449 ret <2 x i16> %conv6450}451 452define arm_aapcs_vfpcc <2 x i16> @ustest_f64i16(<2 x double> %x) {453; CHECK-LABEL: ustest_f64i16:454; CHECK: @ %bb.0: @ %entry455; CHECK-NEXT: .save {r4, r5, r7, lr}456; CHECK-NEXT: push {r4, r5, r7, lr}457; CHECK-NEXT: .vsave {d8, d9}458; CHECK-NEXT: vpush {d8, d9}459; CHECK-NEXT: vmov q4, q0460; CHECK-NEXT: vmov r0, r1, d9461; CHECK-NEXT: bl __aeabi_d2lz462; CHECK-NEXT: mov r4, r0463; CHECK-NEXT: mov r5, r1464; CHECK-NEXT: vmov r0, r1, d8465; CHECK-NEXT: bl __aeabi_d2lz466; CHECK-NEXT: vmov q0[2], q0[0], r0, r4467; CHECK-NEXT: movw r4, #65535468; CHECK-NEXT: vmov q0[3], q0[1], r1, r5469; CHECK-NEXT: vmov.i64 q1, #0xffff470; CHECK-NEXT: vmov r1, r2, d0471; CHECK-NEXT: movs r0, #0472; CHECK-NEXT: vmov r3, r5, d1473; CHECK-NEXT: subs r1, r1, r4474; CHECK-NEXT: sbcs r1, r2, #0475; CHECK-NEXT: mov.w r2, #0476; CHECK-NEXT: csetm r1, lt477; CHECK-NEXT: bfi r2, r1, #0, #8478; CHECK-NEXT: subs r1, r3, r4479; CHECK-NEXT: sbcs r1, r5, #0480; CHECK-NEXT: csetm r1, lt481; CHECK-NEXT: bfi r2, r1, #8, #8482; CHECK-NEXT: vmsr p0, r2483; CHECK-NEXT: vpsel q0, q0, q1484; CHECK-NEXT: vmov.i32 q1, #0x0485; CHECK-NEXT: vmov r1, r2, d0486; CHECK-NEXT: vmov r3, r5, d1487; CHECK-NEXT: rsbs r1, r1, #0488; CHECK-NEXT: sbcs.w r1, r0, r2489; CHECK-NEXT: csetm r1, lt490; CHECK-NEXT: rsbs r2, r3, #0491; CHECK-NEXT: sbcs.w r2, r0, r5492; CHECK-NEXT: bfi r0, r1, #0, #8493; CHECK-NEXT: csetm r1, lt494; CHECK-NEXT: bfi r0, r1, #8, #8495; CHECK-NEXT: vmsr p0, r0496; CHECK-NEXT: vpsel q0, q0, q1497; CHECK-NEXT: vpop {d8, d9}498; CHECK-NEXT: pop {r4, r5, r7, pc}499entry:500 %conv = fptosi <2 x double> %x to <2 x i32>501 %0 = icmp slt <2 x i32> %conv, <i32 65535, i32 65535>502 %spec.store.select = select <2 x i1> %0, <2 x i32> %conv, <2 x i32> <i32 65535, i32 65535>503 %1 = icmp sgt <2 x i32> %spec.store.select, zeroinitializer504 %spec.store.select7 = select <2 x i1> %1, <2 x i32> %spec.store.select, <2 x i32> zeroinitializer505 %conv6 = trunc <2 x i32> %spec.store.select7 to <2 x i16>506 ret <2 x i16> %conv6507}508 509define arm_aapcs_vfpcc <4 x i16> @stest_f32i16(<4 x float> %x) {510; CHECK-LABEL: stest_f32i16:511; CHECK: @ %bb.0: @ %entry512; CHECK-NEXT: vcvt.s32.f32 q0, q0513; CHECK-NEXT: vqmovnb.s32 q0, q0514; CHECK-NEXT: vmovlb.s16 q0, q0515; CHECK-NEXT: bx lr516entry:517 %conv = fptosi <4 x float> %x to <4 x i32>518 %0 = icmp slt <4 x i32> %conv, <i32 32767, i32 32767, i32 32767, i32 32767>519 %spec.store.select = select <4 x i1> %0, <4 x i32> %conv, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>520 %1 = icmp sgt <4 x i32> %spec.store.select, <i32 -32768, i32 -32768, i32 -32768, i32 -32768>521 %spec.store.select7 = select <4 x i1> %1, <4 x i32> %spec.store.select, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>522 %conv6 = trunc <4 x i32> %spec.store.select7 to <4 x i16>523 ret <4 x i16> %conv6524}525 526define arm_aapcs_vfpcc <4 x i16> @utest_f32i16(<4 x float> %x) {527; CHECK-LABEL: utest_f32i16:528; CHECK: @ %bb.0: @ %entry529; CHECK-NEXT: vcvt.u32.f32 q0, q0530; CHECK-NEXT: vqmovnb.u32 q0, q0531; CHECK-NEXT: vmovlb.u16 q0, q0532; CHECK-NEXT: bx lr533entry:534 %conv = fptoui <4 x float> %x to <4 x i32>535 %0 = icmp ult <4 x i32> %conv, <i32 65535, i32 65535, i32 65535, i32 65535>536 %spec.store.select = select <4 x i1> %0, <4 x i32> %conv, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>537 %conv6 = trunc <4 x i32> %spec.store.select to <4 x i16>538 ret <4 x i16> %conv6539}540 541define arm_aapcs_vfpcc <4 x i16> @ustest_f32i16(<4 x float> %x) {542; CHECK-LABEL: ustest_f32i16:543; CHECK: @ %bb.0: @ %entry544; CHECK-NEXT: vmov.i32 q1, #0xffff545; CHECK-NEXT: vcvt.s32.f32 q0, q0546; CHECK-NEXT: vmov.i32 q2, #0x0547; CHECK-NEXT: vmin.s32 q0, q0, q1548; CHECK-NEXT: vmax.s32 q0, q0, q2549; CHECK-NEXT: bx lr550entry:551 %conv = fptosi <4 x float> %x to <4 x i32>552 %0 = icmp slt <4 x i32> %conv, <i32 65535, i32 65535, i32 65535, i32 65535>553 %spec.store.select = select <4 x i1> %0, <4 x i32> %conv, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>554 %1 = icmp sgt <4 x i32> %spec.store.select, zeroinitializer555 %spec.store.select7 = select <4 x i1> %1, <4 x i32> %spec.store.select, <4 x i32> zeroinitializer556 %conv6 = trunc <4 x i32> %spec.store.select7 to <4 x i16>557 ret <4 x i16> %conv6558}559 560define arm_aapcs_vfpcc <8 x i16> @stest_f16i16(<8 x half> %x) {561; CHECK-LABEL: stest_f16i16:562; CHECK: @ %bb.0: @ %entry563; CHECK-NEXT: vcvt.s16.f16 q0, q0564; CHECK-NEXT: bx lr565entry:566 %conv = fptosi <8 x half> %x to <8 x i32>567 %0 = icmp slt <8 x i32> %conv, <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>568 %spec.store.select = select <8 x i1> %0, <8 x i32> %conv, <8 x i32> <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>569 %1 = icmp sgt <8 x i32> %spec.store.select, <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768>570 %spec.store.select7 = select <8 x i1> %1, <8 x i32> %spec.store.select, <8 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768>571 %conv6 = trunc <8 x i32> %spec.store.select7 to <8 x i16>572 ret <8 x i16> %conv6573}574 575define arm_aapcs_vfpcc <8 x i16> @utesth_f16i16(<8 x half> %x) {576; CHECK-LABEL: utesth_f16i16:577; CHECK: @ %bb.0: @ %entry578; CHECK-NEXT: vmovx.f16 s6, s2579; CHECK-NEXT: vcvt.u32.f16 s12, s2580; CHECK-NEXT: vmovx.f16 s2, s0581; CHECK-NEXT: vcvt.u32.f16 s0, s0582; CHECK-NEXT: vcvt.u32.f16 s14, s2583; CHECK-NEXT: vmov r0, s0584; CHECK-NEXT: vmovx.f16 s4, s3585; CHECK-NEXT: vmovx.f16 s10, s1586; CHECK-NEXT: vcvt.u32.f16 s8, s3587; CHECK-NEXT: vcvt.u32.f16 s5, s1588; CHECK-NEXT: vmov.16 q0[0], r0589; CHECK-NEXT: vmov r0, s14590; CHECK-NEXT: vmov.16 q0[1], r0591; CHECK-NEXT: vmov r0, s5592; CHECK-NEXT: vcvt.u32.f16 s10, s10593; CHECK-NEXT: vmov.16 q0[2], r0594; CHECK-NEXT: vmov r0, s10595; CHECK-NEXT: vcvt.u32.f16 s6, s6596; CHECK-NEXT: vmov.16 q0[3], r0597; CHECK-NEXT: vmov r0, s12598; CHECK-NEXT: vmov.16 q0[4], r0599; CHECK-NEXT: vmov r0, s6600; CHECK-NEXT: vmov.16 q0[5], r0601; CHECK-NEXT: vmov r0, s8602; CHECK-NEXT: vcvt.u32.f16 s4, s4603; CHECK-NEXT: vmov.16 q0[6], r0604; CHECK-NEXT: vmov r0, s4605; CHECK-NEXT: vmov.16 q0[7], r0606; CHECK-NEXT: bx lr607entry:608 %conv = fptoui <8 x half> %x to <8 x i32>609 %0 = icmp ult <8 x i32> %conv, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>610 %spec.store.select = select <8 x i1> %0, <8 x i32> %conv, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>611 %conv6 = trunc <8 x i32> %spec.store.select to <8 x i16>612 ret <8 x i16> %conv6613}614 615define arm_aapcs_vfpcc <8 x i16> @ustest_f16i16(<8 x half> %x) {616; CHECK-LABEL: ustest_f16i16:617; CHECK: @ %bb.0: @ %entry618; CHECK-NEXT: .vsave {d8, d9}619; CHECK-NEXT: vpush {d8, d9}620; CHECK-NEXT: .pad #16621; CHECK-NEXT: sub sp, #16622; CHECK-NEXT: vmovx.f16 s6, s0623; CHECK-NEXT: vcvt.s32.f16 s10, s0624; CHECK-NEXT: vmovx.f16 s0, s3625; CHECK-NEXT: vcvt.s32.f16 s5, s3626; CHECK-NEXT: vcvt.s32.f16 s12, s0627; CHECK-NEXT: vmovx.f16 s0, s2628; CHECK-NEXT: vcvt.s32.f16 s7, s2629; CHECK-NEXT: vcvt.s32.f16 s14, s0630; CHECK-NEXT: vmov r1, s5631; CHECK-NEXT: vmovx.f16 s4, s1632; CHECK-NEXT: vmov r2, s7633; CHECK-NEXT: vcvt.s32.f16 s8, s1634; CHECK-NEXT: vmov q4[2], q4[0], r2, r1635; CHECK-NEXT: vmov r1, s12636; CHECK-NEXT: vmov r2, s14637; CHECK-NEXT: vcvt.s32.f16 s4, s4638; CHECK-NEXT: vmov q4[3], q4[1], r2, r1639; CHECK-NEXT: vcvt.s32.f16 s6, s6640; CHECK-NEXT: vmov r1, s8641; CHECK-NEXT: vmov.i32 q0, #0x0642; CHECK-NEXT: vmov r2, s10643; CHECK-NEXT: mov r0, sp644; CHECK-NEXT: vmov q2[2], q2[0], r2, r1645; CHECK-NEXT: vmov r1, s4646; CHECK-NEXT: vmov r2, s6647; CHECK-NEXT: vmax.s32 q3, q4, q0648; CHECK-NEXT: vmov q2[3], q2[1], r2, r1649; CHECK-NEXT: vstrh.32 q3, [r0, #8]650; CHECK-NEXT: vmax.s32 q0, q2, q0651; CHECK-NEXT: vstrh.32 q0, [r0]652; CHECK-NEXT: vldrw.u32 q0, [r0]653; CHECK-NEXT: add sp, #16654; CHECK-NEXT: vpop {d8, d9}655; CHECK-NEXT: bx lr656entry:657 %conv = fptosi <8 x half> %x to <8 x i32>658 %0 = icmp slt <8 x i32> %conv, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>659 %spec.store.select = select <8 x i1> %0, <8 x i32> %conv, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>660 %1 = icmp sgt <8 x i32> %spec.store.select, zeroinitializer661 %spec.store.select7 = select <8 x i1> %1, <8 x i32> %spec.store.select, <8 x i32> zeroinitializer662 %conv6 = trunc <8 x i32> %spec.store.select7 to <8 x i16>663 ret <8 x i16> %conv6664}665 666; i64 saturate667 668define arm_aapcs_vfpcc <2 x i64> @stest_f64i64(<2 x double> %x) {669; CHECK-LABEL: stest_f64i64:670; CHECK: @ %bb.0: @ %entry671; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, lr}672; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr}673; CHECK-NEXT: .pad #4674; CHECK-NEXT: sub sp, #4675; CHECK-NEXT: .vsave {d8, d9}676; CHECK-NEXT: vpush {d8, d9}677; CHECK-NEXT: vmov q4, q0678; CHECK-NEXT: vmov r0, r1, d8679; CHECK-NEXT: bl __fixdfti680; CHECK-NEXT: vmov r12, lr, d9681; CHECK-NEXT: subs.w r5, r0, #-1682; CHECK-NEXT: mvn r4, #-2147483648683; CHECK-NEXT: sbcs.w r5, r1, r4684; CHECK-NEXT: sbcs r5, r2, #0685; CHECK-NEXT: mov.w r7, #-2147483648686; CHECK-NEXT: sbcs r5, r3, #0687; CHECK-NEXT: cset r5, lt688; CHECK-NEXT: cmp r5, #0689; CHECK-NEXT: csel r3, r3, r5, ne690; CHECK-NEXT: csel r2, r2, r5, ne691; CHECK-NEXT: mov.w r5, #-1692; CHECK-NEXT: csel r1, r1, r4, ne693; CHECK-NEXT: csel r0, r0, r5, ne694; CHECK-NEXT: rsbs r6, r0, #0695; CHECK-NEXT: sbcs.w r6, r7, r1696; CHECK-NEXT: sbcs.w r2, r5, r2697; CHECK-NEXT: sbcs.w r2, r5, r3698; CHECK-NEXT: csel r8, r1, r7, lt699; CHECK-NEXT: cset r1, lt700; CHECK-NEXT: cmp r1, #0701; CHECK-NEXT: csel r9, r0, r1, ne702; CHECK-NEXT: mov r0, r12703; CHECK-NEXT: mov r1, lr704; CHECK-NEXT: bl __fixdfti705; CHECK-NEXT: subs.w r6, r0, #-1706; CHECK-NEXT: sbcs.w r6, r1, r4707; CHECK-NEXT: sbcs r6, r2, #0708; CHECK-NEXT: sbcs r6, r3, #0709; CHECK-NEXT: cset r6, lt710; CHECK-NEXT: cmp r6, #0711; CHECK-NEXT: csel r0, r0, r5, ne712; CHECK-NEXT: csel r3, r3, r6, ne713; CHECK-NEXT: csel r2, r2, r6, ne714; CHECK-NEXT: csel r1, r1, r4, ne715; CHECK-NEXT: rsbs r6, r0, #0716; CHECK-NEXT: sbcs.w r6, r7, r1717; CHECK-NEXT: sbcs.w r2, r5, r2718; CHECK-NEXT: sbcs.w r2, r5, r3719; CHECK-NEXT: cset r2, lt720; CHECK-NEXT: csel r1, r1, r7, lt721; CHECK-NEXT: cmp r2, #0722; CHECK-NEXT: csel r0, r0, r2, ne723; CHECK-NEXT: vmov q0[2], q0[0], r9, r0724; CHECK-NEXT: vmov q0[3], q0[1], r8, r1725; CHECK-NEXT: vpop {d8, d9}726; CHECK-NEXT: add sp, #4727; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc}728entry:729 %conv = fptosi <2 x double> %x to <2 x i128>730 %0 = icmp slt <2 x i128> %conv, <i128 9223372036854775807, i128 9223372036854775807>731 %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807>732 %1 = icmp sgt <2 x i128> %spec.store.select, <i128 -9223372036854775808, i128 -9223372036854775808>733 %spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808>734 %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>735 ret <2 x i64> %conv6736}737 738define arm_aapcs_vfpcc <2 x i64> @utest_f64i64(<2 x double> %x) {739; CHECK-LABEL: utest_f64i64:740; CHECK: @ %bb.0: @ %entry741; CHECK-NEXT: .save {r4, r5, r7, lr}742; CHECK-NEXT: push {r4, r5, r7, lr}743; CHECK-NEXT: .vsave {d8, d9}744; CHECK-NEXT: vpush {d8, d9}745; CHECK-NEXT: vmov q4, q0746; CHECK-NEXT: vmov r0, r1, d9747; CHECK-NEXT: bl __fixunsdfti748; CHECK-NEXT: vmov r12, lr, d8749; CHECK-NEXT: subs r2, #1750; CHECK-NEXT: sbcs r2, r3, #0751; CHECK-NEXT: cset r2, lo752; CHECK-NEXT: cmp r2, #0753; CHECK-NEXT: csel r4, r1, r2, ne754; CHECK-NEXT: csel r5, r0, r2, ne755; CHECK-NEXT: mov r0, r12756; CHECK-NEXT: mov r1, lr757; CHECK-NEXT: bl __fixunsdfti758; CHECK-NEXT: subs r2, #1759; CHECK-NEXT: sbcs r2, r3, #0760; CHECK-NEXT: cset r2, lo761; CHECK-NEXT: cmp r2, #0762; CHECK-NEXT: csel r0, r0, r2, ne763; CHECK-NEXT: csel r1, r1, r2, ne764; CHECK-NEXT: vmov q0[2], q0[0], r0, r5765; CHECK-NEXT: vmov q0[3], q0[1], r1, r4766; CHECK-NEXT: vpop {d8, d9}767; CHECK-NEXT: pop {r4, r5, r7, pc}768entry:769 %conv = fptoui <2 x double> %x to <2 x i128>770 %0 = icmp ult <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>771 %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>772 %conv6 = trunc <2 x i128> %spec.store.select to <2 x i64>773 ret <2 x i64> %conv6774}775 776define arm_aapcs_vfpcc <2 x i64> @ustest_f64i64(<2 x double> %x) {777; CHECK-LABEL: ustest_f64i64:778; CHECK: @ %bb.0: @ %entry779; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}780; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, lr}781; CHECK-NEXT: .vsave {d8, d9}782; CHECK-NEXT: vpush {d8, d9}783; CHECK-NEXT: vmov q4, q0784; CHECK-NEXT: vmov r0, r1, d9785; CHECK-NEXT: bl __fixdfti786; CHECK-NEXT: vmov r12, lr, d8787; CHECK-NEXT: subs r4, r2, #1788; CHECK-NEXT: sbcs r4, r3, #0789; CHECK-NEXT: mov.w r8, #1790; CHECK-NEXT: cset r4, lt791; CHECK-NEXT: cmp r4, #0792; CHECK-NEXT: csel r0, r0, r4, ne793; CHECK-NEXT: csel r3, r3, r4, ne794; CHECK-NEXT: csel r1, r1, r4, ne795; CHECK-NEXT: csel r2, r2, r8, ne796; CHECK-NEXT: rsbs r5, r0, #0797; CHECK-NEXT: mov.w r4, #0798; CHECK-NEXT: sbcs.w r5, r4, r1799; CHECK-NEXT: sbcs.w r2, r4, r2800; CHECK-NEXT: sbcs.w r2, r4, r3801; CHECK-NEXT: cset r2, lt802; CHECK-NEXT: cmp r2, #0803; CHECK-NEXT: csel r5, r1, r2, ne804; CHECK-NEXT: csel r7, r0, r2, ne805; CHECK-NEXT: mov r0, r12806; CHECK-NEXT: mov r1, lr807; CHECK-NEXT: bl __fixdfti808; CHECK-NEXT: subs r6, r2, #1809; CHECK-NEXT: sbcs r6, r3, #0810; CHECK-NEXT: cset r6, lt811; CHECK-NEXT: cmp r6, #0812; CHECK-NEXT: csel r0, r0, r6, ne813; CHECK-NEXT: csel r3, r3, r6, ne814; CHECK-NEXT: csel r1, r1, r6, ne815; CHECK-NEXT: csel r2, r2, r8, ne816; CHECK-NEXT: rsbs r6, r0, #0817; CHECK-NEXT: sbcs.w r6, r4, r1818; CHECK-NEXT: sbcs.w r2, r4, r2819; CHECK-NEXT: sbcs.w r2, r4, r3820; CHECK-NEXT: cset r2, lt821; CHECK-NEXT: cmp r2, #0822; CHECK-NEXT: csel r0, r0, r2, ne823; CHECK-NEXT: csel r1, r1, r2, ne824; CHECK-NEXT: vmov q0[2], q0[0], r0, r7825; CHECK-NEXT: vmov q0[3], q0[1], r1, r5826; CHECK-NEXT: vpop {d8, d9}827; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, pc}828entry:829 %conv = fptosi <2 x double> %x to <2 x i128>830 %0 = icmp slt <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>831 %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>832 %1 = icmp sgt <2 x i128> %spec.store.select, zeroinitializer833 %spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> zeroinitializer834 %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>835 ret <2 x i64> %conv6836}837 838define arm_aapcs_vfpcc <2 x i64> @stest_f32i64(<2 x float> %x) {839; CHECK-LABEL: stest_f32i64:840; CHECK: @ %bb.0: @ %entry841; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}842; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, lr}843; CHECK-NEXT: vmov r0, r9, d0844; CHECK-NEXT: bl __fixsfti845; CHECK-NEXT: subs.w r7, r0, #-1846; CHECK-NEXT: mvn r5, #-2147483648847; CHECK-NEXT: sbcs.w r7, r1, r5848; CHECK-NEXT: mov.w r6, #-1849; CHECK-NEXT: sbcs r7, r2, #0850; CHECK-NEXT: sbcs r7, r3, #0851; CHECK-NEXT: cset r7, lt852; CHECK-NEXT: cmp r7, #0853; CHECK-NEXT: csel r0, r0, r6, ne854; CHECK-NEXT: csel r3, r3, r7, ne855; CHECK-NEXT: csel r2, r2, r7, ne856; CHECK-NEXT: csel r1, r1, r5, ne857; CHECK-NEXT: rsbs r4, r0, #0858; CHECK-NEXT: mov.w r7, #-2147483648859; CHECK-NEXT: sbcs.w r4, r7, r1860; CHECK-NEXT: sbcs.w r2, r6, r2861; CHECK-NEXT: sbcs.w r2, r6, r3862; CHECK-NEXT: csel r8, r1, r7, lt863; CHECK-NEXT: cset r1, lt864; CHECK-NEXT: cmp r1, #0865; CHECK-NEXT: csel r10, r0, r1, ne866; CHECK-NEXT: mov r0, r9867; CHECK-NEXT: bl __fixsfti868; CHECK-NEXT: subs.w r4, r0, #-1869; CHECK-NEXT: sbcs.w r4, r1, r5870; CHECK-NEXT: sbcs r4, r2, #0871; CHECK-NEXT: sbcs r4, r3, #0872; CHECK-NEXT: cset r4, lt873; CHECK-NEXT: cmp r4, #0874; CHECK-NEXT: csel r0, r0, r6, ne875; CHECK-NEXT: csel r3, r3, r4, ne876; CHECK-NEXT: csel r2, r2, r4, ne877; CHECK-NEXT: csel r1, r1, r5, ne878; CHECK-NEXT: rsbs r5, r0, #0879; CHECK-NEXT: sbcs.w r5, r7, r1880; CHECK-NEXT: sbcs.w r2, r6, r2881; CHECK-NEXT: sbcs.w r2, r6, r3882; CHECK-NEXT: cset r2, lt883; CHECK-NEXT: csel r1, r1, r7, lt884; CHECK-NEXT: cmp r2, #0885; CHECK-NEXT: csel r0, r0, r2, ne886; CHECK-NEXT: vmov q0[2], q0[0], r10, r0887; CHECK-NEXT: vmov q0[3], q0[1], r8, r1888; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, pc}889entry:890 %conv = fptosi <2 x float> %x to <2 x i128>891 %0 = icmp slt <2 x i128> %conv, <i128 9223372036854775807, i128 9223372036854775807>892 %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807>893 %1 = icmp sgt <2 x i128> %spec.store.select, <i128 -9223372036854775808, i128 -9223372036854775808>894 %spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808>895 %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>896 ret <2 x i64> %conv6897}898 899define arm_aapcs_vfpcc <2 x i64> @utest_f32i64(<2 x float> %x) {900; CHECK-LABEL: utest_f32i64:901; CHECK: @ %bb.0: @ %entry902; CHECK-NEXT: .save {r4, r5, r6, lr}903; CHECK-NEXT: push {r4, r5, r6, lr}904; CHECK-NEXT: vmov r4, r0, d0905; CHECK-NEXT: bl __fixunssfti906; CHECK-NEXT: subs r2, #1907; CHECK-NEXT: sbcs r2, r3, #0908; CHECK-NEXT: cset r2, lo909; CHECK-NEXT: cmp r2, #0910; CHECK-NEXT: csel r6, r0, r2, ne911; CHECK-NEXT: mov r0, r4912; CHECK-NEXT: csel r5, r1, r2, ne913; CHECK-NEXT: bl __fixunssfti914; CHECK-NEXT: subs r2, #1915; CHECK-NEXT: sbcs r2, r3, #0916; CHECK-NEXT: cset r2, lo917; CHECK-NEXT: cmp r2, #0918; CHECK-NEXT: csel r0, r0, r2, ne919; CHECK-NEXT: csel r1, r1, r2, ne920; CHECK-NEXT: vmov q0[2], q0[0], r0, r6921; CHECK-NEXT: vmov q0[3], q0[1], r1, r5922; CHECK-NEXT: pop {r4, r5, r6, pc}923entry:924 %conv = fptoui <2 x float> %x to <2 x i128>925 %0 = icmp ult <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>926 %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>927 %conv6 = trunc <2 x i128> %spec.store.select to <2 x i64>928 ret <2 x i64> %conv6929}930 931define arm_aapcs_vfpcc <2 x i64> @ustest_f32i64(<2 x float> %x) {932; CHECK-LABEL: ustest_f32i64:933; CHECK: @ %bb.0: @ %entry934; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}935; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, lr}936; CHECK-NEXT: vmov r5, r0, d0937; CHECK-NEXT: bl __fixsfti938; CHECK-NEXT: subs r4, r2, #1939; CHECK-NEXT: mov.w r8, #1940; CHECK-NEXT: sbcs r4, r3, #0941; CHECK-NEXT: mov.w r6, #0942; CHECK-NEXT: cset r4, lt943; CHECK-NEXT: cmp r4, #0944; CHECK-NEXT: csel r0, r0, r4, ne945; CHECK-NEXT: csel r3, r3, r4, ne946; CHECK-NEXT: csel r1, r1, r4, ne947; CHECK-NEXT: csel r2, r2, r8, ne948; CHECK-NEXT: rsbs r4, r0, #0949; CHECK-NEXT: sbcs.w r4, r6, r1950; CHECK-NEXT: sbcs.w r2, r6, r2951; CHECK-NEXT: sbcs.w r2, r6, r3952; CHECK-NEXT: cset r2, lt953; CHECK-NEXT: cmp r2, #0954; CHECK-NEXT: csel r7, r0, r2, ne955; CHECK-NEXT: mov r0, r5956; CHECK-NEXT: csel r4, r1, r2, ne957; CHECK-NEXT: bl __fixsfti958; CHECK-NEXT: subs r5, r2, #1959; CHECK-NEXT: sbcs r5, r3, #0960; CHECK-NEXT: cset r5, lt961; CHECK-NEXT: cmp r5, #0962; CHECK-NEXT: csel r0, r0, r5, ne963; CHECK-NEXT: csel r3, r3, r5, ne964; CHECK-NEXT: csel r1, r1, r5, ne965; CHECK-NEXT: csel r2, r2, r8, ne966; CHECK-NEXT: rsbs r5, r0, #0967; CHECK-NEXT: sbcs.w r5, r6, r1968; CHECK-NEXT: sbcs.w r2, r6, r2969; CHECK-NEXT: sbcs.w r2, r6, r3970; CHECK-NEXT: cset r2, lt971; CHECK-NEXT: cmp r2, #0972; CHECK-NEXT: csel r0, r0, r2, ne973; CHECK-NEXT: csel r1, r1, r2, ne974; CHECK-NEXT: vmov q0[2], q0[0], r0, r7975; CHECK-NEXT: vmov q0[3], q0[1], r1, r4976; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, pc}977entry:978 %conv = fptosi <2 x float> %x to <2 x i128>979 %0 = icmp slt <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>980 %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>981 %1 = icmp sgt <2 x i128> %spec.store.select, zeroinitializer982 %spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> zeroinitializer983 %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>984 ret <2 x i64> %conv6985}986 987define arm_aapcs_vfpcc <2 x i64> @stest_f16i64(<2 x half> %x) {988; CHECK-LABEL: stest_f16i64:989; CHECK: @ %bb.0: @ %entry990; CHECK-NEXT: .save {r4, r5, r7, lr}991; CHECK-NEXT: push {r4, r5, r7, lr}992; CHECK-NEXT: .vsave {d8, d9}993; CHECK-NEXT: vpush {d8, d9}994; CHECK-NEXT: vmov.u16 r0, q0[1]995; CHECK-NEXT: vmov q4, q0996; CHECK-NEXT: bl __fixhfti997; CHECK-NEXT: mov r4, r0998; CHECK-NEXT: vmov.u16 r0, q4[0]999; CHECK-NEXT: mov r5, r11000; CHECK-NEXT: bl __fixhfti1001; CHECK-NEXT: vmov q0[2], q0[0], r0, r41002; CHECK-NEXT: vmov q0[3], q0[1], r1, r51003; CHECK-NEXT: vpop {d8, d9}1004; CHECK-NEXT: pop {r4, r5, r7, pc}1005entry:1006 %conv = fptosi <2 x half> %x to <2 x i128>1007 %0 = icmp slt <2 x i128> %conv, <i128 9223372036854775807, i128 9223372036854775807>1008 %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807>1009 %1 = icmp sgt <2 x i128> %spec.store.select, <i128 -9223372036854775808, i128 -9223372036854775808>1010 %spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808>1011 %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>1012 ret <2 x i64> %conv61013}1014 1015define arm_aapcs_vfpcc <2 x i64> @utesth_f16i64(<2 x half> %x) {1016; CHECK-LABEL: utesth_f16i64:1017; CHECK: @ %bb.0: @ %entry1018; CHECK-NEXT: .save {r4, r5, r7, lr}1019; CHECK-NEXT: push {r4, r5, r7, lr}1020; CHECK-NEXT: .vsave {d8, d9}1021; CHECK-NEXT: vpush {d8, d9}1022; CHECK-NEXT: vmov.u16 r0, q0[1]1023; CHECK-NEXT: vmov q4, q01024; CHECK-NEXT: bl __fixunshfti1025; CHECK-NEXT: mov r4, r01026; CHECK-NEXT: vmov.u16 r0, q4[0]1027; CHECK-NEXT: mov r5, r11028; CHECK-NEXT: bl __fixunshfti1029; CHECK-NEXT: vmov q0[2], q0[0], r0, r41030; CHECK-NEXT: vmov q0[3], q0[1], r1, r51031; CHECK-NEXT: vpop {d8, d9}1032; CHECK-NEXT: pop {r4, r5, r7, pc}1033entry:1034 %conv = fptoui <2 x half> %x to <2 x i128>1035 %0 = icmp ult <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>1036 %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>1037 %conv6 = trunc <2 x i128> %spec.store.select to <2 x i64>1038 ret <2 x i64> %conv61039}1040 1041define arm_aapcs_vfpcc <2 x i64> @ustest_f16i64(<2 x half> %x) {1042; CHECK-LABEL: ustest_f16i64:1043; CHECK: @ %bb.0: @ %entry1044; CHECK-NEXT: .save {r4, r5, r6, r7, lr}1045; CHECK-NEXT: push {r4, r5, r6, r7, lr}1046; CHECK-NEXT: .pad #41047; CHECK-NEXT: sub sp, #41048; CHECK-NEXT: .vsave {d8, d9}1049; CHECK-NEXT: vpush {d8, d9}1050; CHECK-NEXT: vmov.u16 r0, q0[1]1051; CHECK-NEXT: vmov q4, q01052; CHECK-NEXT: bl __fixhfti1053; CHECK-NEXT: rsbs r4, r0, #01054; CHECK-NEXT: mov.w r5, #01055; CHECK-NEXT: sbcs.w r4, r5, r11056; CHECK-NEXT: sbcs.w r2, r5, r21057; CHECK-NEXT: sbcs.w r2, r5, r31058; CHECK-NEXT: cset r2, lt1059; CHECK-NEXT: cmp r2, #01060; CHECK-NEXT: csel r6, r0, r2, ne1061; CHECK-NEXT: vmov.u16 r0, q4[0]1062; CHECK-NEXT: csel r7, r1, r2, ne1063; CHECK-NEXT: bl __fixhfti1064; CHECK-NEXT: rsbs r4, r0, #01065; CHECK-NEXT: sbcs.w r4, r5, r11066; CHECK-NEXT: sbcs.w r2, r5, r21067; CHECK-NEXT: sbcs.w r2, r5, r31068; CHECK-NEXT: cset r2, lt1069; CHECK-NEXT: cmp r2, #01070; CHECK-NEXT: csel r0, r0, r2, ne1071; CHECK-NEXT: csel r1, r1, r2, ne1072; CHECK-NEXT: vmov q0[2], q0[0], r0, r61073; CHECK-NEXT: vmov q0[3], q0[1], r1, r71074; CHECK-NEXT: vpop {d8, d9}1075; CHECK-NEXT: add sp, #41076; CHECK-NEXT: pop {r4, r5, r6, r7, pc}1077entry:1078 %conv = fptosi <2 x half> %x to <2 x i128>1079 %0 = icmp slt <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>1080 %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>1081 %1 = icmp sgt <2 x i128> %spec.store.select, zeroinitializer1082 %spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> zeroinitializer1083 %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>1084 ret <2 x i64> %conv61085}1086 1087 1088 1089; i32 saturate1090 1091define arm_aapcs_vfpcc <2 x i32> @stest_f64i32_mm(<2 x double> %x) {1092; CHECK-LABEL: stest_f64i32_mm:1093; CHECK: @ %bb.0: @ %entry1094; CHECK-NEXT: .save {r4, r5, r7, lr}1095; CHECK-NEXT: push {r4, r5, r7, lr}1096; CHECK-NEXT: .vsave {d8, d9}1097; CHECK-NEXT: vpush {d8, d9}1098; CHECK-NEXT: vmov q4, q01099; CHECK-NEXT: vmov r0, r1, d81100; CHECK-NEXT: bl __aeabi_d2lz1101; CHECK-NEXT: mov r4, r01102; CHECK-NEXT: mov r5, r11103; CHECK-NEXT: vmov r0, r1, d91104; CHECK-NEXT: bl __aeabi_d2lz1105; CHECK-NEXT: adr r3, .LCPI27_01106; CHECK-NEXT: mvn r12, #-21474836481107; CHECK-NEXT: vldrw.u32 q0, [r3]1108; CHECK-NEXT: subs.w r3, r4, r121109; CHECK-NEXT: sbcs r3, r5, #01110; CHECK-NEXT: vmov q1[2], q1[0], r4, r01111; CHECK-NEXT: csetm r3, lt1112; CHECK-NEXT: subs.w r0, r0, r121113; CHECK-NEXT: sbcs r0, r1, #01114; CHECK-NEXT: vmov q1[3], q1[1], r5, r11115; CHECK-NEXT: mov.w r5, #01116; CHECK-NEXT: csetm r0, lt1117; CHECK-NEXT: bfi r5, r3, #0, #81118; CHECK-NEXT: mov.w r12, #-11119; CHECK-NEXT: bfi r5, r0, #8, #81120; CHECK-NEXT: movs r2, #01121; CHECK-NEXT: vmsr p0, r51122; CHECK-NEXT: adr r4, .LCPI27_11123; CHECK-NEXT: vpsel q0, q1, q01124; CHECK-NEXT: vldrw.u32 q1, [r4]1125; CHECK-NEXT: vmov r0, r1, d01126; CHECK-NEXT: vmov r3, r5, d11127; CHECK-NEXT: rsbs.w r0, r0, #-21474836481128; CHECK-NEXT: sbcs.w r0, r12, r11129; CHECK-NEXT: csetm r0, lt1130; CHECK-NEXT: bfi r2, r0, #0, #81131; CHECK-NEXT: rsbs.w r0, r3, #-21474836481132; CHECK-NEXT: sbcs.w r0, r12, r51133; CHECK-NEXT: csetm r0, lt1134; CHECK-NEXT: bfi r2, r0, #8, #81135; CHECK-NEXT: vmsr p0, r21136; CHECK-NEXT: vpsel q0, q0, q11137; CHECK-NEXT: vpop {d8, d9}1138; CHECK-NEXT: pop {r4, r5, r7, pc}1139; CHECK-NEXT: .p2align 41140; CHECK-NEXT: @ %bb.1:1141; CHECK-NEXT: .LCPI27_0:1142; CHECK-NEXT: .long 2147483647 @ 0x7fffffff1143; CHECK-NEXT: .long 0 @ 0x01144; CHECK-NEXT: .long 2147483647 @ 0x7fffffff1145; CHECK-NEXT: .long 0 @ 0x01146; CHECK-NEXT: .LCPI27_1:1147; CHECK-NEXT: .long 2147483648 @ 0x800000001148; CHECK-NEXT: .long 4294967295 @ 0xffffffff1149; CHECK-NEXT: .long 2147483648 @ 0x800000001150; CHECK-NEXT: .long 4294967295 @ 0xffffffff1151entry:1152 %conv = fptosi <2 x double> %x to <2 x i64>1153 %spec.store.select = call <2 x i64> @llvm.smin.v2i64(<2 x i64> %conv, <2 x i64> <i64 2147483647, i64 2147483647>)1154 %spec.store.select7 = call <2 x i64> @llvm.smax.v2i64(<2 x i64> %spec.store.select, <2 x i64> <i64 -2147483648, i64 -2147483648>)1155 %conv6 = trunc <2 x i64> %spec.store.select7 to <2 x i32>1156 ret <2 x i32> %conv61157}1158 1159define arm_aapcs_vfpcc <2 x i32> @utest_f64i32_mm(<2 x double> %x) {1160; CHECK-LABEL: utest_f64i32_mm:1161; CHECK: @ %bb.0: @ %entry1162; CHECK-NEXT: .save {r4, r5, r7, lr}1163; CHECK-NEXT: push {r4, r5, r7, lr}1164; CHECK-NEXT: .vsave {d8, d9}1165; CHECK-NEXT: vpush {d8, d9}1166; CHECK-NEXT: vmov q4, q01167; CHECK-NEXT: vmov r0, r1, d81168; CHECK-NEXT: bl __aeabi_d2ulz1169; CHECK-NEXT: mov r4, r01170; CHECK-NEXT: mov r5, r11171; CHECK-NEXT: vmov r0, r1, d91172; CHECK-NEXT: bl __aeabi_d2ulz1173; CHECK-NEXT: subs.w r3, r4, #-11174; CHECK-NEXT: vmov q1[2], q1[0], r4, r01175; CHECK-NEXT: sbcs r3, r5, #01176; CHECK-NEXT: mov.w r2, #01177; CHECK-NEXT: csetm r3, lo1178; CHECK-NEXT: subs.w r0, r0, #-11179; CHECK-NEXT: sbcs r0, r1, #01180; CHECK-NEXT: bfi r2, r3, #0, #81181; CHECK-NEXT: csetm r0, lo1182; CHECK-NEXT: vmov.i64 q0, #0xffffffff1183; CHECK-NEXT: bfi r2, r0, #8, #81184; CHECK-NEXT: vmov q1[3], q1[1], r5, r11185; CHECK-NEXT: vmsr p0, r21186; CHECK-NEXT: vpsel q0, q1, q01187; CHECK-NEXT: vpop {d8, d9}1188; CHECK-NEXT: pop {r4, r5, r7, pc}1189entry:1190 %conv = fptoui <2 x double> %x to <2 x i64>1191 %spec.store.select = call <2 x i64> @llvm.umin.v2i64(<2 x i64> %conv, <2 x i64> <i64 4294967295, i64 4294967295>)1192 %conv6 = trunc <2 x i64> %spec.store.select to <2 x i32>1193 ret <2 x i32> %conv61194}1195 1196define arm_aapcs_vfpcc <2 x i32> @ustest_f64i32_mm(<2 x double> %x) {1197; CHECK-LABEL: ustest_f64i32_mm:1198; CHECK: @ %bb.0: @ %entry1199; CHECK-NEXT: .save {r4, r5, r7, lr}1200; CHECK-NEXT: push {r4, r5, r7, lr}1201; CHECK-NEXT: .vsave {d8, d9}1202; CHECK-NEXT: vpush {d8, d9}1203; CHECK-NEXT: vmov q4, q01204; CHECK-NEXT: vmov r0, r1, d81205; CHECK-NEXT: bl __aeabi_d2lz1206; CHECK-NEXT: mov r4, r01207; CHECK-NEXT: mov r5, r11208; CHECK-NEXT: vmov r0, r1, d91209; CHECK-NEXT: bl __aeabi_d2lz1210; CHECK-NEXT: subs.w r3, r4, #-11211; CHECK-NEXT: vmov q1[2], q1[0], r4, r01212; CHECK-NEXT: sbcs r3, r5, #01213; CHECK-NEXT: vmov q1[3], q1[1], r5, r11214; CHECK-NEXT: csetm r3, lt1215; CHECK-NEXT: subs.w r0, r0, #-11216; CHECK-NEXT: mov.w r5, #01217; CHECK-NEXT: sbcs r0, r1, #01218; CHECK-NEXT: bfi r5, r3, #0, #81219; CHECK-NEXT: csetm r0, lt1220; CHECK-NEXT: bfi r5, r0, #8, #81221; CHECK-NEXT: vmov.i64 q0, #0xffffffff1222; CHECK-NEXT: vmsr p0, r51223; CHECK-NEXT: movs r2, #01224; CHECK-NEXT: vpsel q0, q1, q01225; CHECK-NEXT: vmov.i32 q1, #0x01226; CHECK-NEXT: vmov r0, r1, d01227; CHECK-NEXT: vmov r3, r5, d11228; CHECK-NEXT: rsbs r0, r0, #01229; CHECK-NEXT: sbcs.w r0, r2, r11230; CHECK-NEXT: csetm r0, lt1231; CHECK-NEXT: rsbs r1, r3, #01232; CHECK-NEXT: sbcs.w r1, r2, r51233; CHECK-NEXT: bfi r2, r0, #0, #81234; CHECK-NEXT: csetm r0, lt1235; CHECK-NEXT: bfi r2, r0, #8, #81236; CHECK-NEXT: vmsr p0, r21237; CHECK-NEXT: vpsel q0, q0, q11238; CHECK-NEXT: vpop {d8, d9}1239; CHECK-NEXT: pop {r4, r5, r7, pc}1240entry:1241 %conv = fptosi <2 x double> %x to <2 x i64>1242 %spec.store.select = call <2 x i64> @llvm.smin.v2i64(<2 x i64> %conv, <2 x i64> <i64 4294967295, i64 4294967295>)1243 %spec.store.select7 = call <2 x i64> @llvm.smax.v2i64(<2 x i64> %spec.store.select, <2 x i64> zeroinitializer)1244 %conv6 = trunc <2 x i64> %spec.store.select7 to <2 x i32>1245 ret <2 x i32> %conv61246}1247 1248define arm_aapcs_vfpcc <4 x i32> @stest_f32i32_mm(<4 x float> %x) {1249; CHECK-LABEL: stest_f32i32_mm:1250; CHECK: @ %bb.0: @ %entry1251; CHECK-NEXT: vcvt.s32.f32 q0, q01252; CHECK-NEXT: bx lr1253entry:1254 %conv = fptosi <4 x float> %x to <4 x i64>1255 %spec.store.select = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %conv, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>)1256 %spec.store.select7 = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %spec.store.select, <4 x i64> <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>)1257 %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>1258 ret <4 x i32> %conv61259}1260 1261define arm_aapcs_vfpcc <4 x i32> @utest_f32i32_mm(<4 x float> %x) {1262; CHECK-LABEL: utest_f32i32_mm:1263; CHECK: @ %bb.0: @ %entry1264; CHECK-NEXT: vcvt.u32.f32 q0, q01265; CHECK-NEXT: bx lr1266entry:1267 %conv = fptoui <4 x float> %x to <4 x i64>1268 %spec.store.select = call <4 x i64> @llvm.umin.v4i64(<4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>)1269 %conv6 = trunc <4 x i64> %spec.store.select to <4 x i32>1270 ret <4 x i32> %conv61271}1272 1273define arm_aapcs_vfpcc <4 x i32> @ustest_f32i32_mm(<4 x float> %x) {1274; CHECK-LABEL: ustest_f32i32_mm:1275; CHECK: @ %bb.0: @ %entry1276; CHECK-NEXT: vcvt.u32.f32 q0, q01277; CHECK-NEXT: bx lr1278entry:1279 %conv = fptosi <4 x float> %x to <4 x i64>1280 %spec.store.select = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>)1281 %spec.store.select7 = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %spec.store.select, <4 x i64> zeroinitializer)1282 %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>1283 ret <4 x i32> %conv61284}1285 1286define arm_aapcs_vfpcc <4 x i32> @stest_f16i32_mm(<4 x half> %x) {1287; CHECK-LABEL: stest_f16i32_mm:1288; CHECK: @ %bb.0: @ %entry1289; CHECK-NEXT: .save {r4, r5, r7, lr}1290; CHECK-NEXT: push {r4, r5, r7, lr}1291; CHECK-NEXT: .vsave {d8, d9, d10, d11}1292; CHECK-NEXT: vpush {d8, d9, d10, d11}1293; CHECK-NEXT: vmov.u16 r0, q0[3]1294; CHECK-NEXT: vmov q4, q01295; CHECK-NEXT: bl __fixhfdi1296; CHECK-NEXT: mov r4, r01297; CHECK-NEXT: vmov.u16 r0, q4[0]1298; CHECK-NEXT: bl __fixhfdi1299; CHECK-NEXT: mov r5, r01300; CHECK-NEXT: vmov.u16 r0, q4[2]1301; CHECK-NEXT: bl __fixhfdi1302; CHECK-NEXT: vmov q5[2], q5[0], r5, r01303; CHECK-NEXT: vmov.u16 r0, q4[1]1304; CHECK-NEXT: bl __fixhfdi1305; CHECK-NEXT: vmov q5[3], q5[1], r0, r41306; CHECK-NEXT: vmov q0, q51307; CHECK-NEXT: vpop {d8, d9, d10, d11}1308; CHECK-NEXT: pop {r4, r5, r7, pc}1309entry:1310 %conv = fptosi <4 x half> %x to <4 x i64>1311 %spec.store.select = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %conv, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>)1312 %spec.store.select7 = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %spec.store.select, <4 x i64> <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>)1313 %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>1314 ret <4 x i32> %conv61315}1316 1317define arm_aapcs_vfpcc <4 x i32> @utesth_f16i32_mm(<4 x half> %x) {1318; CHECK-LABEL: utesth_f16i32_mm:1319; CHECK: @ %bb.0: @ %entry1320; CHECK-NEXT: .save {r4, r5, r7, lr}1321; CHECK-NEXT: push {r4, r5, r7, lr}1322; CHECK-NEXT: .vsave {d8, d9, d10, d11}1323; CHECK-NEXT: vpush {d8, d9, d10, d11}1324; CHECK-NEXT: vmov.u16 r0, q0[3]1325; CHECK-NEXT: vmov q4, q01326; CHECK-NEXT: bl __fixunshfdi1327; CHECK-NEXT: mov r4, r01328; CHECK-NEXT: vmov.u16 r0, q4[0]1329; CHECK-NEXT: bl __fixunshfdi1330; CHECK-NEXT: mov r5, r01331; CHECK-NEXT: vmov.u16 r0, q4[2]1332; CHECK-NEXT: bl __fixunshfdi1333; CHECK-NEXT: vmov q5[2], q5[0], r5, r01334; CHECK-NEXT: vmov.u16 r0, q4[1]1335; CHECK-NEXT: bl __fixunshfdi1336; CHECK-NEXT: vmov q5[3], q5[1], r0, r41337; CHECK-NEXT: vmov q0, q51338; CHECK-NEXT: vpop {d8, d9, d10, d11}1339; CHECK-NEXT: pop {r4, r5, r7, pc}1340entry:1341 %conv = fptoui <4 x half> %x to <4 x i64>1342 %spec.store.select = call <4 x i64> @llvm.umin.v4i64(<4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>)1343 %conv6 = trunc <4 x i64> %spec.store.select to <4 x i32>1344 ret <4 x i32> %conv61345}1346 1347define arm_aapcs_vfpcc <4 x i32> @ustest_f16i32_mm(<4 x half> %x) {1348; CHECK-LABEL: ustest_f16i32_mm:1349; CHECK: @ %bb.0: @ %entry1350; CHECK-NEXT: .save {r4, r5, r6, lr}1351; CHECK-NEXT: push {r4, r5, r6, lr}1352; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}1353; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}1354; CHECK-NEXT: vmov.u16 r0, q0[3]1355; CHECK-NEXT: vmov q4, q01356; CHECK-NEXT: bl __fixhfdi1357; CHECK-NEXT: mov r4, r01358; CHECK-NEXT: vmov.u16 r0, q4[2]1359; CHECK-NEXT: mov r5, r11360; CHECK-NEXT: bl __fixhfdi1361; CHECK-NEXT: rsbs r2, r0, #01362; CHECK-NEXT: mov.w r6, #01363; CHECK-NEXT: vmov q0[2], q0[0], r0, r41364; CHECK-NEXT: sbcs.w r0, r6, r11365; CHECK-NEXT: csetm r0, lt1366; CHECK-NEXT: movs r1, #01367; CHECK-NEXT: bfi r1, r0, #0, #81368; CHECK-NEXT: rsbs r0, r4, #01369; CHECK-NEXT: sbcs.w r0, r6, r51370; CHECK-NEXT: vmov.i32 q5, #0x01371; CHECK-NEXT: csetm r0, lt1372; CHECK-NEXT: bfi r1, r0, #8, #81373; CHECK-NEXT: vmov.u16 r0, q4[1]1374; CHECK-NEXT: vmsr p0, r11375; CHECK-NEXT: vpsel q6, q0, q51376; CHECK-NEXT: bl __fixhfdi1377; CHECK-NEXT: mov r4, r01378; CHECK-NEXT: vmov.u16 r0, q4[0]1379; CHECK-NEXT: mov r5, r11380; CHECK-NEXT: bl __fixhfdi1381; CHECK-NEXT: rsbs r2, r0, #01382; CHECK-NEXT: vmov q0[2], q0[0], r0, r41383; CHECK-NEXT: sbcs.w r0, r6, r11384; CHECK-NEXT: csetm r0, lt1385; CHECK-NEXT: rsbs r1, r4, #01386; CHECK-NEXT: sbcs.w r1, r6, r51387; CHECK-NEXT: bfi r6, r0, #0, #81388; CHECK-NEXT: csetm r0, lt1389; CHECK-NEXT: bfi r6, r0, #8, #81390; CHECK-NEXT: vmsr p0, r61391; CHECK-NEXT: vpsel q0, q0, q51392; CHECK-NEXT: vmov.f32 s1, s21393; CHECK-NEXT: vmov.f32 s2, s241394; CHECK-NEXT: vmov.f32 s3, s261395; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}1396; CHECK-NEXT: pop {r4, r5, r6, pc}1397entry:1398 %conv = fptosi <4 x half> %x to <4 x i64>1399 %spec.store.select = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>)1400 %spec.store.select7 = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %spec.store.select, <4 x i64> zeroinitializer)1401 %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>1402 ret <4 x i32> %conv61403}1404 1405; i16 saturate1406 1407define arm_aapcs_vfpcc <2 x i16> @stest_f64i16_mm(<2 x double> %x) {1408; CHECK-LABEL: stest_f64i16_mm:1409; CHECK: @ %bb.0: @ %entry1410; CHECK-NEXT: .save {r4, r5, r7, lr}1411; CHECK-NEXT: push {r4, r5, r7, lr}1412; CHECK-NEXT: .vsave {d8, d9}1413; CHECK-NEXT: vpush {d8, d9}1414; CHECK-NEXT: vmov q4, q01415; CHECK-NEXT: vmov r0, r1, d91416; CHECK-NEXT: bl __aeabi_d2lz1417; CHECK-NEXT: mov r4, r01418; CHECK-NEXT: mov r5, r11419; CHECK-NEXT: vmov r0, r1, d81420; CHECK-NEXT: bl __aeabi_d2lz1421; CHECK-NEXT: vmov q0[2], q0[0], r0, r41422; CHECK-NEXT: movw r4, #327671423; CHECK-NEXT: vmov q0[3], q0[1], r1, r51424; CHECK-NEXT: adr.w r12, .LCPI36_01425; CHECK-NEXT: vmov r1, r2, d01426; CHECK-NEXT: vldrw.u32 q1, [r12]1427; CHECK-NEXT: vmov r3, r5, d11428; CHECK-NEXT: movw lr, #327681429; CHECK-NEXT: movt lr, #655351430; CHECK-NEXT: mov.w r12, #-11431; CHECK-NEXT: movs r0, #01432; CHECK-NEXT: subs r1, r1, r41433; CHECK-NEXT: sbcs r1, r2, #01434; CHECK-NEXT: mov.w r2, #01435; CHECK-NEXT: csetm r1, lt1436; CHECK-NEXT: bfi r2, r1, #0, #81437; CHECK-NEXT: subs r1, r3, r41438; CHECK-NEXT: sbcs r1, r5, #01439; CHECK-NEXT: adr r4, .LCPI36_11440; CHECK-NEXT: csetm r1, lt1441; CHECK-NEXT: bfi r2, r1, #8, #81442; CHECK-NEXT: vmsr p0, r21443; CHECK-NEXT: vpsel q0, q0, q11444; CHECK-NEXT: vldrw.u32 q1, [r4]1445; CHECK-NEXT: vmov r1, r2, d01446; CHECK-NEXT: vmov r3, r5, d11447; CHECK-NEXT: subs.w r1, lr, r11448; CHECK-NEXT: sbcs.w r1, r12, r21449; CHECK-NEXT: csetm r1, lt1450; CHECK-NEXT: bfi r0, r1, #0, #81451; CHECK-NEXT: subs.w r1, lr, r31452; CHECK-NEXT: sbcs.w r1, r12, r51453; CHECK-NEXT: csetm r1, lt1454; CHECK-NEXT: bfi r0, r1, #8, #81455; CHECK-NEXT: vmsr p0, r01456; CHECK-NEXT: vpsel q0, q0, q11457; CHECK-NEXT: vpop {d8, d9}1458; CHECK-NEXT: pop {r4, r5, r7, pc}1459; CHECK-NEXT: .p2align 41460; CHECK-NEXT: @ %bb.1:1461; CHECK-NEXT: .LCPI36_0:1462; CHECK-NEXT: .long 32767 @ 0x7fff1463; CHECK-NEXT: .long 0 @ 0x01464; CHECK-NEXT: .long 32767 @ 0x7fff1465; CHECK-NEXT: .long 0 @ 0x01466; CHECK-NEXT: .LCPI36_1:1467; CHECK-NEXT: .long 4294934528 @ 0xffff80001468; CHECK-NEXT: .long 4294967295 @ 0xffffffff1469; CHECK-NEXT: .long 4294934528 @ 0xffff80001470; CHECK-NEXT: .long 4294967295 @ 0xffffffff1471entry:1472 %conv = fptosi <2 x double> %x to <2 x i32>1473 %spec.store.select = call <2 x i32> @llvm.smin.v2i32(<2 x i32> %conv, <2 x i32> <i32 32767, i32 32767>)1474 %spec.store.select7 = call <2 x i32> @llvm.smax.v2i32(<2 x i32> %spec.store.select, <2 x i32> <i32 -32768, i32 -32768>)1475 %conv6 = trunc <2 x i32> %spec.store.select7 to <2 x i16>1476 ret <2 x i16> %conv61477}1478 1479define arm_aapcs_vfpcc <2 x i16> @utest_f64i16_mm(<2 x double> %x) {1480; CHECK-LABEL: utest_f64i16_mm:1481; CHECK: @ %bb.0: @ %entry1482; CHECK-NEXT: .save {r4, r5, r7, lr}1483; CHECK-NEXT: push {r4, r5, r7, lr}1484; CHECK-NEXT: .vsave {d8, d9}1485; CHECK-NEXT: vpush {d8, d9}1486; CHECK-NEXT: vmov q4, q01487; CHECK-NEXT: vmov r0, r1, d91488; CHECK-NEXT: bl __aeabi_d2ulz1489; CHECK-NEXT: mov r4, r01490; CHECK-NEXT: mov r5, r11491; CHECK-NEXT: vmov r0, r1, d81492; CHECK-NEXT: bl __aeabi_d2ulz1493; CHECK-NEXT: vmov q0[2], q0[0], r0, r41494; CHECK-NEXT: movw r4, #655351495; CHECK-NEXT: vmov q0[3], q0[1], r1, r51496; CHECK-NEXT: movs r5, #01497; CHECK-NEXT: vmov r0, r1, d01498; CHECK-NEXT: vmov.i64 q1, #0xffff1499; CHECK-NEXT: vmov r2, r3, d11500; CHECK-NEXT: subs r0, r0, r41501; CHECK-NEXT: sbcs r0, r1, #01502; CHECK-NEXT: csetm r0, lo1503; CHECK-NEXT: bfi r5, r0, #0, #81504; CHECK-NEXT: subs r0, r2, r41505; CHECK-NEXT: sbcs r0, r3, #01506; CHECK-NEXT: csetm r0, lo1507; CHECK-NEXT: bfi r5, r0, #8, #81508; CHECK-NEXT: vmsr p0, r51509; CHECK-NEXT: vpsel q0, q0, q11510; CHECK-NEXT: vpop {d8, d9}1511; CHECK-NEXT: pop {r4, r5, r7, pc}1512entry:1513 %conv = fptoui <2 x double> %x to <2 x i32>1514 %spec.store.select = call <2 x i32> @llvm.umin.v2i32(<2 x i32> %conv, <2 x i32> <i32 65535, i32 65535>)1515 %conv6 = trunc <2 x i32> %spec.store.select to <2 x i16>1516 ret <2 x i16> %conv61517}1518 1519define arm_aapcs_vfpcc <2 x i16> @ustest_f64i16_mm(<2 x double> %x) {1520; CHECK-LABEL: ustest_f64i16_mm:1521; CHECK: @ %bb.0: @ %entry1522; CHECK-NEXT: .save {r4, r5, r7, lr}1523; CHECK-NEXT: push {r4, r5, r7, lr}1524; CHECK-NEXT: .vsave {d8, d9}1525; CHECK-NEXT: vpush {d8, d9}1526; CHECK-NEXT: vmov q4, q01527; CHECK-NEXT: vmov r0, r1, d91528; CHECK-NEXT: bl __aeabi_d2lz1529; CHECK-NEXT: mov r4, r01530; CHECK-NEXT: mov r5, r11531; CHECK-NEXT: vmov r0, r1, d81532; CHECK-NEXT: bl __aeabi_d2lz1533; CHECK-NEXT: vmov q0[2], q0[0], r0, r41534; CHECK-NEXT: movw r4, #655351535; CHECK-NEXT: vmov q0[3], q0[1], r1, r51536; CHECK-NEXT: vmov.i64 q1, #0xffff1537; CHECK-NEXT: vmov r1, r2, d01538; CHECK-NEXT: movs r0, #01539; CHECK-NEXT: vmov r3, r5, d11540; CHECK-NEXT: subs r1, r1, r41541; CHECK-NEXT: sbcs r1, r2, #01542; CHECK-NEXT: mov.w r2, #01543; CHECK-NEXT: csetm r1, lt1544; CHECK-NEXT: bfi r2, r1, #0, #81545; CHECK-NEXT: subs r1, r3, r41546; CHECK-NEXT: sbcs r1, r5, #01547; CHECK-NEXT: csetm r1, lt1548; CHECK-NEXT: bfi r2, r1, #8, #81549; CHECK-NEXT: vmsr p0, r21550; CHECK-NEXT: vpsel q0, q0, q11551; CHECK-NEXT: vmov.i32 q1, #0x01552; CHECK-NEXT: vmov r1, r2, d01553; CHECK-NEXT: vmov r3, r5, d11554; CHECK-NEXT: rsbs r1, r1, #01555; CHECK-NEXT: sbcs.w r1, r0, r21556; CHECK-NEXT: csetm r1, lt1557; CHECK-NEXT: rsbs r2, r3, #01558; CHECK-NEXT: sbcs.w r2, r0, r51559; CHECK-NEXT: bfi r0, r1, #0, #81560; CHECK-NEXT: csetm r1, lt1561; CHECK-NEXT: bfi r0, r1, #8, #81562; CHECK-NEXT: vmsr p0, r01563; CHECK-NEXT: vpsel q0, q0, q11564; CHECK-NEXT: vpop {d8, d9}1565; CHECK-NEXT: pop {r4, r5, r7, pc}1566entry:1567 %conv = fptosi <2 x double> %x to <2 x i32>1568 %spec.store.select = call <2 x i32> @llvm.smin.v2i32(<2 x i32> %conv, <2 x i32> <i32 65535, i32 65535>)1569 %spec.store.select7 = call <2 x i32> @llvm.smax.v2i32(<2 x i32> %spec.store.select, <2 x i32> zeroinitializer)1570 %conv6 = trunc <2 x i32> %spec.store.select7 to <2 x i16>1571 ret <2 x i16> %conv61572}1573 1574define arm_aapcs_vfpcc <4 x i16> @stest_f32i16_mm(<4 x float> %x) {1575; CHECK-LABEL: stest_f32i16_mm:1576; CHECK: @ %bb.0: @ %entry1577; CHECK-NEXT: vcvt.s32.f32 q0, q01578; CHECK-NEXT: vqmovnb.s32 q0, q01579; CHECK-NEXT: vmovlb.s16 q0, q01580; CHECK-NEXT: bx lr1581entry:1582 %conv = fptosi <4 x float> %x to <4 x i32>1583 %spec.store.select = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %conv, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>)1584 %spec.store.select7 = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %spec.store.select, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>)1585 %conv6 = trunc <4 x i32> %spec.store.select7 to <4 x i16>1586 ret <4 x i16> %conv61587}1588 1589define arm_aapcs_vfpcc <4 x i16> @utest_f32i16_mm(<4 x float> %x) {1590; CHECK-LABEL: utest_f32i16_mm:1591; CHECK: @ %bb.0: @ %entry1592; CHECK-NEXT: vcvt.u32.f32 q0, q01593; CHECK-NEXT: vqmovnb.u32 q0, q01594; CHECK-NEXT: vmovlb.u16 q0, q01595; CHECK-NEXT: bx lr1596entry:1597 %conv = fptoui <4 x float> %x to <4 x i32>1598 %spec.store.select = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %conv, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>)1599 %conv6 = trunc <4 x i32> %spec.store.select to <4 x i16>1600 ret <4 x i16> %conv61601}1602 1603define arm_aapcs_vfpcc <4 x i16> @ustest_f32i16_mm(<4 x float> %x) {1604; CHECK-LABEL: ustest_f32i16_mm:1605; CHECK: @ %bb.0: @ %entry1606; CHECK-NEXT: vmov.i32 q1, #0xffff1607; CHECK-NEXT: vcvt.s32.f32 q0, q01608; CHECK-NEXT: vmov.i32 q2, #0x01609; CHECK-NEXT: vmin.s32 q0, q0, q11610; CHECK-NEXT: vmax.s32 q0, q0, q21611; CHECK-NEXT: bx lr1612entry:1613 %conv = fptosi <4 x float> %x to <4 x i32>1614 %spec.store.select = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %conv, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>)1615 %spec.store.select7 = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %spec.store.select, <4 x i32> zeroinitializer)1616 %conv6 = trunc <4 x i32> %spec.store.select7 to <4 x i16>1617 ret <4 x i16> %conv61618}1619 1620define arm_aapcs_vfpcc <8 x i16> @stest_f16i16_mm(<8 x half> %x) {1621; CHECK-LABEL: stest_f16i16_mm:1622; CHECK: @ %bb.0: @ %entry1623; CHECK-NEXT: vcvt.s16.f16 q0, q01624; CHECK-NEXT: bx lr1625entry:1626 %conv = fptosi <8 x half> %x to <8 x i32>1627 %spec.store.select = call <8 x i32> @llvm.smin.v8i32(<8 x i32> %conv, <8 x i32> <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>)1628 %spec.store.select7 = call <8 x i32> @llvm.smax.v8i32(<8 x i32> %spec.store.select, <8 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768>)1629 %conv6 = trunc <8 x i32> %spec.store.select7 to <8 x i16>1630 ret <8 x i16> %conv61631}1632 1633define arm_aapcs_vfpcc <8 x i16> @utesth_f16i16_mm(<8 x half> %x) {1634; CHECK-LABEL: utesth_f16i16_mm:1635; CHECK: @ %bb.0: @ %entry1636; CHECK-NEXT: vmovx.f16 s6, s21637; CHECK-NEXT: vcvt.u32.f16 s12, s21638; CHECK-NEXT: vmovx.f16 s2, s01639; CHECK-NEXT: vcvt.u32.f16 s0, s01640; CHECK-NEXT: vcvt.u32.f16 s14, s21641; CHECK-NEXT: vmov r0, s01642; CHECK-NEXT: vmovx.f16 s4, s31643; CHECK-NEXT: vmovx.f16 s10, s11644; CHECK-NEXT: vcvt.u32.f16 s8, s31645; CHECK-NEXT: vcvt.u32.f16 s5, s11646; CHECK-NEXT: vmov.16 q0[0], r01647; CHECK-NEXT: vmov r0, s141648; CHECK-NEXT: vmov.16 q0[1], r01649; CHECK-NEXT: vmov r0, s51650; CHECK-NEXT: vcvt.u32.f16 s10, s101651; CHECK-NEXT: vmov.16 q0[2], r01652; CHECK-NEXT: vmov r0, s101653; CHECK-NEXT: vcvt.u32.f16 s6, s61654; CHECK-NEXT: vmov.16 q0[3], r01655; CHECK-NEXT: vmov r0, s121656; CHECK-NEXT: vmov.16 q0[4], r01657; CHECK-NEXT: vmov r0, s61658; CHECK-NEXT: vmov.16 q0[5], r01659; CHECK-NEXT: vmov r0, s81660; CHECK-NEXT: vcvt.u32.f16 s4, s41661; CHECK-NEXT: vmov.16 q0[6], r01662; CHECK-NEXT: vmov r0, s41663; CHECK-NEXT: vmov.16 q0[7], r01664; CHECK-NEXT: bx lr1665entry:1666 %conv = fptoui <8 x half> %x to <8 x i32>1667 %spec.store.select = call <8 x i32> @llvm.umin.v8i32(<8 x i32> %conv, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>)1668 %conv6 = trunc <8 x i32> %spec.store.select to <8 x i16>1669 ret <8 x i16> %conv61670}1671 1672define arm_aapcs_vfpcc <8 x i16> @ustest_f16i16_mm(<8 x half> %x) {1673; CHECK-LABEL: ustest_f16i16_mm:1674; CHECK: @ %bb.0: @ %entry1675; CHECK-NEXT: .vsave {d8, d9}1676; CHECK-NEXT: vpush {d8, d9}1677; CHECK-NEXT: .pad #161678; CHECK-NEXT: sub sp, #161679; CHECK-NEXT: vmovx.f16 s6, s01680; CHECK-NEXT: vcvt.s32.f16 s10, s01681; CHECK-NEXT: vmovx.f16 s0, s31682; CHECK-NEXT: vcvt.s32.f16 s5, s31683; CHECK-NEXT: vcvt.s32.f16 s12, s01684; CHECK-NEXT: vmovx.f16 s0, s21685; CHECK-NEXT: vcvt.s32.f16 s7, s21686; CHECK-NEXT: vcvt.s32.f16 s14, s01687; CHECK-NEXT: vmov r1, s51688; CHECK-NEXT: vmovx.f16 s4, s11689; CHECK-NEXT: vmov r2, s71690; CHECK-NEXT: vcvt.s32.f16 s8, s11691; CHECK-NEXT: vmov q4[2], q4[0], r2, r11692; CHECK-NEXT: vmov r1, s121693; CHECK-NEXT: vmov r2, s141694; CHECK-NEXT: vcvt.s32.f16 s4, s41695; CHECK-NEXT: vmov q4[3], q4[1], r2, r11696; CHECK-NEXT: vcvt.s32.f16 s6, s61697; CHECK-NEXT: vmov r1, s81698; CHECK-NEXT: vmov.i32 q0, #0x01699; CHECK-NEXT: vmov r2, s101700; CHECK-NEXT: mov r0, sp1701; CHECK-NEXT: vmov q2[2], q2[0], r2, r11702; CHECK-NEXT: vmov r1, s41703; CHECK-NEXT: vmov r2, s61704; CHECK-NEXT: vmax.s32 q3, q4, q01705; CHECK-NEXT: vmov q2[3], q2[1], r2, r11706; CHECK-NEXT: vstrh.32 q3, [r0, #8]1707; CHECK-NEXT: vmax.s32 q0, q2, q01708; CHECK-NEXT: vstrh.32 q0, [r0]1709; CHECK-NEXT: vldrw.u32 q0, [r0]1710; CHECK-NEXT: add sp, #161711; CHECK-NEXT: vpop {d8, d9}1712; CHECK-NEXT: bx lr1713entry:1714 %conv = fptosi <8 x half> %x to <8 x i32>1715 %spec.store.select = call <8 x i32> @llvm.smin.v8i32(<8 x i32> %conv, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>)1716 %spec.store.select7 = call <8 x i32> @llvm.smax.v8i32(<8 x i32> %spec.store.select, <8 x i32> zeroinitializer)1717 %conv6 = trunc <8 x i32> %spec.store.select7 to <8 x i16>1718 ret <8 x i16> %conv61719}1720 1721; i64 saturate1722 1723define arm_aapcs_vfpcc <2 x i64> @stest_f64i64_mm(<2 x double> %x) {1724; CHECK-LABEL: stest_f64i64_mm:1725; CHECK: @ %bb.0: @ %entry1726; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, lr}1727; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr}1728; CHECK-NEXT: .pad #41729; CHECK-NEXT: sub sp, #41730; CHECK-NEXT: .vsave {d8, d9}1731; CHECK-NEXT: vpush {d8, d9}1732; CHECK-NEXT: vmov q4, q01733; CHECK-NEXT: vmov r0, r1, d91734; CHECK-NEXT: bl __fixdfti1735; CHECK-NEXT: vmov r12, lr, d81736; CHECK-NEXT: subs.w r5, r0, #-11737; CHECK-NEXT: mvn r4, #-21474836481738; CHECK-NEXT: sbcs.w r5, r1, r41739; CHECK-NEXT: sbcs r5, r2, #01740; CHECK-NEXT: mov.w r6, #-11741; CHECK-NEXT: sbcs r5, r3, #01742; CHECK-NEXT: cset r5, lt1743; CHECK-NEXT: cmp r5, #01744; CHECK-NEXT: csel r0, r0, r6, ne1745; CHECK-NEXT: csel r3, r3, r5, ne1746; CHECK-NEXT: csel r2, r2, r5, ne1747; CHECK-NEXT: csel r1, r1, r4, ne1748; CHECK-NEXT: rsbs r7, r0, #01749; CHECK-NEXT: mov.w r5, #-21474836481750; CHECK-NEXT: sbcs.w r7, r5, r11751; CHECK-NEXT: sbcs.w r2, r6, r21752; CHECK-NEXT: sbcs.w r2, r6, r31753; CHECK-NEXT: cset r2, lt1754; CHECK-NEXT: cmp r2, #01755; CHECK-NEXT: csel r9, r0, r2, ne1756; CHECK-NEXT: csel r8, r1, r5, ne1757; CHECK-NEXT: mov r0, r121758; CHECK-NEXT: mov r1, lr1759; CHECK-NEXT: bl __fixdfti1760; CHECK-NEXT: subs.w r7, r0, #-11761; CHECK-NEXT: sbcs.w r7, r1, r41762; CHECK-NEXT: sbcs r7, r2, #01763; CHECK-NEXT: sbcs r7, r3, #01764; CHECK-NEXT: cset r7, lt1765; CHECK-NEXT: cmp r7, #01766; CHECK-NEXT: csel r0, r0, r6, ne1767; CHECK-NEXT: csel r3, r3, r7, ne1768; CHECK-NEXT: csel r2, r2, r7, ne1769; CHECK-NEXT: csel r1, r1, r4, ne1770; CHECK-NEXT: rsbs r7, r0, #01771; CHECK-NEXT: sbcs.w r7, r5, r11772; CHECK-NEXT: sbcs.w r2, r6, r21773; CHECK-NEXT: sbcs.w r2, r6, r31774; CHECK-NEXT: cset r2, lt1775; CHECK-NEXT: cmp r2, #01776; CHECK-NEXT: csel r0, r0, r2, ne1777; CHECK-NEXT: csel r1, r1, r5, ne1778; CHECK-NEXT: vmov q0[2], q0[0], r0, r91779; CHECK-NEXT: vmov q0[3], q0[1], r1, r81780; CHECK-NEXT: vpop {d8, d9}1781; CHECK-NEXT: add sp, #41782; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc}1783entry:1784 %conv = fptosi <2 x double> %x to <2 x i128>1785 %spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807>)1786 %spec.store.select7 = call <2 x i128> @llvm.smax.v2i128(<2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808>)1787 %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>1788 ret <2 x i64> %conv61789}1790 1791define arm_aapcs_vfpcc <2 x i64> @utest_f64i64_mm(<2 x double> %x) {1792; CHECK-LABEL: utest_f64i64_mm:1793; CHECK: @ %bb.0: @ %entry1794; CHECK-NEXT: .save {r4, r5, r7, lr}1795; CHECK-NEXT: push {r4, r5, r7, lr}1796; CHECK-NEXT: .vsave {d8, d9}1797; CHECK-NEXT: vpush {d8, d9}1798; CHECK-NEXT: vmov q4, q01799; CHECK-NEXT: vmov r0, r1, d91800; CHECK-NEXT: bl __fixunsdfti1801; CHECK-NEXT: vmov r12, lr, d81802; CHECK-NEXT: subs r2, #11803; CHECK-NEXT: sbcs r2, r3, #01804; CHECK-NEXT: cset r2, lo1805; CHECK-NEXT: cmp r2, #01806; CHECK-NEXT: csel r4, r1, r2, ne1807; CHECK-NEXT: csel r5, r0, r2, ne1808; CHECK-NEXT: mov r0, r121809; CHECK-NEXT: mov r1, lr1810; CHECK-NEXT: bl __fixunsdfti1811; CHECK-NEXT: subs r2, #11812; CHECK-NEXT: sbcs r2, r3, #01813; CHECK-NEXT: cset r2, lo1814; CHECK-NEXT: cmp r2, #01815; CHECK-NEXT: csel r0, r0, r2, ne1816; CHECK-NEXT: csel r1, r1, r2, ne1817; CHECK-NEXT: vmov q0[2], q0[0], r0, r51818; CHECK-NEXT: vmov q0[3], q0[1], r1, r41819; CHECK-NEXT: vpop {d8, d9}1820; CHECK-NEXT: pop {r4, r5, r7, pc}1821entry:1822 %conv = fptoui <2 x double> %x to <2 x i128>1823 %spec.store.select = call <2 x i128> @llvm.umin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)1824 %conv6 = trunc <2 x i128> %spec.store.select to <2 x i64>1825 ret <2 x i64> %conv61826}1827 1828define arm_aapcs_vfpcc <2 x i64> @ustest_f64i64_mm(<2 x double> %x) {1829; CHECK-LABEL: ustest_f64i64_mm:1830; CHECK: @ %bb.0: @ %entry1831; CHECK-NEXT: .save {r4, r5, r7, lr}1832; CHECK-NEXT: push {r4, r5, r7, lr}1833; CHECK-NEXT: .vsave {d8, d9}1834; CHECK-NEXT: vpush {d8, d9}1835; CHECK-NEXT: vmov q4, q01836; CHECK-NEXT: vmov r0, r1, d91837; CHECK-NEXT: bl __fixdfti1838; CHECK-NEXT: vmov r12, lr, d81839; CHECK-NEXT: subs r2, #11840; CHECK-NEXT: sbcs r2, r3, #01841; CHECK-NEXT: cset r2, lt1842; CHECK-NEXT: cmp r2, #01843; CHECK-NEXT: csel r5, r0, r2, ne1844; CHECK-NEXT: csel r0, r3, r2, ne1845; CHECK-NEXT: csel r4, r1, r2, ne1846; CHECK-NEXT: cmp r0, #01847; CHECK-NEXT: itt mi1848; CHECK-NEXT: movmi r4, #01849; CHECK-NEXT: movmi r5, #01850; CHECK-NEXT: mov r0, r121851; CHECK-NEXT: mov r1, lr1852; CHECK-NEXT: bl __fixdfti1853; CHECK-NEXT: subs r2, #11854; CHECK-NEXT: sbcs r2, r3, #01855; CHECK-NEXT: cset r2, lt1856; CHECK-NEXT: cmp r2, #01857; CHECK-NEXT: csel r1, r1, r2, ne1858; CHECK-NEXT: csel r0, r0, r2, ne1859; CHECK-NEXT: csel r2, r3, r2, ne1860; CHECK-NEXT: cmp r2, #01861; CHECK-NEXT: itt mi1862; CHECK-NEXT: movmi r0, #01863; CHECK-NEXT: movmi r1, #01864; CHECK-NEXT: vmov q0[2], q0[0], r0, r51865; CHECK-NEXT: vmov q0[3], q0[1], r1, r41866; CHECK-NEXT: vpop {d8, d9}1867; CHECK-NEXT: pop {r4, r5, r7, pc}1868entry:1869 %conv = fptosi <2 x double> %x to <2 x i128>1870 %spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)1871 %spec.store.select7 = call <2 x i128> @llvm.smax.v2i128(<2 x i128> %spec.store.select, <2 x i128> zeroinitializer)1872 %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>1873 ret <2 x i64> %conv61874}1875 1876define arm_aapcs_vfpcc <2 x i64> @stest_f32i64_mm(<2 x float> %x) {1877; CHECK-LABEL: stest_f32i64_mm:1878; CHECK: @ %bb.0: @ %entry1879; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}1880; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, lr}1881; CHECK-NEXT: vmov r8, r0, d01882; CHECK-NEXT: bl __fixsfti1883; CHECK-NEXT: subs.w r7, r0, #-11884; CHECK-NEXT: mvn r5, #-21474836481885; CHECK-NEXT: sbcs.w r7, r1, r51886; CHECK-NEXT: mov.w r6, #-21474836481887; CHECK-NEXT: sbcs r7, r2, #01888; CHECK-NEXT: sbcs r7, r3, #01889; CHECK-NEXT: cset r7, lt1890; CHECK-NEXT: cmp r7, #01891; CHECK-NEXT: csel r3, r3, r7, ne1892; CHECK-NEXT: csel r2, r2, r7, ne1893; CHECK-NEXT: mov.w r7, #-11894; CHECK-NEXT: csel r1, r1, r5, ne1895; CHECK-NEXT: csel r0, r0, r7, ne1896; CHECK-NEXT: rsbs r4, r0, #01897; CHECK-NEXT: sbcs.w r4, r6, r11898; CHECK-NEXT: sbcs.w r2, r7, r21899; CHECK-NEXT: sbcs.w r2, r7, r31900; CHECK-NEXT: cset r2, lt1901; CHECK-NEXT: cmp r2, #01902; CHECK-NEXT: csel r10, r0, r2, ne1903; CHECK-NEXT: mov r0, r81904; CHECK-NEXT: csel r9, r1, r6, ne1905; CHECK-NEXT: bl __fixsfti1906; CHECK-NEXT: subs.w r4, r0, #-11907; CHECK-NEXT: sbcs.w r4, r1, r51908; CHECK-NEXT: sbcs r4, r2, #01909; CHECK-NEXT: sbcs r4, r3, #01910; CHECK-NEXT: cset r4, lt1911; CHECK-NEXT: cmp r4, #01912; CHECK-NEXT: csel r0, r0, r7, ne1913; CHECK-NEXT: csel r3, r3, r4, ne1914; CHECK-NEXT: csel r2, r2, r4, ne1915; CHECK-NEXT: csel r1, r1, r5, ne1916; CHECK-NEXT: rsbs r5, r0, #01917; CHECK-NEXT: sbcs.w r5, r6, r11918; CHECK-NEXT: sbcs.w r2, r7, r21919; CHECK-NEXT: sbcs.w r2, r7, r31920; CHECK-NEXT: cset r2, lt1921; CHECK-NEXT: cmp r2, #01922; CHECK-NEXT: csel r0, r0, r2, ne1923; CHECK-NEXT: csel r1, r1, r6, ne1924; CHECK-NEXT: vmov q0[2], q0[0], r0, r101925; CHECK-NEXT: vmov q0[3], q0[1], r1, r91926; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, pc}1927entry:1928 %conv = fptosi <2 x float> %x to <2 x i128>1929 %spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807>)1930 %spec.store.select7 = call <2 x i128> @llvm.smax.v2i128(<2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808>)1931 %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>1932 ret <2 x i64> %conv61933}1934 1935define arm_aapcs_vfpcc <2 x i64> @utest_f32i64_mm(<2 x float> %x) {1936; CHECK-LABEL: utest_f32i64_mm:1937; CHECK: @ %bb.0: @ %entry1938; CHECK-NEXT: .save {r4, r5, r6, lr}1939; CHECK-NEXT: push {r4, r5, r6, lr}1940; CHECK-NEXT: vmov r4, r0, d01941; CHECK-NEXT: bl __fixunssfti1942; CHECK-NEXT: subs r2, #11943; CHECK-NEXT: sbcs r2, r3, #01944; CHECK-NEXT: cset r2, lo1945; CHECK-NEXT: cmp r2, #01946; CHECK-NEXT: csel r6, r0, r2, ne1947; CHECK-NEXT: mov r0, r41948; CHECK-NEXT: csel r5, r1, r2, ne1949; CHECK-NEXT: bl __fixunssfti1950; CHECK-NEXT: subs r2, #11951; CHECK-NEXT: sbcs r2, r3, #01952; CHECK-NEXT: cset r2, lo1953; CHECK-NEXT: cmp r2, #01954; CHECK-NEXT: csel r0, r0, r2, ne1955; CHECK-NEXT: csel r1, r1, r2, ne1956; CHECK-NEXT: vmov q0[2], q0[0], r0, r61957; CHECK-NEXT: vmov q0[3], q0[1], r1, r51958; CHECK-NEXT: pop {r4, r5, r6, pc}1959entry:1960 %conv = fptoui <2 x float> %x to <2 x i128>1961 %spec.store.select = call <2 x i128> @llvm.umin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)1962 %conv6 = trunc <2 x i128> %spec.store.select to <2 x i64>1963 ret <2 x i64> %conv61964}1965 1966define arm_aapcs_vfpcc <2 x i64> @ustest_f32i64_mm(<2 x float> %x) {1967; CHECK-LABEL: ustest_f32i64_mm:1968; CHECK: @ %bb.0: @ %entry1969; CHECK-NEXT: .save {r4, r5, r6, lr}1970; CHECK-NEXT: push {r4, r5, r6, lr}1971; CHECK-NEXT: vmov r4, r0, d01972; CHECK-NEXT: bl __fixsfti1973; CHECK-NEXT: subs r2, #11974; CHECK-NEXT: sbcs r2, r3, #01975; CHECK-NEXT: cset r2, lt1976; CHECK-NEXT: cmp r2, #01977; CHECK-NEXT: csel r6, r0, r2, ne1978; CHECK-NEXT: csel r0, r3, r2, ne1979; CHECK-NEXT: csel r5, r1, r2, ne1980; CHECK-NEXT: cmp r0, #01981; CHECK-NEXT: mov r0, r41982; CHECK-NEXT: itt mi1983; CHECK-NEXT: movmi r5, #01984; CHECK-NEXT: movmi r6, #01985; CHECK-NEXT: bl __fixsfti1986; CHECK-NEXT: subs r2, #11987; CHECK-NEXT: sbcs r2, r3, #01988; CHECK-NEXT: cset r2, lt1989; CHECK-NEXT: cmp r2, #01990; CHECK-NEXT: csel r1, r1, r2, ne1991; CHECK-NEXT: csel r0, r0, r2, ne1992; CHECK-NEXT: csel r2, r3, r2, ne1993; CHECK-NEXT: cmp r2, #01994; CHECK-NEXT: itt mi1995; CHECK-NEXT: movmi r0, #01996; CHECK-NEXT: movmi r1, #01997; CHECK-NEXT: vmov q0[2], q0[0], r0, r61998; CHECK-NEXT: vmov q0[3], q0[1], r1, r51999; CHECK-NEXT: pop {r4, r5, r6, pc}2000entry:2001 %conv = fptosi <2 x float> %x to <2 x i128>2002 %spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)2003 %spec.store.select7 = call <2 x i128> @llvm.smax.v2i128(<2 x i128> %spec.store.select, <2 x i128> zeroinitializer)2004 %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>2005 ret <2 x i64> %conv62006}2007 2008define arm_aapcs_vfpcc <2 x i64> @stest_f16i64_mm(<2 x half> %x) {2009; CHECK-LABEL: stest_f16i64_mm:2010; CHECK: @ %bb.0: @ %entry2011; CHECK-NEXT: .save {r4, r5, r7, lr}2012; CHECK-NEXT: push {r4, r5, r7, lr}2013; CHECK-NEXT: .vsave {d8, d9}2014; CHECK-NEXT: vpush {d8, d9}2015; CHECK-NEXT: vmov.u16 r0, q0[1]2016; CHECK-NEXT: vmov q4, q02017; CHECK-NEXT: bl __fixhfti2018; CHECK-NEXT: mov r4, r02019; CHECK-NEXT: vmov.u16 r0, q4[0]2020; CHECK-NEXT: mov r5, r12021; CHECK-NEXT: bl __fixhfti2022; CHECK-NEXT: vmov q0[2], q0[0], r0, r42023; CHECK-NEXT: vmov q0[3], q0[1], r1, r52024; CHECK-NEXT: vpop {d8, d9}2025; CHECK-NEXT: pop {r4, r5, r7, pc}2026entry:2027 %conv = fptosi <2 x half> %x to <2 x i128>2028 %spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807>)2029 %spec.store.select7 = call <2 x i128> @llvm.smax.v2i128(<2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808>)2030 %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>2031 ret <2 x i64> %conv62032}2033 2034define arm_aapcs_vfpcc <2 x i64> @utesth_f16i64_mm(<2 x half> %x) {2035; CHECK-LABEL: utesth_f16i64_mm:2036; CHECK: @ %bb.0: @ %entry2037; CHECK-NEXT: .save {r4, r5, r7, lr}2038; CHECK-NEXT: push {r4, r5, r7, lr}2039; CHECK-NEXT: .vsave {d8, d9}2040; CHECK-NEXT: vpush {d8, d9}2041; CHECK-NEXT: vmov.u16 r0, q0[1]2042; CHECK-NEXT: vmov q4, q02043; CHECK-NEXT: bl __fixunshfti2044; CHECK-NEXT: mov r4, r02045; CHECK-NEXT: vmov.u16 r0, q4[0]2046; CHECK-NEXT: mov r5, r12047; CHECK-NEXT: bl __fixunshfti2048; CHECK-NEXT: vmov q0[2], q0[0], r0, r42049; CHECK-NEXT: vmov q0[3], q0[1], r1, r52050; CHECK-NEXT: vpop {d8, d9}2051; CHECK-NEXT: pop {r4, r5, r7, pc}2052entry:2053 %conv = fptoui <2 x half> %x to <2 x i128>2054 %spec.store.select = call <2 x i128> @llvm.umin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)2055 %conv6 = trunc <2 x i128> %spec.store.select to <2 x i64>2056 ret <2 x i64> %conv62057}2058 2059define arm_aapcs_vfpcc <2 x i64> @ustest_f16i64_mm(<2 x half> %x) {2060; CHECK-LABEL: ustest_f16i64_mm:2061; CHECK: @ %bb.0: @ %entry2062; CHECK-NEXT: .save {r4, r5, r7, lr}2063; CHECK-NEXT: push {r4, r5, r7, lr}2064; CHECK-NEXT: .vsave {d8, d9}2065; CHECK-NEXT: vpush {d8, d9}2066; CHECK-NEXT: vmov.u16 r0, q0[1]2067; CHECK-NEXT: vmov q4, q02068; CHECK-NEXT: bl __fixhfti2069; CHECK-NEXT: mov r4, r02070; CHECK-NEXT: vmov.u16 r0, q4[0]2071; CHECK-NEXT: mov r5, r12072; CHECK-NEXT: cmp r3, #02073; CHECK-NEXT: itt mi2074; CHECK-NEXT: movmi r5, #02075; CHECK-NEXT: movmi r4, #02076; CHECK-NEXT: bl __fixhfti2077; CHECK-NEXT: cmp r3, #02078; CHECK-NEXT: itt mi2079; CHECK-NEXT: movmi r0, #02080; CHECK-NEXT: movmi r1, #02081; CHECK-NEXT: vmov q0[2], q0[0], r0, r42082; CHECK-NEXT: vmov q0[3], q0[1], r1, r52083; CHECK-NEXT: vpop {d8, d9}2084; CHECK-NEXT: pop {r4, r5, r7, pc}2085entry:2086 %conv = fptosi <2 x half> %x to <2 x i128>2087 %spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)2088 %spec.store.select7 = call <2 x i128> @llvm.smax.v2i128(<2 x i128> %spec.store.select, <2 x i128> zeroinitializer)2089 %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>2090 ret <2 x i64> %conv62091}2092 2093declare <2 x i32> @llvm.smin.v2i32(<2 x i32>, <2 x i32>)2094declare <2 x i32> @llvm.smax.v2i32(<2 x i32>, <2 x i32>)2095declare <2 x i32> @llvm.umin.v2i32(<2 x i32>, <2 x i32>)2096declare <4 x i32> @llvm.smin.v4i32(<4 x i32>, <4 x i32>)2097declare <4 x i32> @llvm.smax.v4i32(<4 x i32>, <4 x i32>)2098declare <4 x i32> @llvm.umin.v4i32(<4 x i32>, <4 x i32>)2099declare <8 x i32> @llvm.smin.v8i32(<8 x i32>, <8 x i32>)2100declare <8 x i32> @llvm.smax.v8i32(<8 x i32>, <8 x i32>)2101declare <8 x i32> @llvm.umin.v8i32(<8 x i32>, <8 x i32>)2102declare <2 x i64> @llvm.smin.v2i64(<2 x i64>, <2 x i64>)2103declare <2 x i64> @llvm.smax.v2i64(<2 x i64>, <2 x i64>)2104declare <2 x i64> @llvm.umin.v2i64(<2 x i64>, <2 x i64>)2105declare <4 x i64> @llvm.smin.v4i64(<4 x i64>, <4 x i64>)2106declare <4 x i64> @llvm.smax.v4i64(<4 x i64>, <4 x i64>)2107declare <4 x i64> @llvm.umin.v4i64(<4 x i64>, <4 x i64>)2108declare <2 x i128> @llvm.smin.v2i128(<2 x i128>, <2 x i128>)2109declare <2 x i128> @llvm.smax.v2i128(<2 x i128>, <2 x i128>)2110declare <2 x i128> @llvm.umin.v2i128(<2 x i128>, <2 x i128>)2111