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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE3; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP4 5define arm_aapcs_vfpcc <4 x float> @fceil_float32_t(<4 x float> %src) {6; CHECK-MVE-LABEL: fceil_float32_t:7; CHECK-MVE: @ %bb.0: @ %entry8; CHECK-MVE-NEXT: vrintp.f32 s3, s39; CHECK-MVE-NEXT: vrintp.f32 s2, s210; CHECK-MVE-NEXT: vrintp.f32 s1, s111; CHECK-MVE-NEXT: vrintp.f32 s0, s012; CHECK-MVE-NEXT: bx lr13;14; CHECK-MVEFP-LABEL: fceil_float32_t:15; CHECK-MVEFP: @ %bb.0: @ %entry16; CHECK-MVEFP-NEXT: vrintp.f32 q0, q017; CHECK-MVEFP-NEXT: bx lr18entry:19 %0 = call fast <4 x float> @llvm.ceil.v4f32(<4 x float> %src)20 ret <4 x float> %021}22 23define arm_aapcs_vfpcc <8 x half> @fceil_float16_t(<8 x half> %src) {24; CHECK-MVE-LABEL: fceil_float16_t:25; CHECK-MVE: @ %bb.0: @ %entry26; CHECK-MVE-NEXT: vmovx.f16 s4, s027; CHECK-MVE-NEXT: vrintp.f16 s0, s028; CHECK-MVE-NEXT: vrintp.f16 s4, s429; CHECK-MVE-NEXT: vins.f16 s0, s430; CHECK-MVE-NEXT: vmovx.f16 s4, s131; CHECK-MVE-NEXT: vrintp.f16 s4, s432; CHECK-MVE-NEXT: vrintp.f16 s1, s133; CHECK-MVE-NEXT: vins.f16 s1, s434; CHECK-MVE-NEXT: vmovx.f16 s4, s235; CHECK-MVE-NEXT: vrintp.f16 s4, s436; CHECK-MVE-NEXT: vrintp.f16 s2, s237; CHECK-MVE-NEXT: vins.f16 s2, s438; CHECK-MVE-NEXT: vmovx.f16 s4, s339; CHECK-MVE-NEXT: vrintp.f16 s4, s440; CHECK-MVE-NEXT: vrintp.f16 s3, s341; CHECK-MVE-NEXT: vins.f16 s3, s442; CHECK-MVE-NEXT: bx lr43;44; CHECK-MVEFP-LABEL: fceil_float16_t:45; CHECK-MVEFP: @ %bb.0: @ %entry46; CHECK-MVEFP-NEXT: vrintp.f16 q0, q047; CHECK-MVEFP-NEXT: bx lr48entry:49 %0 = call fast <8 x half> @llvm.ceil.v8f16(<8 x half> %src)50 ret <8 x half> %051}52 53define arm_aapcs_vfpcc <2 x double> @fceil_float64_t(<2 x double> %src) {54; CHECK-LABEL: fceil_float64_t:55; CHECK: @ %bb.0: @ %entry56; CHECK-NEXT: .save {r7, lr}57; CHECK-NEXT: push {r7, lr}58; CHECK-NEXT: .vsave {d8, d9}59; CHECK-NEXT: vpush {d8, d9}60; CHECK-NEXT: vmov q4, q061; CHECK-NEXT: vmov r0, r1, d962; CHECK-NEXT: bl ceil63; CHECK-NEXT: vmov r2, r3, d864; CHECK-NEXT: vmov d9, r0, r165; CHECK-NEXT: mov r0, r266; CHECK-NEXT: mov r1, r367; CHECK-NEXT: bl ceil68; CHECK-NEXT: vmov d8, r0, r169; CHECK-NEXT: vmov q0, q470; CHECK-NEXT: vpop {d8, d9}71; CHECK-NEXT: pop {r7, pc}72entry:73 %0 = call fast <2 x double> @llvm.ceil.v2f64(<2 x double> %src)74 ret <2 x double> %075}76 77define arm_aapcs_vfpcc <4 x float> @ftrunc_float32_t(<4 x float> %src) {78; CHECK-MVE-LABEL: ftrunc_float32_t:79; CHECK-MVE: @ %bb.0: @ %entry80; CHECK-MVE-NEXT: vrintz.f32 s3, s381; CHECK-MVE-NEXT: vrintz.f32 s2, s282; CHECK-MVE-NEXT: vrintz.f32 s1, s183; CHECK-MVE-NEXT: vrintz.f32 s0, s084; CHECK-MVE-NEXT: bx lr85;86; CHECK-MVEFP-LABEL: ftrunc_float32_t:87; CHECK-MVEFP: @ %bb.0: @ %entry88; CHECK-MVEFP-NEXT: vrintz.f32 q0, q089; CHECK-MVEFP-NEXT: bx lr90entry:91 %0 = call fast <4 x float> @llvm.trunc.v4f32(<4 x float> %src)92 ret <4 x float> %093}94 95define arm_aapcs_vfpcc <8 x half> @ftrunc_float16_t(<8 x half> %src) {96; CHECK-MVE-LABEL: ftrunc_float16_t:97; CHECK-MVE: @ %bb.0: @ %entry98; CHECK-MVE-NEXT: vmovx.f16 s4, s099; CHECK-MVE-NEXT: vrintz.f16 s0, s0100; CHECK-MVE-NEXT: vrintz.f16 s4, s4101; CHECK-MVE-NEXT: vins.f16 s0, s4102; CHECK-MVE-NEXT: vmovx.f16 s4, s1103; CHECK-MVE-NEXT: vrintz.f16 s4, s4104; CHECK-MVE-NEXT: vrintz.f16 s1, s1105; CHECK-MVE-NEXT: vins.f16 s1, s4106; CHECK-MVE-NEXT: vmovx.f16 s4, s2107; CHECK-MVE-NEXT: vrintz.f16 s4, s4108; CHECK-MVE-NEXT: vrintz.f16 s2, s2109; CHECK-MVE-NEXT: vins.f16 s2, s4110; CHECK-MVE-NEXT: vmovx.f16 s4, s3111; CHECK-MVE-NEXT: vrintz.f16 s4, s4112; CHECK-MVE-NEXT: vrintz.f16 s3, s3113; CHECK-MVE-NEXT: vins.f16 s3, s4114; CHECK-MVE-NEXT: bx lr115;116; CHECK-MVEFP-LABEL: ftrunc_float16_t:117; CHECK-MVEFP: @ %bb.0: @ %entry118; CHECK-MVEFP-NEXT: vrintz.f16 q0, q0119; CHECK-MVEFP-NEXT: bx lr120entry:121 %0 = call fast <8 x half> @llvm.trunc.v8f16(<8 x half> %src)122 ret <8 x half> %0123}124 125define arm_aapcs_vfpcc <2 x double> @ftrunc_float64_t(<2 x double> %src) {126; CHECK-LABEL: ftrunc_float64_t:127; CHECK: @ %bb.0: @ %entry128; CHECK-NEXT: .save {r7, lr}129; CHECK-NEXT: push {r7, lr}130; CHECK-NEXT: .vsave {d8, d9}131; CHECK-NEXT: vpush {d8, d9}132; CHECK-NEXT: vmov q4, q0133; CHECK-NEXT: vmov r0, r1, d9134; CHECK-NEXT: bl trunc135; CHECK-NEXT: vmov r2, r3, d8136; CHECK-NEXT: vmov d9, r0, r1137; CHECK-NEXT: mov r0, r2138; CHECK-NEXT: mov r1, r3139; CHECK-NEXT: bl trunc140; CHECK-NEXT: vmov d8, r0, r1141; CHECK-NEXT: vmov q0, q4142; CHECK-NEXT: vpop {d8, d9}143; CHECK-NEXT: pop {r7, pc}144entry:145 %0 = call fast <2 x double> @llvm.trunc.v2f64(<2 x double> %src)146 ret <2 x double> %0147}148 149define arm_aapcs_vfpcc <4 x float> @frint_float32_t(<4 x float> %src) {150; CHECK-MVE-LABEL: frint_float32_t:151; CHECK-MVE: @ %bb.0: @ %entry152; CHECK-MVE-NEXT: vrintx.f32 s3, s3153; CHECK-MVE-NEXT: vrintx.f32 s2, s2154; CHECK-MVE-NEXT: vrintx.f32 s1, s1155; CHECK-MVE-NEXT: vrintx.f32 s0, s0156; CHECK-MVE-NEXT: bx lr157;158; CHECK-MVEFP-LABEL: frint_float32_t:159; CHECK-MVEFP: @ %bb.0: @ %entry160; CHECK-MVEFP-NEXT: vrintx.f32 q0, q0161; CHECK-MVEFP-NEXT: bx lr162entry:163 %0 = call fast <4 x float> @llvm.rint.v4f32(<4 x float> %src)164 ret <4 x float> %0165}166 167define arm_aapcs_vfpcc <8 x half> @frint_float16_t(<8 x half> %src) {168; CHECK-MVE-LABEL: frint_float16_t:169; CHECK-MVE: @ %bb.0: @ %entry170; CHECK-MVE-NEXT: vmovx.f16 s4, s0171; CHECK-MVE-NEXT: vrintx.f16 s0, s0172; CHECK-MVE-NEXT: vrintx.f16 s4, s4173; CHECK-MVE-NEXT: vins.f16 s0, s4174; CHECK-MVE-NEXT: vmovx.f16 s4, s1175; CHECK-MVE-NEXT: vrintx.f16 s4, s4176; CHECK-MVE-NEXT: vrintx.f16 s1, s1177; CHECK-MVE-NEXT: vins.f16 s1, s4178; CHECK-MVE-NEXT: vmovx.f16 s4, s2179; CHECK-MVE-NEXT: vrintx.f16 s4, s4180; CHECK-MVE-NEXT: vrintx.f16 s2, s2181; CHECK-MVE-NEXT: vins.f16 s2, s4182; CHECK-MVE-NEXT: vmovx.f16 s4, s3183; CHECK-MVE-NEXT: vrintx.f16 s4, s4184; CHECK-MVE-NEXT: vrintx.f16 s3, s3185; CHECK-MVE-NEXT: vins.f16 s3, s4186; CHECK-MVE-NEXT: bx lr187;188; CHECK-MVEFP-LABEL: frint_float16_t:189; CHECK-MVEFP: @ %bb.0: @ %entry190; CHECK-MVEFP-NEXT: vrintx.f16 q0, q0191; CHECK-MVEFP-NEXT: bx lr192entry:193 %0 = call fast <8 x half> @llvm.rint.v8f16(<8 x half> %src)194 ret <8 x half> %0195}196 197define arm_aapcs_vfpcc <2 x double> @frint_float64_t(<2 x double> %src) {198; CHECK-LABEL: frint_float64_t:199; CHECK: @ %bb.0: @ %entry200; CHECK-NEXT: .save {r7, lr}201; CHECK-NEXT: push {r7, lr}202; CHECK-NEXT: .vsave {d8, d9}203; CHECK-NEXT: vpush {d8, d9}204; CHECK-NEXT: vmov q4, q0205; CHECK-NEXT: vmov r0, r1, d9206; CHECK-NEXT: bl rint207; CHECK-NEXT: vmov r2, r3, d8208; CHECK-NEXT: vmov d9, r0, r1209; CHECK-NEXT: mov r0, r2210; CHECK-NEXT: mov r1, r3211; CHECK-NEXT: bl rint212; CHECK-NEXT: vmov d8, r0, r1213; CHECK-NEXT: vmov q0, q4214; CHECK-NEXT: vpop {d8, d9}215; CHECK-NEXT: pop {r7, pc}216entry:217 %0 = call fast <2 x double> @llvm.rint.v2f64(<2 x double> %src)218 ret <2 x double> %0219}220 221define arm_aapcs_vfpcc <4 x float> @fnearbyint_float32_t(<4 x float> %src) {222; CHECK-LABEL: fnearbyint_float32_t:223; CHECK: @ %bb.0: @ %entry224; CHECK-NEXT: vrintr.f32 s3, s3225; CHECK-NEXT: vrintr.f32 s2, s2226; CHECK-NEXT: vrintr.f32 s1, s1227; CHECK-NEXT: vrintr.f32 s0, s0228; CHECK-NEXT: bx lr229entry:230 %0 = call fast <4 x float> @llvm.nearbyint.v4f32(<4 x float> %src)231 ret <4 x float> %0232}233 234define arm_aapcs_vfpcc <8 x half> @fnearbyint_float16_t(<8 x half> %src) {235; CHECK-LABEL: fnearbyint_float16_t:236; CHECK: @ %bb.0: @ %entry237; CHECK-NEXT: vmovx.f16 s4, s0238; CHECK-NEXT: vrintr.f16 s0, s0239; CHECK-NEXT: vrintr.f16 s4, s4240; CHECK-NEXT: vins.f16 s0, s4241; CHECK-NEXT: vmovx.f16 s4, s1242; CHECK-NEXT: vrintr.f16 s4, s4243; CHECK-NEXT: vrintr.f16 s1, s1244; CHECK-NEXT: vins.f16 s1, s4245; CHECK-NEXT: vmovx.f16 s4, s2246; CHECK-NEXT: vrintr.f16 s4, s4247; CHECK-NEXT: vrintr.f16 s2, s2248; CHECK-NEXT: vins.f16 s2, s4249; CHECK-NEXT: vmovx.f16 s4, s3250; CHECK-NEXT: vrintr.f16 s4, s4251; CHECK-NEXT: vrintr.f16 s3, s3252; CHECK-NEXT: vins.f16 s3, s4253; CHECK-NEXT: bx lr254entry:255 %0 = call fast <8 x half> @llvm.nearbyint.v8f16(<8 x half> %src)256 ret <8 x half> %0257}258 259define arm_aapcs_vfpcc <2 x double> @fnearbyint_float64_t(<2 x double> %src) {260; CHECK-LABEL: fnearbyint_float64_t:261; CHECK: @ %bb.0: @ %entry262; CHECK-NEXT: .save {r7, lr}263; CHECK-NEXT: push {r7, lr}264; CHECK-NEXT: .vsave {d8, d9}265; CHECK-NEXT: vpush {d8, d9}266; CHECK-NEXT: vmov q4, q0267; CHECK-NEXT: vmov r0, r1, d9268; CHECK-NEXT: bl nearbyint269; CHECK-NEXT: vmov r2, r3, d8270; CHECK-NEXT: vmov d9, r0, r1271; CHECK-NEXT: mov r0, r2272; CHECK-NEXT: mov r1, r3273; CHECK-NEXT: bl nearbyint274; CHECK-NEXT: vmov d8, r0, r1275; CHECK-NEXT: vmov q0, q4276; CHECK-NEXT: vpop {d8, d9}277; CHECK-NEXT: pop {r7, pc}278entry:279 %0 = call fast <2 x double> @llvm.nearbyint.v2f64(<2 x double> %src)280 ret <2 x double> %0281}282 283define arm_aapcs_vfpcc <4 x float> @ffloor_float32_t(<4 x float> %src) {284; CHECK-MVE-LABEL: ffloor_float32_t:285; CHECK-MVE: @ %bb.0: @ %entry286; CHECK-MVE-NEXT: vrintm.f32 s3, s3287; CHECK-MVE-NEXT: vrintm.f32 s2, s2288; CHECK-MVE-NEXT: vrintm.f32 s1, s1289; CHECK-MVE-NEXT: vrintm.f32 s0, s0290; CHECK-MVE-NEXT: bx lr291;292; CHECK-MVEFP-LABEL: ffloor_float32_t:293; CHECK-MVEFP: @ %bb.0: @ %entry294; CHECK-MVEFP-NEXT: vrintm.f32 q0, q0295; CHECK-MVEFP-NEXT: bx lr296entry:297 %0 = call fast <4 x float> @llvm.floor.v4f32(<4 x float> %src)298 ret <4 x float> %0299}300 301define arm_aapcs_vfpcc <8 x half> @ffloor_float16_t(<8 x half> %src) {302; CHECK-MVE-LABEL: ffloor_float16_t:303; CHECK-MVE: @ %bb.0: @ %entry304; CHECK-MVE-NEXT: vmovx.f16 s4, s0305; CHECK-MVE-NEXT: vrintm.f16 s0, s0306; CHECK-MVE-NEXT: vrintm.f16 s4, s4307; CHECK-MVE-NEXT: vins.f16 s0, s4308; CHECK-MVE-NEXT: vmovx.f16 s4, s1309; CHECK-MVE-NEXT: vrintm.f16 s4, s4310; CHECK-MVE-NEXT: vrintm.f16 s1, s1311; CHECK-MVE-NEXT: vins.f16 s1, s4312; CHECK-MVE-NEXT: vmovx.f16 s4, s2313; CHECK-MVE-NEXT: vrintm.f16 s4, s4314; CHECK-MVE-NEXT: vrintm.f16 s2, s2315; CHECK-MVE-NEXT: vins.f16 s2, s4316; CHECK-MVE-NEXT: vmovx.f16 s4, s3317; CHECK-MVE-NEXT: vrintm.f16 s4, s4318; CHECK-MVE-NEXT: vrintm.f16 s3, s3319; CHECK-MVE-NEXT: vins.f16 s3, s4320; CHECK-MVE-NEXT: bx lr321;322; CHECK-MVEFP-LABEL: ffloor_float16_t:323; CHECK-MVEFP: @ %bb.0: @ %entry324; CHECK-MVEFP-NEXT: vrintm.f16 q0, q0325; CHECK-MVEFP-NEXT: bx lr326entry:327 %0 = call fast <8 x half> @llvm.floor.v8f16(<8 x half> %src)328 ret <8 x half> %0329}330 331define arm_aapcs_vfpcc <2 x double> @ffloor_float64_t(<2 x double> %src) {332; CHECK-LABEL: ffloor_float64_t:333; CHECK: @ %bb.0: @ %entry334; CHECK-NEXT: .save {r7, lr}335; CHECK-NEXT: push {r7, lr}336; CHECK-NEXT: .vsave {d8, d9}337; CHECK-NEXT: vpush {d8, d9}338; CHECK-NEXT: vmov q4, q0339; CHECK-NEXT: vmov r0, r1, d9340; CHECK-NEXT: bl floor341; CHECK-NEXT: vmov r2, r3, d8342; CHECK-NEXT: vmov d9, r0, r1343; CHECK-NEXT: mov r0, r2344; CHECK-NEXT: mov r1, r3345; CHECK-NEXT: bl floor346; CHECK-NEXT: vmov d8, r0, r1347; CHECK-NEXT: vmov q0, q4348; CHECK-NEXT: vpop {d8, d9}349; CHECK-NEXT: pop {r7, pc}350entry:351 %0 = call fast <2 x double> @llvm.floor.v2f64(<2 x double> %src)352 ret <2 x double> %0353}354 355define arm_aapcs_vfpcc <4 x float> @fround_float32_t(<4 x float> %src) {356; CHECK-MVE-LABEL: fround_float32_t:357; CHECK-MVE: @ %bb.0: @ %entry358; CHECK-MVE-NEXT: vrinta.f32 s3, s3359; CHECK-MVE-NEXT: vrinta.f32 s2, s2360; CHECK-MVE-NEXT: vrinta.f32 s1, s1361; CHECK-MVE-NEXT: vrinta.f32 s0, s0362; CHECK-MVE-NEXT: bx lr363;364; CHECK-MVEFP-LABEL: fround_float32_t:365; CHECK-MVEFP: @ %bb.0: @ %entry366; CHECK-MVEFP-NEXT: vrinta.f32 q0, q0367; CHECK-MVEFP-NEXT: bx lr368entry:369 %0 = call fast <4 x float> @llvm.round.v4f32(<4 x float> %src)370 ret <4 x float> %0371}372 373define arm_aapcs_vfpcc <8 x half> @fround_float16_t(<8 x half> %src) {374; CHECK-MVE-LABEL: fround_float16_t:375; CHECK-MVE: @ %bb.0: @ %entry376; CHECK-MVE-NEXT: vmovx.f16 s4, s0377; CHECK-MVE-NEXT: vrinta.f16 s0, s0378; CHECK-MVE-NEXT: vrinta.f16 s4, s4379; CHECK-MVE-NEXT: vins.f16 s0, s4380; CHECK-MVE-NEXT: vmovx.f16 s4, s1381; CHECK-MVE-NEXT: vrinta.f16 s4, s4382; CHECK-MVE-NEXT: vrinta.f16 s1, s1383; CHECK-MVE-NEXT: vins.f16 s1, s4384; CHECK-MVE-NEXT: vmovx.f16 s4, s2385; CHECK-MVE-NEXT: vrinta.f16 s4, s4386; CHECK-MVE-NEXT: vrinta.f16 s2, s2387; CHECK-MVE-NEXT: vins.f16 s2, s4388; CHECK-MVE-NEXT: vmovx.f16 s4, s3389; CHECK-MVE-NEXT: vrinta.f16 s4, s4390; CHECK-MVE-NEXT: vrinta.f16 s3, s3391; CHECK-MVE-NEXT: vins.f16 s3, s4392; CHECK-MVE-NEXT: bx lr393;394; CHECK-MVEFP-LABEL: fround_float16_t:395; CHECK-MVEFP: @ %bb.0: @ %entry396; CHECK-MVEFP-NEXT: vrinta.f16 q0, q0397; CHECK-MVEFP-NEXT: bx lr398entry:399 %0 = call fast <8 x half> @llvm.round.v8f16(<8 x half> %src)400 ret <8 x half> %0401}402 403define arm_aapcs_vfpcc <2 x double> @fround_float64_t(<2 x double> %src) {404; CHECK-LABEL: fround_float64_t:405; CHECK: @ %bb.0: @ %entry406; CHECK-NEXT: .save {r7, lr}407; CHECK-NEXT: push {r7, lr}408; CHECK-NEXT: .vsave {d8, d9}409; CHECK-NEXT: vpush {d8, d9}410; CHECK-NEXT: vmov q4, q0411; CHECK-NEXT: vmov r0, r1, d9412; CHECK-NEXT: bl round413; CHECK-NEXT: vmov r2, r3, d8414; CHECK-NEXT: vmov d9, r0, r1415; CHECK-NEXT: mov r0, r2416; CHECK-NEXT: mov r1, r3417; CHECK-NEXT: bl round418; CHECK-NEXT: vmov d8, r0, r1419; CHECK-NEXT: vmov q0, q4420; CHECK-NEXT: vpop {d8, d9}421; CHECK-NEXT: pop {r7, pc}422entry:423 %0 = call fast <2 x double> @llvm.round.v2f64(<2 x double> %src)424 ret <2 x double> %0425}426 427define arm_aapcs_vfpcc <4 x float> @froundeven_float32_t(<4 x float> %src) {428; CHECK-MVE-LABEL: froundeven_float32_t:429; CHECK-MVE: @ %bb.0: @ %entry430; CHECK-MVE-NEXT: vrintn.f32 s3, s3431; CHECK-MVE-NEXT: vrintn.f32 s2, s2432; CHECK-MVE-NEXT: vrintn.f32 s1, s1433; CHECK-MVE-NEXT: vrintn.f32 s0, s0434; CHECK-MVE-NEXT: bx lr435;436; CHECK-MVEFP-LABEL: froundeven_float32_t:437; CHECK-MVEFP: @ %bb.0: @ %entry438; CHECK-MVEFP-NEXT: vrintn.f32 q0, q0439; CHECK-MVEFP-NEXT: bx lr440entry:441 %0 = call fast <4 x float> @llvm.roundeven.v4f32(<4 x float> %src)442 ret <4 x float> %0443}444 445define arm_aapcs_vfpcc <8 x half> @froundeven_float16_t(<8 x half> %src) {446; CHECK-MVE-LABEL: froundeven_float16_t:447; CHECK-MVE: @ %bb.0: @ %entry448; CHECK-MVE-NEXT: vmovx.f16 s4, s0449; CHECK-MVE-NEXT: vrintn.f16 s0, s0450; CHECK-MVE-NEXT: vrintn.f16 s4, s4451; CHECK-MVE-NEXT: vins.f16 s0, s4452; CHECK-MVE-NEXT: vmovx.f16 s4, s1453; CHECK-MVE-NEXT: vrintn.f16 s4, s4454; CHECK-MVE-NEXT: vrintn.f16 s1, s1455; CHECK-MVE-NEXT: vins.f16 s1, s4456; CHECK-MVE-NEXT: vmovx.f16 s4, s2457; CHECK-MVE-NEXT: vrintn.f16 s4, s4458; CHECK-MVE-NEXT: vrintn.f16 s2, s2459; CHECK-MVE-NEXT: vins.f16 s2, s4460; CHECK-MVE-NEXT: vmovx.f16 s4, s3461; CHECK-MVE-NEXT: vrintn.f16 s4, s4462; CHECK-MVE-NEXT: vrintn.f16 s3, s3463; CHECK-MVE-NEXT: vins.f16 s3, s4464; CHECK-MVE-NEXT: bx lr465;466; CHECK-MVEFP-LABEL: froundeven_float16_t:467; CHECK-MVEFP: @ %bb.0: @ %entry468; CHECK-MVEFP-NEXT: vrintn.f16 q0, q0469; CHECK-MVEFP-NEXT: bx lr470entry:471 %0 = call fast <8 x half> @llvm.roundeven.v8f16(<8 x half> %src)472 ret <8 x half> %0473}474 475define arm_aapcs_vfpcc <2 x double> @froundeven_float64_t(<2 x double> %src) {476; CHECK-LABEL: froundeven_float64_t:477; CHECK: @ %bb.0: @ %entry478; CHECK-NEXT: .save {r7, lr}479; CHECK-NEXT: push {r7, lr}480; CHECK-NEXT: .vsave {d8, d9}481; CHECK-NEXT: vpush {d8, d9}482; CHECK-NEXT: vmov q4, q0483; CHECK-NEXT: vmov r0, r1, d9484; CHECK-NEXT: bl roundeven485; CHECK-NEXT: vmov r2, r3, d8486; CHECK-NEXT: vmov d9, r0, r1487; CHECK-NEXT: mov r0, r2488; CHECK-NEXT: mov r1, r3489; CHECK-NEXT: bl roundeven490; CHECK-NEXT: vmov d8, r0, r1491; CHECK-NEXT: vmov q0, q4492; CHECK-NEXT: vpop {d8, d9}493; CHECK-NEXT: pop {r7, pc}494entry:495 %0 = call fast <2 x double> @llvm.roundeven.v2f64(<2 x double> %src)496 ret <2 x double> %0497}498