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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s3 4define arm_aapcs_vfpcc <8 x i16> @scaled_v8i16_i16(ptr %base, ptr %offptr) {5; CHECK-LABEL: scaled_v8i16_i16:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vldrh.u16 q1, [r1]8; CHECK-NEXT: vldrh.u16 q0, [r0, q1, uxtw #1]9; CHECK-NEXT: bx lr10entry:11 %offs = load <8 x i16>, ptr %offptr, align 212 %offs.zext = zext <8 x i16> %offs to <8 x i32>13 %ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> %offs.zext14 %gather = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i16> undef)15 ret <8 x i16> %gather16}17 18define arm_aapcs_vfpcc <8 x half> @scaled_v8f16_i16(ptr %base, ptr %offptr) {19; CHECK-LABEL: scaled_v8f16_i16:20; CHECK: @ %bb.0: @ %entry21; CHECK-NEXT: vldrh.u16 q1, [r1]22; CHECK-NEXT: vldrh.u16 q0, [r0, q1, uxtw #1]23; CHECK-NEXT: bx lr24entry:25 %offs = load <8 x i16>, ptr %offptr, align 226 %offs.zext = zext <8 x i16> %offs to <8 x i32>27 %i16_ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> %offs.zext28 %ptrs = bitcast <8 x ptr> %i16_ptrs to <8 x ptr>29 %gather = call <8 x half> @llvm.masked.gather.v8f16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x half> undef)30 ret <8 x half> %gather31}32 33define arm_aapcs_vfpcc <8 x half> @scaled_v8f16_half(ptr %base, ptr %offptr) {34; CHECK-LABEL: scaled_v8f16_half:35; CHECK: @ %bb.0: @ %entry36; CHECK-NEXT: vldrh.u16 q1, [r1]37; CHECK-NEXT: vldrh.u16 q0, [r0, q1, uxtw #1]38; CHECK-NEXT: bx lr39entry:40 %offs = load <8 x i16>, ptr %offptr, align 241 %offs.zext = zext <8 x i16> %offs to <8 x i32>42 %ptrs = getelementptr inbounds half, ptr %base, <8 x i32> %offs.zext43 %gather = call <8 x half> @llvm.masked.gather.v8f16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x half> undef)44 ret <8 x half> %gather45}46 47define arm_aapcs_vfpcc <8 x i16> @scaled_v8i16_sext(ptr %base, ptr %offptr) {48; CHECK-LABEL: scaled_v8i16_sext:49; CHECK: @ %bb.0: @ %entry50; CHECK-NEXT: .save {r4, r5, r7, lr}51; CHECK-NEXT: push {r4, r5, r7, lr}52; CHECK-NEXT: vldrh.s32 q0, [r1, #8]53; CHECK-NEXT: vshl.i32 q0, q0, #154; CHECK-NEXT: vadd.i32 q0, q0, r055; CHECK-NEXT: vmov r2, r12, d056; CHECK-NEXT: vmov r3, lr, d157; CHECK-NEXT: vldrh.s32 q0, [r1]58; CHECK-NEXT: vshl.i32 q0, q0, #159; CHECK-NEXT: vadd.i32 q0, q0, r060; CHECK-NEXT: vmov r4, r5, d061; CHECK-NEXT: vmov r0, r1, d162; CHECK-NEXT: ldrh r2, [r2]63; CHECK-NEXT: ldrh.w r12, [r12]64; CHECK-NEXT: ldrh r3, [r3]65; CHECK-NEXT: ldrh.w lr, [lr]66; CHECK-NEXT: ldrh r4, [r4]67; CHECK-NEXT: ldrh r5, [r5]68; CHECK-NEXT: vmov.16 q0[0], r469; CHECK-NEXT: ldrh r0, [r0]70; CHECK-NEXT: vmov.16 q0[1], r571; CHECK-NEXT: ldrh r1, [r1]72; CHECK-NEXT: vmov.16 q0[2], r073; CHECK-NEXT: vmov.16 q0[3], r174; CHECK-NEXT: vmov.16 q0[4], r275; CHECK-NEXT: vmov.16 q0[5], r1276; CHECK-NEXT: vmov.16 q0[6], r377; CHECK-NEXT: vmov.16 q0[7], lr78; CHECK-NEXT: pop {r4, r5, r7, pc}79entry:80 %offs = load <8 x i16>, ptr %offptr, align 281 %offs.sext = sext <8 x i16> %offs to <8 x i32>82 %ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> %offs.sext83 %gather = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i16> undef)84 ret <8 x i16> %gather85}86 87define arm_aapcs_vfpcc <8 x half> @scaled_v8f16_sext(ptr %base, ptr %offptr) {88; CHECK-LABEL: scaled_v8f16_sext:89; CHECK: @ %bb.0: @ %entry90; CHECK-NEXT: vldrh.s32 q0, [r1]91; CHECK-NEXT: vshl.i32 q0, q0, #192; CHECK-NEXT: vadd.i32 q0, q0, r093; CHECK-NEXT: vmov r2, r3, d094; CHECK-NEXT: vldr.16 s4, [r3]95; CHECK-NEXT: vldr.16 s0, [r2]96; CHECK-NEXT: vmov r2, r3, d197; CHECK-NEXT: vins.f16 s0, s498; CHECK-NEXT: vldrh.s32 q1, [r1, #8]99; CHECK-NEXT: vldr.16 s2, [r3]100; CHECK-NEXT: vldr.16 s1, [r2]101; CHECK-NEXT: vshl.i32 q1, q1, #1102; CHECK-NEXT: vadd.i32 q1, q1, r0103; CHECK-NEXT: vins.f16 s1, s2104; CHECK-NEXT: vmov r0, r1, d2105; CHECK-NEXT: vldr.16 s4, [r1]106; CHECK-NEXT: vldr.16 s2, [r0]107; CHECK-NEXT: vmov r0, r1, d3108; CHECK-NEXT: vins.f16 s2, s4109; CHECK-NEXT: vldr.16 s4, [r1]110; CHECK-NEXT: vldr.16 s3, [r0]111; CHECK-NEXT: vins.f16 s3, s4112; CHECK-NEXT: bx lr113entry:114 %offs = load <8 x i16>, ptr %offptr, align 2115 %offs.sext = sext <8 x i16> %offs to <8 x i32>116 %i16_ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> %offs.sext117 %ptrs = bitcast <8 x ptr> %i16_ptrs to <8 x ptr>118 %gather = call <8 x half> @llvm.masked.gather.v8f16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x half> undef)119 ret <8 x half> %gather120}121 122define arm_aapcs_vfpcc <8 x i16> @unsigned_scaled_v8i16_i8(ptr %base, ptr %offptr) {123; CHECK-LABEL: unsigned_scaled_v8i16_i8:124; CHECK: @ %bb.0: @ %entry125; CHECK-NEXT: vldrb.u16 q1, [r1]126; CHECK-NEXT: vldrh.u16 q0, [r0, q1, uxtw #1]127; CHECK-NEXT: bx lr128entry:129 %offs = load <8 x i8>, ptr %offptr, align 1130 %offs.zext = zext <8 x i8> %offs to <8 x i32>131 %ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> %offs.zext132 %gather = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i16> undef)133 ret <8 x i16> %gather134}135 136define arm_aapcs_vfpcc <8 x half> @unsigned_scaled_v8f16_i8(ptr %base, ptr %offptr) {137; CHECK-LABEL: unsigned_scaled_v8f16_i8:138; CHECK: @ %bb.0: @ %entry139; CHECK-NEXT: vldrb.u16 q1, [r1]140; CHECK-NEXT: vldrh.u16 q0, [r0, q1, uxtw #1]141; CHECK-NEXT: bx lr142entry:143 %offs = load <8 x i8>, ptr %offptr, align 1144 %offs.zext = zext <8 x i8> %offs to <8 x i32>145 %i16_ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> %offs.zext146 %ptrs = bitcast <8 x ptr> %i16_ptrs to <8 x ptr>147 %gather = call <8 x half> @llvm.masked.gather.v8f16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x half> undef)148 ret <8 x half> %gather149}150 151define arm_aapcs_vfpcc <8 x i16> @scaled_v8i16_i16_passthru0t(ptr %base, ptr %offptr) {152; CHECK-LABEL: scaled_v8i16_i16_passthru0t:153; CHECK: @ %bb.0: @ %entry154; CHECK-NEXT: vldrh.u16 q1, [r1]155; CHECK-NEXT: vldrh.u16 q0, [r0, q1, uxtw #1]156; CHECK-NEXT: bx lr157entry:158 %offs = load <8 x i16>, ptr %offptr, align 2159 %offs.zext = zext <8 x i16> %offs to <8 x i32>160 %ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> %offs.zext161 %gather = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i16> zeroinitializer)162 ret <8 x i16> %gather163}164 165define arm_aapcs_vfpcc <8 x i16> @scaled_v8i16_i16_passthru1t(ptr %base, ptr %offptr) {166; CHECK-LABEL: scaled_v8i16_i16_passthru1t:167; CHECK: @ %bb.0: @ %entry168; CHECK-NEXT: vldrh.u16 q1, [r1]169; CHECK-NEXT: vldrh.u16 q0, [r0, q1, uxtw #1]170; CHECK-NEXT: bx lr171entry:172 %offs = load <8 x i16>, ptr %offptr, align 2173 %offs.zext = zext <8 x i16> %offs to <8 x i32>174 %ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> %offs.zext175 %gather = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)176 ret <8 x i16> %gather177}178 179define arm_aapcs_vfpcc <8 x i16> @scaled_v8i16_i16_passthru1f(ptr %base, ptr %offptr) {180; CHECK-LABEL: scaled_v8i16_i16_passthru1f:181; CHECK: @ %bb.0: @ %entry182; CHECK-NEXT: movw r2, #65487183; CHECK-NEXT: vmov.i16 q0, #0x1184; CHECK-NEXT: vmsr p0, r2185; CHECK-NEXT: vldrh.u16 q1, [r1]186; CHECK-NEXT: vpst187; CHECK-NEXT: vldrht.u16 q2, [r0, q1, uxtw #1]188; CHECK-NEXT: vpsel q0, q2, q0189; CHECK-NEXT: bx lr190entry:191 %offs = load <8 x i16>, ptr %offptr, align 2192 %offs.zext = zext <8 x i16> %offs to <8 x i32>193 %ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> %offs.zext194 %gather = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> <i1 true, i1 true, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)195 ret <8 x i16> %gather196}197 198define arm_aapcs_vfpcc <8 x i16> @scaled_v8i16_i16_passthru0f(ptr %base, ptr %offptr) {199; CHECK-LABEL: scaled_v8i16_i16_passthru0f:200; CHECK: @ %bb.0: @ %entry201; CHECK-NEXT: movw r2, #65523202; CHECK-NEXT: vmsr p0, r2203; CHECK-NEXT: vldrh.u16 q1, [r1]204; CHECK-NEXT: vpst205; CHECK-NEXT: vldrht.u16 q0, [r0, q1, uxtw #1]206; CHECK-NEXT: bx lr207entry:208 %offs = load <8 x i16>, ptr %offptr, align 2209 %offs.zext = zext <8 x i16> %offs to <8 x i32>210 %ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> %offs.zext211 %gather = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> <i1 true, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>)212 ret <8 x i16> %gather213}214 215define arm_aapcs_vfpcc <8 x i16> @scaled_v8i16_i16_passthru_icmp0(ptr %base, ptr %offptr) {216; CHECK-LABEL: scaled_v8i16_i16_passthru_icmp0:217; CHECK: @ %bb.0: @ %entry218; CHECK-NEXT: vldrh.u16 q1, [r1]219; CHECK-NEXT: vpt.s16 gt, q1, zr220; CHECK-NEXT: vldrht.u16 q0, [r0, q1, uxtw #1]221; CHECK-NEXT: bx lr222entry:223 %offs = load <8 x i16>, ptr %offptr, align 2224 %offs.zext = zext <8 x i16> %offs to <8 x i32>225 %ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> %offs.zext226 %mask = icmp sgt <8 x i16> %offs, zeroinitializer227 %gather = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> %mask, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>)228 ret <8 x i16> %gather229}230 231define arm_aapcs_vfpcc <8 x i16> @scaled_v8i16_i16_passthru_icmp1(ptr %base, ptr %offptr) {232; CHECK-LABEL: scaled_v8i16_i16_passthru_icmp1:233; CHECK: @ %bb.0: @ %entry234; CHECK-NEXT: vldrh.u16 q1, [r1]235; CHECK-NEXT: vmov.i16 q0, #0x1236; CHECK-NEXT: vpt.s16 gt, q1, zr237; CHECK-NEXT: vldrht.u16 q2, [r0, q1, uxtw #1]238; CHECK-NEXT: vpsel q0, q2, q0239; CHECK-NEXT: bx lr240entry:241 %offs = load <8 x i16>, ptr %offptr, align 2242 %offs.zext = zext <8 x i16> %offs to <8 x i32>243 %ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> %offs.zext244 %mask = icmp sgt <8 x i16> %offs, zeroinitializer245 %gather = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> %mask, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)246 ret <8 x i16> %gather247}248 249define arm_aapcs_vfpcc <8 x i16> @scaled_v8i16_i16_2gep(ptr %base, ptr %offptr) {250; CHECK-LABEL: scaled_v8i16_i16_2gep:251; CHECK: @ %bb.0: @ %entry252; CHECK-NEXT: .save {r4, r5, r7, lr}253; CHECK-NEXT: push {r4, r5, r7, lr}254; CHECK-NEXT: vldrh.s32 q0, [r1, #8]255; CHECK-NEXT: mov.w r12, #40256; CHECK-NEXT: vshl.i32 q0, q0, #1257; CHECK-NEXT: vadd.i32 q0, q0, r0258; CHECK-NEXT: vadd.i32 q0, q0, r12259; CHECK-NEXT: vmov r3, lr, d0260; CHECK-NEXT: vmov r2, r4, d1261; CHECK-NEXT: vldrh.s32 q0, [r1]262; CHECK-NEXT: vshl.i32 q0, q0, #1263; CHECK-NEXT: vadd.i32 q0, q0, r0264; CHECK-NEXT: vadd.i32 q0, q0, r12265; CHECK-NEXT: vmov r0, r1, d1266; CHECK-NEXT: ldrh.w r12, [lr]267; CHECK-NEXT: ldrh.w lr, [r4]268; CHECK-NEXT: vmov r4, r5, d0269; CHECK-NEXT: ldrh r3, [r3]270; CHECK-NEXT: ldrh r2, [r2]271; CHECK-NEXT: ldrh r0, [r0]272; CHECK-NEXT: ldrh r1, [r1]273; CHECK-NEXT: ldrh r4, [r4]274; CHECK-NEXT: ldrh r5, [r5]275; CHECK-NEXT: vmov.16 q0[0], r4276; CHECK-NEXT: vmov.16 q0[1], r5277; CHECK-NEXT: vmov.16 q0[2], r0278; CHECK-NEXT: vmov.16 q0[3], r1279; CHECK-NEXT: vmov.16 q0[4], r3280; CHECK-NEXT: vmov.16 q0[5], r12281; CHECK-NEXT: vmov.16 q0[6], r2282; CHECK-NEXT: vmov.16 q0[7], lr283; CHECK-NEXT: pop {r4, r5, r7, pc}284entry:285 %offs = load <8 x i16>, ptr %offptr, align 2286 %ptrs = getelementptr inbounds i16, ptr %base, <8 x i16> %offs287 %ptrs2 = getelementptr inbounds i16, <8 x ptr> %ptrs, i16 20288 %gather = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs2, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i16> undef)289 ret <8 x i16> %gather290}291 292define arm_aapcs_vfpcc <8 x i16> @scaled_v8i16_i16_2gep2(ptr %base, ptr %offptr) {293; CHECK-LABEL: scaled_v8i16_i16_2gep2:294; CHECK: @ %bb.0: @ %entry295; CHECK-NEXT: adr r1, .LCPI14_0296; CHECK-NEXT: vldrw.u32 q1, [r1]297; CHECK-NEXT: vldrh.u16 q0, [r0, q1]298; CHECK-NEXT: bx lr299; CHECK-NEXT: .p2align 4300; CHECK-NEXT: @ %bb.1:301; CHECK-NEXT: .LCPI14_0:302; CHECK-NEXT: .short 40 @ 0x28303; CHECK-NEXT: .short 46 @ 0x2e304; CHECK-NEXT: .short 52 @ 0x34305; CHECK-NEXT: .short 58 @ 0x3a306; CHECK-NEXT: .short 64 @ 0x40307; CHECK-NEXT: .short 70 @ 0x46308; CHECK-NEXT: .short 76 @ 0x4c309; CHECK-NEXT: .short 82 @ 0x52310entry:311 %ptrs = getelementptr inbounds i16, ptr %base, <8 x i16> <i16 0, i16 3, i16 6, i16 9, i16 12, i16 15, i16 18, i16 21>312 %ptrs2 = getelementptr inbounds i16,<8 x ptr> %ptrs, i16 20313 %gather = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs2, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i16> undef)314 ret <8 x i16> %gather315}316 317define arm_aapcs_vfpcc <8 x i16> @scaled_v8i16_i16_biggep(ptr %base) {318; CHECK-LABEL: scaled_v8i16_i16_biggep:319; CHECK: @ %bb.0: @ %entry320; CHECK-NEXT: adr r1, .LCPI15_0321; CHECK-NEXT: vldrw.u32 q1, [r1]322; CHECK-NEXT: vldrh.u16 q0, [r0, q1]323; CHECK-NEXT: bx lr324; CHECK-NEXT: .p2align 4325; CHECK-NEXT: @ %bb.1:326; CHECK-NEXT: .LCPI15_0:327; CHECK-NEXT: .short 40 @ 0x28328; CHECK-NEXT: .short 46 @ 0x2e329; CHECK-NEXT: .short 52 @ 0x34330; CHECK-NEXT: .short 58 @ 0x3a331; CHECK-NEXT: .short 64 @ 0x40332; CHECK-NEXT: .short 70 @ 0x46333; CHECK-NEXT: .short 76 @ 0x4c334; CHECK-NEXT: .short 82 @ 0x52335entry:336 %ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21>337 %ptrs2 = getelementptr inbounds i16,<8 x ptr> %ptrs, i32 20338 %gather = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs2, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i16> undef)339 ret <8 x i16> %gather340}341 342define arm_aapcs_vfpcc <8 x i16> @scaled_v8i16_i16_biggep2(ptr %base) {343; CHECK-LABEL: scaled_v8i16_i16_biggep2:344; CHECK: @ %bb.0: @ %entry345; CHECK-NEXT: adr r1, .LCPI16_0346; CHECK-NEXT: vldrw.u32 q1, [r1]347; CHECK-NEXT: vldrh.u16 q0, [r0, q1, uxtw #1]348; CHECK-NEXT: bx lr349; CHECK-NEXT: .p2align 4350; CHECK-NEXT: @ %bb.1:351; CHECK-NEXT: .LCPI16_0:352; CHECK-NEXT: .short 0 @ 0x0353; CHECK-NEXT: .short 3 @ 0x3354; CHECK-NEXT: .short 6 @ 0x6355; CHECK-NEXT: .short 9 @ 0x9356; CHECK-NEXT: .short 12 @ 0xc357; CHECK-NEXT: .short 15 @ 0xf358; CHECK-NEXT: .short 18 @ 0x12359; CHECK-NEXT: .short 21 @ 0x15360entry:361 %ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21>362 %gather = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i16> undef)363 ret <8 x i16> %gather364}365 366define arm_aapcs_vfpcc <8 x i16> @scaled_v8i16_i16_biggep3(ptr %base) {367; CHECK-LABEL: scaled_v8i16_i16_biggep3:368; CHECK: @ %bb.0: @ %entry369; CHECK-NEXT: .save {r4, r5, r7, lr}370; CHECK-NEXT: push {r4, r5, r7, lr}371; CHECK-NEXT: adr r1, .LCPI17_0372; CHECK-NEXT: adr r2, .LCPI17_1373; CHECK-NEXT: vldrw.u32 q0, [r1]374; CHECK-NEXT: vadd.i32 q0, q0, r0375; CHECK-NEXT: vmov r1, lr, d0376; CHECK-NEXT: vmov r3, r12, d1377; CHECK-NEXT: vldrw.u32 q0, [r2]378; CHECK-NEXT: vadd.i32 q0, q0, r0379; CHECK-NEXT: vmov r4, r5, d0380; CHECK-NEXT: vmov r0, r2, d1381; CHECK-NEXT: ldrh r1, [r1]382; CHECK-NEXT: ldrh.w lr, [lr]383; CHECK-NEXT: ldrh r3, [r3]384; CHECK-NEXT: ldrh.w r12, [r12]385; CHECK-NEXT: ldrh r4, [r4]386; CHECK-NEXT: ldrh r5, [r5]387; CHECK-NEXT: vmov.16 q0[0], r4388; CHECK-NEXT: ldrh r0, [r0]389; CHECK-NEXT: vmov.16 q0[1], r5390; CHECK-NEXT: ldrh r2, [r2]391; CHECK-NEXT: vmov.16 q0[2], r0392; CHECK-NEXT: vmov.16 q0[3], r2393; CHECK-NEXT: vmov.16 q0[4], r1394; CHECK-NEXT: vmov.16 q0[5], lr395; CHECK-NEXT: vmov.16 q0[6], r3396; CHECK-NEXT: vmov.16 q0[7], r12397; CHECK-NEXT: pop {r4, r5, r7, pc}398; CHECK-NEXT: .p2align 4399; CHECK-NEXT: @ %bb.1:400; CHECK-NEXT: .LCPI17_0:401; CHECK-NEXT: .long 131096 @ 0x20018402; CHECK-NEXT: .long 131102 @ 0x2001e403; CHECK-NEXT: .long 131108 @ 0x20024404; CHECK-NEXT: .long 131114 @ 0x2002a405; CHECK-NEXT: .LCPI17_1:406; CHECK-NEXT: .long 131072 @ 0x20000407; CHECK-NEXT: .long 131078 @ 0x20006408; CHECK-NEXT: .long 131084 @ 0x2000c409; CHECK-NEXT: .long 131090 @ 0x20012410entry:411 %ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21>412 %ptrs2 = getelementptr inbounds i16,<8 x ptr> %ptrs, i32 65536413 %gather = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs2, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i16> undef)414 ret <8 x i16> %gather415}416 417define arm_aapcs_vfpcc <8 x i16> @scaled_v8i16_i16_biggep4(ptr %base) {418; CHECK-LABEL: scaled_v8i16_i16_biggep4:419; CHECK: @ %bb.0: @ %entry420; CHECK-NEXT: .save {r4, r5, r7, lr}421; CHECK-NEXT: push {r4, r5, r7, lr}422; CHECK-NEXT: adr r1, .LCPI18_0423; CHECK-NEXT: adr r2, .LCPI18_1424; CHECK-NEXT: vldrw.u32 q0, [r1]425; CHECK-NEXT: vadd.i32 q0, q0, r0426; CHECK-NEXT: vmov r1, lr, d0427; CHECK-NEXT: vmov r3, r12, d1428; CHECK-NEXT: vldrw.u32 q0, [r2]429; CHECK-NEXT: vadd.i32 q0, q0, r0430; CHECK-NEXT: vmov r4, r5, d0431; CHECK-NEXT: vmov r0, r2, d1432; CHECK-NEXT: ldrh r1, [r1]433; CHECK-NEXT: ldrh.w lr, [lr]434; CHECK-NEXT: ldrh r3, [r3]435; CHECK-NEXT: ldrh.w r12, [r12]436; CHECK-NEXT: ldrh r4, [r4]437; CHECK-NEXT: ldrh r5, [r5]438; CHECK-NEXT: vmov.16 q0[0], r4439; CHECK-NEXT: ldrh r0, [r0]440; CHECK-NEXT: vmov.16 q0[1], r5441; CHECK-NEXT: ldrh r2, [r2]442; CHECK-NEXT: vmov.16 q0[2], r0443; CHECK-NEXT: vmov.16 q0[3], r2444; CHECK-NEXT: vmov.16 q0[4], r1445; CHECK-NEXT: vmov.16 q0[5], lr446; CHECK-NEXT: vmov.16 q0[6], r3447; CHECK-NEXT: vmov.16 q0[7], r12448; CHECK-NEXT: pop {r4, r5, r7, pc}449; CHECK-NEXT: .p2align 4450; CHECK-NEXT: @ %bb.1:451; CHECK-NEXT: .LCPI18_0:452; CHECK-NEXT: .long 24 @ 0x18453; CHECK-NEXT: .long 131072 @ 0x20000454; CHECK-NEXT: .long 36 @ 0x24455; CHECK-NEXT: .long 42 @ 0x2a456; CHECK-NEXT: .LCPI18_1:457; CHECK-NEXT: .long 0 @ 0x0458; CHECK-NEXT: .long 6 @ 0x6459; CHECK-NEXT: .long 12 @ 0xc460; CHECK-NEXT: .long 18 @ 0x12461entry:462 %ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 65536, i32 18, i32 21>463 %gather = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i16> undef)464 ret <8 x i16> %gather465}466 467define arm_aapcs_vfpcc <8 x i16> @scaled_v8i16_i16_biggep5(<8 x ptr> %base) {468; CHECK-LABEL: scaled_v8i16_i16_biggep5:469; CHECK: @ %bb.0: @ %entry470; CHECK-NEXT: .save {r4, r5, r6, lr}471; CHECK-NEXT: push {r4, r5, r6, lr}472; CHECK-NEXT: mov.w r12, #131072473; CHECK-NEXT: vadd.i32 q0, q0, r12474; CHECK-NEXT: vadd.i32 q1, q1, r12475; CHECK-NEXT: vmov r4, r5, d0476; CHECK-NEXT: vmov r0, r12, d1477; CHECK-NEXT: vmov r3, lr, d3478; CHECK-NEXT: vmov r1, r2, d2479; CHECK-NEXT: ldrh r4, [r4]480; CHECK-NEXT: ldrh r5, [r5]481; CHECK-NEXT: vmov.16 q0[0], r4482; CHECK-NEXT: ldrh r0, [r0]483; CHECK-NEXT: vmov.16 q0[1], r5484; CHECK-NEXT: ldrh r6, [r3]485; CHECK-NEXT: ldrh.w r3, [r12]486; CHECK-NEXT: vmov.16 q0[2], r0487; CHECK-NEXT: ldrh r1, [r1]488; CHECK-NEXT: vmov.16 q0[3], r3489; CHECK-NEXT: ldrh r2, [r2]490; CHECK-NEXT: vmov.16 q0[4], r1491; CHECK-NEXT: ldrh.w lr, [lr]492; CHECK-NEXT: vmov.16 q0[5], r2493; CHECK-NEXT: vmov.16 q0[6], r6494; CHECK-NEXT: vmov.16 q0[7], lr495; CHECK-NEXT: pop {r4, r5, r6, pc}496entry:497 %ptrs2 = getelementptr inbounds i16,<8 x ptr> %base, i32 65536498 %gather = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs2, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i16> undef)499 ret <8 x i16> %gather500}501 502define arm_aapcs_vfpcc <8 x i16> @scaled_v8i16_i16_biggep6(ptr %base) {503; CHECK-LABEL: scaled_v8i16_i16_biggep6:504; CHECK: @ %bb.0: @ %entry505; CHECK-NEXT: .save {r4, r5, r7, lr}506; CHECK-NEXT: push {r4, r5, r7, lr}507; CHECK-NEXT: adr r1, .LCPI20_0508; CHECK-NEXT: adr r2, .LCPI20_1509; CHECK-NEXT: vldrw.u32 q0, [r1]510; CHECK-NEXT: vadd.i32 q0, q0, r0511; CHECK-NEXT: vmov r1, lr, d0512; CHECK-NEXT: vmov r3, r12, d1513; CHECK-NEXT: vldrw.u32 q0, [r2]514; CHECK-NEXT: vadd.i32 q0, q0, r0515; CHECK-NEXT: vmov r4, r5, d0516; CHECK-NEXT: vmov r0, r2, d1517; CHECK-NEXT: ldrh r1, [r1]518; CHECK-NEXT: ldrh.w lr, [lr]519; CHECK-NEXT: ldrh r3, [r3]520; CHECK-NEXT: ldrh.w r12, [r12]521; CHECK-NEXT: ldrh r4, [r4]522; CHECK-NEXT: ldrh r5, [r5]523; CHECK-NEXT: vmov.16 q0[0], r4524; CHECK-NEXT: ldrh r0, [r0]525; CHECK-NEXT: vmov.16 q0[1], r5526; CHECK-NEXT: ldrh r2, [r2]527; CHECK-NEXT: vmov.16 q0[2], r0528; CHECK-NEXT: vmov.16 q0[3], r2529; CHECK-NEXT: vmov.16 q0[4], r1530; CHECK-NEXT: vmov.16 q0[5], lr531; CHECK-NEXT: vmov.16 q0[6], r3532; CHECK-NEXT: vmov.16 q0[7], r12533; CHECK-NEXT: pop {r4, r5, r7, pc}534; CHECK-NEXT: .p2align 4535; CHECK-NEXT: @ %bb.1:536; CHECK-NEXT: .LCPI20_0:537; CHECK-NEXT: .long 131074 @ 0x20002538; CHECK-NEXT: .long 32 @ 0x20539; CHECK-NEXT: .long 38 @ 0x26540; CHECK-NEXT: .long 44 @ 0x2c541; CHECK-NEXT: .LCPI20_1:542; CHECK-NEXT: .long 2 @ 0x2543; CHECK-NEXT: .long 8 @ 0x8544; CHECK-NEXT: .long 14 @ 0xe545; CHECK-NEXT: .long 20 @ 0x14546entry:547 %ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 65536, i32 15, i32 18, i32 21>548 %ptrs2 = getelementptr inbounds i16,<8 x ptr> %ptrs, i32 1549 %gather = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs2, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i16> undef)550 ret <8 x i16> %gather551}552 553define arm_aapcs_vfpcc <8 x i16> @scaled_v8i16_i16_biggep7(ptr %base, ptr %offptr) {554; CHECK-LABEL: scaled_v8i16_i16_biggep7:555; CHECK: @ %bb.0: @ %entry556; CHECK-NEXT: .save {r4, r5, r7, lr}557; CHECK-NEXT: push {r4, r5, r7, lr}558; CHECK-NEXT: adr r1, .LCPI21_0559; CHECK-NEXT: adr r2, .LCPI21_1560; CHECK-NEXT: vldrw.u32 q0, [r1]561; CHECK-NEXT: vadd.i32 q0, q0, r0562; CHECK-NEXT: vmov r1, lr, d0563; CHECK-NEXT: vmov r3, r12, d1564; CHECK-NEXT: vldrw.u32 q0, [r2]565; CHECK-NEXT: vadd.i32 q0, q0, r0566; CHECK-NEXT: vmov r4, r5, d0567; CHECK-NEXT: vmov r0, r2, d1568; CHECK-NEXT: ldrh r1, [r1]569; CHECK-NEXT: ldrh.w lr, [lr]570; CHECK-NEXT: ldrh r3, [r3]571; CHECK-NEXT: ldrh.w r12, [r12]572; CHECK-NEXT: ldrh r4, [r4]573; CHECK-NEXT: ldrh r5, [r5]574; CHECK-NEXT: vmov.16 q0[0], r4575; CHECK-NEXT: ldrh r0, [r0]576; CHECK-NEXT: vmov.16 q0[1], r5577; CHECK-NEXT: ldrh r2, [r2]578; CHECK-NEXT: vmov.16 q0[2], r0579; CHECK-NEXT: vmov.16 q0[3], r2580; CHECK-NEXT: vmov.16 q0[4], r1581; CHECK-NEXT: vmov.16 q0[5], lr582; CHECK-NEXT: vmov.16 q0[6], r3583; CHECK-NEXT: vmov.16 q0[7], r12584; CHECK-NEXT: pop {r4, r5, r7, pc}585; CHECK-NEXT: .p2align 4586; CHECK-NEXT: @ %bb.1:587; CHECK-NEXT: .LCPI21_0:588; CHECK-NEXT: .long 1224 @ 0x4c8589; CHECK-NEXT: .long 1230 @ 0x4ce590; CHECK-NEXT: .long 1236 @ 0x4d4591; CHECK-NEXT: .long 1242 @ 0x4da592; CHECK-NEXT: .LCPI21_1:593; CHECK-NEXT: .long 128 @ 0x80594; CHECK-NEXT: .long 1206 @ 0x4b6595; CHECK-NEXT: .long 1212 @ 0x4bc596; CHECK-NEXT: .long 1218 @ 0x4c2597entry:598 %ptrs = getelementptr inbounds i16, ptr %base, <8 x i16> <i16 65000, i16 3, i16 6, i16 9, i16 12, i16 15, i16 18, i16 21>599 %ptrs2 = getelementptr inbounds i16,<8 x ptr> %ptrs, i16 600600 %gather = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs2, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i16> undef)601 ret <8 x i16> %gather602}603 604define arm_aapcs_vfpcc <8 x i16> @scaled_v8i16_i16_basei32(ptr %base, ptr %offptr) {605; CHECK-LABEL: scaled_v8i16_i16_basei32:606; CHECK: @ %bb.0: @ %entry607; CHECK-NEXT: .save {r4, r5, r7, lr}608; CHECK-NEXT: push {r4, r5, r7, lr}609; CHECK-NEXT: vldrh.u32 q0, [r1, #8]610; CHECK-NEXT: vshl.i32 q0, q0, #2611; CHECK-NEXT: vadd.i32 q0, q0, r0612; CHECK-NEXT: vmov r2, r12, d0613; CHECK-NEXT: vmov r3, lr, d1614; CHECK-NEXT: vldrh.u32 q0, [r1]615; CHECK-NEXT: vshl.i32 q0, q0, #2616; CHECK-NEXT: vadd.i32 q0, q0, r0617; CHECK-NEXT: vmov r4, r5, d0618; CHECK-NEXT: vmov r0, r1, d1619; CHECK-NEXT: ldrh r2, [r2]620; CHECK-NEXT: ldrh.w r12, [r12]621; CHECK-NEXT: ldrh r3, [r3]622; CHECK-NEXT: ldrh.w lr, [lr]623; CHECK-NEXT: ldrh r4, [r4]624; CHECK-NEXT: ldrh r5, [r5]625; CHECK-NEXT: vmov.16 q0[0], r4626; CHECK-NEXT: ldrh r0, [r0]627; CHECK-NEXT: vmov.16 q0[1], r5628; CHECK-NEXT: ldrh r1, [r1]629; CHECK-NEXT: vmov.16 q0[2], r0630; CHECK-NEXT: vmov.16 q0[3], r1631; CHECK-NEXT: vmov.16 q0[4], r2632; CHECK-NEXT: vmov.16 q0[5], r12633; CHECK-NEXT: vmov.16 q0[6], r3634; CHECK-NEXT: vmov.16 q0[7], lr635; CHECK-NEXT: pop {r4, r5, r7, pc}636entry:637 %offs = load <8 x i16>, ptr %offptr, align 2638 %offs.zext = zext <8 x i16> %offs to <8 x i32>639 %ptrs = getelementptr inbounds i32, ptr %base, <8 x i32> %offs.zext640 %ptrs.cast = bitcast <8 x ptr> %ptrs to <8 x ptr>641 %gather = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs.cast, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i16> undef)642 ret <8 x i16> %gather643}644 645declare <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr>, i32, <8 x i1>, <8 x i8>) #1646declare <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr>, i32, <8 x i1>, <8 x i16>) #1647declare <8 x half> @llvm.masked.gather.v8f16.v8p0(<8 x ptr>, i32, <8 x i1>, <8 x half>) #1648