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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s3 4define arm_aapcs_vfpcc <8 x i16> @zext_unscaled_i8_i16(ptr %base, ptr %offptr) {5; CHECK-LABEL: zext_unscaled_i8_i16:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vldrh.u16 q1, [r1]8; CHECK-NEXT: vldrb.u16 q0, [r0, q1]9; CHECK-NEXT: bx lr10entry:11 %offs = load <8 x i16>, ptr %offptr, align 212 %offs.zext = zext <8 x i16> %offs to <8 x i32>13 %ptrs = getelementptr inbounds i8, ptr %base, <8 x i32> %offs.zext14 %gather = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> %ptrs, i32 1, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i8> undef)15 %gather.zext = zext <8 x i8> %gather to <8 x i16>16 ret <8 x i16> %gather.zext17}18 19define arm_aapcs_vfpcc <8 x i16> @zext_unscaled_i8_i16_noext(ptr %base, ptr %offptr) {20; CHECK-LABEL: zext_unscaled_i8_i16_noext:21; CHECK: @ %bb.0: @ %entry22; CHECK-NEXT: .save {r4, r5, r6, lr}23; CHECK-NEXT: push {r4, r5, r6, lr}24; CHECK-NEXT: vldrb.s32 q0, [r1, #4]25; CHECK-NEXT: vadd.i32 q0, q0, r026; CHECK-NEXT: vmov r2, lr, d127; CHECK-NEXT: vmov r12, r3, d028; CHECK-NEXT: vldrb.s32 q0, [r1]29; CHECK-NEXT: vadd.i32 q0, q0, r030; CHECK-NEXT: vmov r4, r5, d031; CHECK-NEXT: vmov r0, r1, d132; CHECK-NEXT: ldrb r6, [r2]33; CHECK-NEXT: ldrb.w r2, [r12]34; CHECK-NEXT: ldrb r3, [r3]35; CHECK-NEXT: ldrb.w lr, [lr]36; CHECK-NEXT: ldrb r4, [r4]37; CHECK-NEXT: ldrb r5, [r5]38; CHECK-NEXT: vmov.16 q0[0], r439; CHECK-NEXT: ldrb r0, [r0]40; CHECK-NEXT: vmov.16 q0[1], r541; CHECK-NEXT: ldrb r1, [r1]42; CHECK-NEXT: vmov.16 q0[2], r043; CHECK-NEXT: vmov.16 q0[3], r144; CHECK-NEXT: vmov.16 q0[4], r245; CHECK-NEXT: vmov.16 q0[5], r346; CHECK-NEXT: vmov.16 q0[6], r647; CHECK-NEXT: vmov.16 q0[7], lr48; CHECK-NEXT: vmovlb.u8 q0, q049; CHECK-NEXT: pop {r4, r5, r6, pc}50entry:51 %offs = load <8 x i8>, ptr %offptr, align 252 %ptrs = getelementptr inbounds i8, ptr %base, <8 x i8> %offs53 %gather = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> %ptrs, i32 1, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i8> undef)54 %gather.zext = zext <8 x i8> %gather to <8 x i16>55 ret <8 x i16> %gather.zext56}57 58define arm_aapcs_vfpcc <8 x i16> @scaled_v8i16_sext(ptr %base, ptr %offptr) {59; CHECK-LABEL: scaled_v8i16_sext:60; CHECK: @ %bb.0: @ %entry61; CHECK-NEXT: .save {r4, r5, r7, lr}62; CHECK-NEXT: push {r4, r5, r7, lr}63; CHECK-NEXT: vldrb.s32 q0, [r1, #4]64; CHECK-NEXT: vshl.i32 q0, q0, #165; CHECK-NEXT: vadd.i32 q0, q0, r066; CHECK-NEXT: vmov r2, r12, d067; CHECK-NEXT: vmov r3, lr, d168; CHECK-NEXT: vldrb.s32 q0, [r1]69; CHECK-NEXT: vshl.i32 q0, q0, #170; CHECK-NEXT: vadd.i32 q0, q0, r071; CHECK-NEXT: vmov r4, r5, d072; CHECK-NEXT: vmov r0, r1, d173; CHECK-NEXT: ldrh r2, [r2]74; CHECK-NEXT: ldrh.w r12, [r12]75; CHECK-NEXT: ldrh r3, [r3]76; CHECK-NEXT: ldrh.w lr, [lr]77; CHECK-NEXT: ldrh r4, [r4]78; CHECK-NEXT: ldrh r5, [r5]79; CHECK-NEXT: vmov.16 q0[0], r480; CHECK-NEXT: ldrh r0, [r0]81; CHECK-NEXT: vmov.16 q0[1], r582; CHECK-NEXT: ldrh r1, [r1]83; CHECK-NEXT: vmov.16 q0[2], r084; CHECK-NEXT: vmov.16 q0[3], r185; CHECK-NEXT: vmov.16 q0[4], r286; CHECK-NEXT: vmov.16 q0[5], r1287; CHECK-NEXT: vmov.16 q0[6], r388; CHECK-NEXT: vmov.16 q0[7], lr89; CHECK-NEXT: pop {r4, r5, r7, pc}90entry:91 %offs = load <8 x i8>, ptr %offptr, align 292 %offs.sext = sext <8 x i8> %offs to <8 x i16>93 %ptrs = getelementptr inbounds i16, ptr %base, <8 x i16> %offs.sext94 %gather = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i16> undef)95 ret <8 x i16> %gather96}97 98define arm_aapcs_vfpcc <8 x i16> @scaled_v8i16_zext(ptr %base, ptr %offptr) {99; CHECK-LABEL: scaled_v8i16_zext:100; CHECK: @ %bb.0: @ %entry101; CHECK-NEXT: .save {r4, r5, r7, lr}102; CHECK-NEXT: push {r4, r5, r7, lr}103; CHECK-NEXT: vldrb.u32 q0, [r1, #4]104; CHECK-NEXT: vshl.i32 q0, q0, #1105; CHECK-NEXT: vadd.i32 q0, q0, r0106; CHECK-NEXT: vmov r2, r12, d0107; CHECK-NEXT: vmov r3, lr, d1108; CHECK-NEXT: vldrb.u32 q0, [r1]109; CHECK-NEXT: vshl.i32 q0, q0, #1110; CHECK-NEXT: vadd.i32 q0, q0, r0111; CHECK-NEXT: vmov r4, r5, d0112; CHECK-NEXT: vmov r0, r1, d1113; CHECK-NEXT: ldrh r2, [r2]114; CHECK-NEXT: ldrh.w r12, [r12]115; CHECK-NEXT: ldrh r3, [r3]116; CHECK-NEXT: ldrh.w lr, [lr]117; CHECK-NEXT: ldrh r4, [r4]118; CHECK-NEXT: ldrh r5, [r5]119; CHECK-NEXT: vmov.16 q0[0], r4120; CHECK-NEXT: ldrh r0, [r0]121; CHECK-NEXT: vmov.16 q0[1], r5122; CHECK-NEXT: ldrh r1, [r1]123; CHECK-NEXT: vmov.16 q0[2], r0124; CHECK-NEXT: vmov.16 q0[3], r1125; CHECK-NEXT: vmov.16 q0[4], r2126; CHECK-NEXT: vmov.16 q0[5], r12127; CHECK-NEXT: vmov.16 q0[6], r3128; CHECK-NEXT: vmov.16 q0[7], lr129; CHECK-NEXT: pop {r4, r5, r7, pc}130entry:131 %offs = load <8 x i8>, ptr %offptr, align 2132 %offs.zext = zext <8 x i8> %offs to <8 x i16>133 %ptrs = getelementptr inbounds i16, ptr %base, <8 x i16> %offs.zext134 %gather = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i16> undef)135 ret <8 x i16> %gather136}137 138define arm_aapcs_vfpcc <8 x i16> @sext_unscaled_i8_i16(ptr %base, ptr %offptr) {139; CHECK-LABEL: sext_unscaled_i8_i16:140; CHECK: @ %bb.0: @ %entry141; CHECK-NEXT: vldrh.u16 q1, [r1]142; CHECK-NEXT: vldrb.s16 q0, [r0, q1]143; CHECK-NEXT: bx lr144entry:145 %offs = load <8 x i16>, ptr %offptr, align 2146 %offs.zext = zext <8 x i16> %offs to <8 x i32>147 %ptrs = getelementptr inbounds i8, ptr %base, <8 x i32> %offs.zext148 %gather = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> %ptrs, i32 1, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i8> undef)149 %gather.sext = sext <8 x i8> %gather to <8 x i16>150 ret <8 x i16> %gather.sext151}152 153define arm_aapcs_vfpcc <8 x i16> @unscaled_i16_i16(ptr %base, ptr %offptr) {154; CHECK-LABEL: unscaled_i16_i16:155; CHECK: @ %bb.0: @ %entry156; CHECK-NEXT: vldrh.u16 q1, [r1]157; CHECK-NEXT: vldrh.u16 q0, [r0, q1]158; CHECK-NEXT: bx lr159entry:160 %offs = load <8 x i16>, ptr %offptr, align 2161 %offs.zext = zext <8 x i16> %offs to <8 x i32>162 %byte_ptrs = getelementptr inbounds i8, ptr %base, <8 x i32> %offs.zext163 %ptrs = bitcast <8 x ptr> %byte_ptrs to <8 x ptr>164 %gather = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i16> undef)165 ret <8 x i16> %gather166}167 168define arm_aapcs_vfpcc <8 x half> @unscaled_f16_i16(ptr %base, ptr %offptr) {169; CHECK-LABEL: unscaled_f16_i16:170; CHECK: @ %bb.0: @ %entry171; CHECK-NEXT: vldrh.u16 q1, [r1]172; CHECK-NEXT: vldrh.u16 q0, [r0, q1]173; CHECK-NEXT: bx lr174entry:175 %offs = load <8 x i16>, ptr %offptr, align 2176 %offs.zext = zext <8 x i16> %offs to <8 x i32>177 %byte_ptrs = getelementptr inbounds i8, ptr %base, <8 x i32> %offs.zext178 %ptrs = bitcast <8 x ptr> %byte_ptrs to <8 x ptr>179 %gather = call <8 x half> @llvm.masked.gather.v8f16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x half> undef)180 ret <8 x half> %gather181}182 183define arm_aapcs_vfpcc <8 x i16> @zext_unsigned_unscaled_i8_i8(ptr %base, ptr %offptr) {184; CHECK-LABEL: zext_unsigned_unscaled_i8_i8:185; CHECK: @ %bb.0: @ %entry186; CHECK-NEXT: vldrb.u16 q1, [r1]187; CHECK-NEXT: vldrb.u16 q0, [r0, q1]188; CHECK-NEXT: bx lr189entry:190 %offs = load <8 x i8>, ptr %offptr, align 1191 %offs.zext = zext <8 x i8> %offs to <8 x i32>192 %ptrs = getelementptr inbounds i8, ptr %base, <8 x i32> %offs.zext193 %gather = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> %ptrs, i32 1, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i8> undef)194 %gather.zext = zext <8 x i8> %gather to <8 x i16>195 ret <8 x i16> %gather.zext196}197 198define arm_aapcs_vfpcc <8 x i16> @sext_unsigned_unscaled_i8_i8(ptr %base, ptr %offptr) {199; CHECK-LABEL: sext_unsigned_unscaled_i8_i8:200; CHECK: @ %bb.0: @ %entry201; CHECK-NEXT: vldrb.u16 q1, [r1]202; CHECK-NEXT: vldrb.s16 q0, [r0, q1]203; CHECK-NEXT: bx lr204entry:205 %offs = load <8 x i8>, ptr %offptr, align 1206 %offs.zext = zext <8 x i8> %offs to <8 x i32>207 %ptrs = getelementptr inbounds i8, ptr %base, <8 x i32> %offs.zext208 %gather = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> %ptrs, i32 1, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i8> undef)209 %gather.sext = sext <8 x i8> %gather to <8 x i16>210 ret <8 x i16> %gather.sext211}212 213define arm_aapcs_vfpcc <8 x i16> @unsigned_unscaled_i16_i8(ptr %base, ptr %offptr) {214; CHECK-LABEL: unsigned_unscaled_i16_i8:215; CHECK: @ %bb.0: @ %entry216; CHECK-NEXT: vldrb.u16 q1, [r1]217; CHECK-NEXT: vldrh.u16 q0, [r0, q1]218; CHECK-NEXT: bx lr219entry:220 %offs = load <8 x i8>, ptr %offptr, align 1221 %offs.zext = zext <8 x i8> %offs to <8 x i32>222 %byte_ptrs = getelementptr inbounds i8, ptr %base, <8 x i32> %offs.zext223 %ptrs = bitcast <8 x ptr> %byte_ptrs to <8 x ptr>224 %gather = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i16> undef)225 ret <8 x i16> %gather226}227 228define arm_aapcs_vfpcc <8 x half> @unsigned_unscaled_f16_i8(ptr %base, ptr %offptr) {229; CHECK-LABEL: unsigned_unscaled_f16_i8:230; CHECK: @ %bb.0: @ %entry231; CHECK-NEXT: vldrb.u16 q1, [r1]232; CHECK-NEXT: vldrh.u16 q0, [r0, q1]233; CHECK-NEXT: bx lr234entry:235 %offs = load <8 x i8>, ptr %offptr, align 1236 %offs.zext = zext <8 x i8> %offs to <8 x i32>237 %byte_ptrs = getelementptr inbounds i8, ptr %base, <8 x i32> %offs.zext238 %ptrs = bitcast <8 x ptr> %byte_ptrs to <8 x ptr>239 %gather = call <8 x half> @llvm.masked.gather.v8f16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x half> undef)240 ret <8 x half> %gather241}242 243declare <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr>, i32, <8 x i1>, <8 x i8>) #1244declare <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr>, i32, <8 x i1>, <8 x i16>) #1245declare <8 x half> @llvm.masked.gather.v8f16.v8p0(<8 x ptr>, i32, <8 x i1>, <8 x half>) #1246