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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedldst -enable-mem-access-versioning=false -tail-predication=force-enabled %s -o - | FileCheck %s3 4define dso_local void @mve_gather_qi_wb(ptr noalias nocapture readonly %A, ptr noalias nocapture readonly %B, ptr noalias nocapture %C, i32 %n, i32 %m, i32 %l) {5; CHECK-LABEL: mve_gather_qi_wb:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: .save {r4, lr}8; CHECK-NEXT: push {r4, lr}9; CHECK-NEXT: add.w r4, r0, r3, lsl #210; CHECK-NEXT: adr r0, .LCPI0_011; CHECK-NEXT: vldrw.u32 q1, [r0]12; CHECK-NEXT: vmov.i32 q0, #0x013; CHECK-NEXT: vadd.i32 q1, q1, r114; CHECK-NEXT: adds r1, r3, #415; CHECK-NEXT: dlstp.32 lr, r316; CHECK-NEXT: .LBB0_1: @ %vector.body17; CHECK-NEXT: @ =>This Inner Loop Header: Depth=118; CHECK-NEXT: vldrw.u32 q2, [r4], #1619; CHECK-NEXT: vldrw.u32 q3, [q1, #80]!20; CHECK-NEXT: vmul.i32 q2, q3, q221; CHECK-NEXT: vadd.i32 q0, q0, q222; CHECK-NEXT: letp lr, .LBB0_123; CHECK-NEXT: @ %bb.2: @ %middle.block24; CHECK-NEXT: vaddv.u32 r0, q025; CHECK-NEXT: str.w r0, [r2, r1, lsl #2]26; CHECK-NEXT: pop {r4, pc}27; CHECK-NEXT: .p2align 428; CHECK-NEXT: @ %bb.3:29; CHECK-NEXT: .LCPI0_0:30; CHECK-NEXT: .long 4294967228 @ 0xffffffbc31; CHECK-NEXT: .long 4294967248 @ 0xffffffd032; CHECK-NEXT: .long 4294967268 @ 0xffffffe433; CHECK-NEXT: .long 4294967288 @ 0xfffffff834entry: ; preds = %middle.35 %add.us.us = add i32 4, %n36 %arrayidx.us.us = getelementptr inbounds i32, ptr %C, i32 %add.us.us37 br label %vector.body38vector.body: ; preds = %vector.body, %entry39 %index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ]40 %vec.phi = phi <4 x i32> [ zeroinitializer, %entry ], [ %7, %vector.body ]41 %vec.ind = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %entry ], [ %vec.ind.next, %vector.body ]42 %0 = add i32 %index, %n43 %1 = getelementptr inbounds i32, ptr %A, i32 %044 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %n)45 %2 = bitcast ptr %1 to ptr46 %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %2, i32 4, <4 x i1> %active.lane.mask, <4 x i32> undef)47 %3 = mul <4 x i32> %vec.ind, <i32 5, i32 5, i32 5, i32 5>48 %4 = add <4 x i32> %3, <i32 3, i32 3, i32 3, i32 3>49 %5 = getelementptr inbounds i32, ptr %B, <4 x i32> %450 %wide.masked.gather = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %5, i32 4, <4 x i1> %active.lane.mask, <4 x i32> undef)51 %6 = mul nsw <4 x i32> %wide.masked.gather, %wide.masked.load52 %7 = add <4 x i32> %vec.phi, %653 %index.next = add i32 %index, 454 %vec.ind.next = add <4 x i32> %vec.ind, <i32 4, i32 4, i32 4, i32 4>55 %8 = icmp eq i32 %index.next, 500056 br i1 %8, label %middle.block, label %vector.body57middle.block: ; preds = %vector.body58 %9 = select <4 x i1> %active.lane.mask, <4 x i32> %7, <4 x i32> %vec.phi59 %10 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %7)60 store i32 %10, ptr %arrayidx.us.us, align 461 %inc21.us.us = add nuw i32 4, 162 %exitcond81.not = icmp eq i32 %inc21.us.us, %n63 br label %end64end: ; preds = %middle.block65 ret void66}67 68define dso_local void @mve_gatherscatter_offset(ptr noalias nocapture readonly %A, ptr noalias nocapture readonly %B, ptr noalias nocapture %C, i32 %n, i32 %m, i32 %l) {69; CHECK-LABEL: mve_gatherscatter_offset:70; CHECK: @ %bb.0: @ %entry71; CHECK-NEXT: .save {r4, lr}72; CHECK-NEXT: push {r4, lr}73; CHECK-NEXT: .vsave {d8, d9}74; CHECK-NEXT: vpush {d8, d9}75; CHECK-NEXT: add.w r4, r0, r3, lsl #276; CHECK-NEXT: adr r0, .LCPI1_077; CHECK-NEXT: vldrw.u32 q2, [r0]78; CHECK-NEXT: add.w r12, r3, #479; CHECK-NEXT: vmov.i32 q0, #0x080; CHECK-NEXT: vmov.i32 q1, #0x1481; CHECK-NEXT: dlstp.32 lr, r382; CHECK-NEXT: .LBB1_1: @ %vector.body83; CHECK-NEXT: @ =>This Inner Loop Header: Depth=184; CHECK-NEXT: vldrw.u32 q3, [r1, q2, uxtw #2]85; CHECK-NEXT: vldrw.u32 q4, [r4], #1686; CHECK-NEXT: vmul.i32 q3, q3, q487; CHECK-NEXT: vstrw.32 q3, [r1, q2, uxtw #2]88; CHECK-NEXT: vadd.i32 q2, q2, q189; CHECK-NEXT: vadd.i32 q0, q0, q390; CHECK-NEXT: letp lr, .LBB1_191; CHECK-NEXT: @ %bb.2: @ %middle.block92; CHECK-NEXT: vaddv.u32 r0, q093; CHECK-NEXT: str.w r0, [r2, r12, lsl #2]94; CHECK-NEXT: vpop {d8, d9}95; CHECK-NEXT: pop {r4, pc}96; CHECK-NEXT: .p2align 497; CHECK-NEXT: @ %bb.3:98; CHECK-NEXT: .LCPI1_0:99; CHECK-NEXT: .long 3 @ 0x3100; CHECK-NEXT: .long 8 @ 0x8101; CHECK-NEXT: .long 13 @ 0xd102; CHECK-NEXT: .long 18 @ 0x12103entry: ; preds = %middle.104 %add.us.us = add i32 4, %n105 %arrayidx.us.us = getelementptr inbounds i32, ptr %C, i32 %add.us.us106 br label %vector.body107vector.body: ; preds = %vector.body, %entry108 %index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ]109 %vec.phi = phi <4 x i32> [ zeroinitializer, %entry ], [ %7, %vector.body ]110 %vec.ind = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %entry ], [ %vec.ind.next, %vector.body ]111 %0 = add i32 %index, %n112 %1 = getelementptr inbounds i32, ptr %A, i32 %0113 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %n)114 %2 = bitcast ptr %1 to ptr115 %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %2, i32 4, <4 x i1> %active.lane.mask, <4 x i32> undef)116 %3 = mul <4 x i32> %vec.ind, <i32 5, i32 5, i32 5, i32 5>117 %4 = add <4 x i32> %3, <i32 3, i32 3, i32 3, i32 3>118 %5 = getelementptr inbounds i32, ptr %B, <4 x i32> %4119 %wide.masked.gather = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %5, i32 4, <4 x i1> %active.lane.mask, <4 x i32> undef)120 %6 = mul nsw <4 x i32> %wide.masked.gather, %wide.masked.load121 call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %6, <4 x ptr> %5, i32 4, <4 x i1> %active.lane.mask)122 %7 = add <4 x i32> %vec.phi, %6123 %index.next = add i32 %index, 4124 %vec.ind.next = add <4 x i32> %vec.ind, <i32 4, i32 4, i32 4, i32 4>125 %8 = icmp eq i32 %index.next, 5000126 br i1 %8, label %middle.block, label %vector.body127middle.block: ; preds = %vector.body128 %9 = select <4 x i1> %active.lane.mask, <4 x i32> %7, <4 x i32> %vec.phi129 %10 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %7)130 store i32 %10, ptr %arrayidx.us.us, align 4131 %inc21.us.us = add nuw i32 4, 1132 %exitcond81.not = icmp eq i32 %inc21.us.us, %n133 br label %end134end: ; preds = %middle.block135 ret void136}137 138define dso_local void @mve_scatter_qi(ptr noalias nocapture readonly %A, ptr noalias nocapture readonly %B, ptr noalias nocapture %C, i32 %n, i32 %m, i32 %l) {139; CHECK-LABEL: mve_scatter_qi:140; CHECK: @ %bb.0: @ %entry141; CHECK-NEXT: .save {r4, lr}142; CHECK-NEXT: push {r4, lr}143; CHECK-NEXT: add.w r4, r0, r3, lsl #2144; CHECK-NEXT: adr r0, .LCPI2_0145; CHECK-NEXT: vldrw.u32 q1, [r0]146; CHECK-NEXT: add.w r12, r3, #4147; CHECK-NEXT: vmov.i32 q0, #0x0148; CHECK-NEXT: movw lr, #1250149; CHECK-NEXT: vadd.i32 q1, q1, r1150; CHECK-NEXT: movs r1, #3151; CHECK-NEXT: .LBB2_1: @ %vector.body152; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1153; CHECK-NEXT: vctp.32 r3154; CHECK-NEXT: subs r3, #4155; CHECK-NEXT: vpst156; CHECK-NEXT: vldrwt.u32 q2, [r4], #16157; CHECK-NEXT: vmul.i32 q3, q2, r1158; CHECK-NEXT: vmla.i32 q0, q2, r1159; CHECK-NEXT: vpst160; CHECK-NEXT: vstrwt.32 q3, [q1, #80]!161; CHECK-NEXT: le lr, .LBB2_1162; CHECK-NEXT: @ %bb.2: @ %middle.block163; CHECK-NEXT: vaddv.u32 r0, q0164; CHECK-NEXT: str.w r0, [r2, r12, lsl #2]165; CHECK-NEXT: pop {r4, pc}166; CHECK-NEXT: .p2align 4167; CHECK-NEXT: @ %bb.3:168; CHECK-NEXT: .LCPI2_0:169; CHECK-NEXT: .long 4294967228 @ 0xffffffbc170; CHECK-NEXT: .long 4294967248 @ 0xffffffd0171; CHECK-NEXT: .long 4294967268 @ 0xffffffe4172; CHECK-NEXT: .long 4294967288 @ 0xfffffff8173entry: ; preds = %middle.174 %add.us.us = add i32 4, %n175 %arrayidx.us.us = getelementptr inbounds i32, ptr %C, i32 %add.us.us176 br label %vector.body177vector.body: ; preds = %vector.body, %entry178 %index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ]179 %vec.phi = phi <4 x i32> [ zeroinitializer, %entry ], [ %7, %vector.body ]180 %vec.ind = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %entry ], [ %vec.ind.next, %vector.body ]181 %0 = add i32 %index, %n182 %1 = getelementptr inbounds i32, ptr %A, i32 %0183 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %n)184 %2 = bitcast ptr %1 to ptr185 %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %2, i32 4, <4 x i1> %active.lane.mask, <4 x i32> undef)186 %3 = mul <4 x i32> %vec.ind, <i32 5, i32 5, i32 5, i32 5>187 %4 = add <4 x i32> %3, <i32 3, i32 3, i32 3, i32 3>188 %5 = getelementptr inbounds i32, ptr %B, <4 x i32> %4189 %6 = mul nsw <4 x i32> <i32 3, i32 3, i32 3, i32 3>, %wide.masked.load190 call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %6, <4 x ptr> %5, i32 4, <4 x i1> %active.lane.mask)191 %7 = add <4 x i32> %vec.phi, %6192 %index.next = add i32 %index, 4193 %vec.ind.next = add <4 x i32> %vec.ind, <i32 4, i32 4, i32 4, i32 4>194 %8 = icmp eq i32 %index.next, 5000195 br i1 %8, label %middle.block, label %vector.body196middle.block: ; preds = %vector.body197 %9 = select <4 x i1> %active.lane.mask, <4 x i32> %7, <4 x i32> %vec.phi198 %10 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %7)199 store i32 %10, ptr %arrayidx.us.us, align 4200 %inc21.us.us = add nuw i32 4, 1201 %exitcond81.not = icmp eq i32 %inc21.us.us, %n202 br label %end203end: ; preds = %middle.block204 ret void205}206 207define void @justoffsets(ptr noalias nocapture readonly %r, ptr noalias nocapture %w, i32 %N) {208; CHECK-LABEL: justoffsets:209; CHECK: @ %bb.0: @ %entry210; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}211; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}212; CHECK-NEXT: .pad #4213; CHECK-NEXT: sub sp, #4214; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}215; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}216; CHECK-NEXT: cmp r2, #0217; CHECK-NEXT: beq .LBB3_3218; CHECK-NEXT: @ %bb.1: @ %vector.ph219; CHECK-NEXT: adr r5, .LCPI3_1220; CHECK-NEXT: adr r4, .LCPI3_0221; CHECK-NEXT: vldrw.u32 q0, [r5]222; CHECK-NEXT: adr r5, .LCPI3_2223; CHECK-NEXT: movw r9, #47888224; CHECK-NEXT: movw r10, #50417225; CHECK-NEXT: vldrw.u32 q1, [r5]226; CHECK-NEXT: vldrw.u32 q2, [r4]227; CHECK-NEXT: movw r4, #32769228; CHECK-NEXT: movw r12, #7471229; CHECK-NEXT: mov.w r3, #32768230; CHECK-NEXT: movw r11, #38470231; CHECK-NEXT: movw r8, #19595232; CHECK-NEXT: movt r9, #65535233; CHECK-NEXT: movt r10, #65535234; CHECK-NEXT: movw r7, #32767235; CHECK-NEXT: movt r4, #65535236; CHECK-NEXT: movw r5, #13282237; CHECK-NEXT: movw r6, #19485238; CHECK-NEXT: dlstp.32 lr, r2239; CHECK-NEXT: .LBB3_2: @ %vector.body240; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1241; CHECK-NEXT: vldrb.u32 q4, [r0, q0]242; CHECK-NEXT: vldrb.u32 q3, [r0, q1]243; CHECK-NEXT: vldrb.u32 q5, [r0, q2]244; CHECK-NEXT: adds r0, #12245; CHECK-NEXT: vmul.i32 q6, q4, r11246; CHECK-NEXT: vmla.i32 q6, q3, r8247; CHECK-NEXT: vmla.i32 q6, q5, r12248; CHECK-NEXT: vadd.i32 q6, q6, r3249; CHECK-NEXT: vshr.u32 q6, q6, #16250; CHECK-NEXT: vstrb.32 q6, [r1, q1]251; CHECK-NEXT: vmul.i32 q6, q4, r4252; CHECK-NEXT: vmul.i32 q4, q4, r10253; CHECK-NEXT: vmla.i32 q6, q3, r5254; CHECK-NEXT: vmla.i32 q4, q3, r7255; CHECK-NEXT: vmla.i32 q6, q5, r6256; CHECK-NEXT: vmla.i32 q4, q5, r9257; CHECK-NEXT: vadd.i32 q6, q6, r3258; CHECK-NEXT: vadd.i32 q3, q4, r3259; CHECK-NEXT: vshr.u32 q6, q6, #16260; CHECK-NEXT: vshr.u32 q3, q3, #16261; CHECK-NEXT: vstrb.32 q3, [r1, q0]262; CHECK-NEXT: vstrb.32 q6, [r1, q2]263; CHECK-NEXT: adds r1, #12264; CHECK-NEXT: letp lr, .LBB3_2265; CHECK-NEXT: .LBB3_3: @ %for.cond.cleanup266; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}267; CHECK-NEXT: add sp, #4268; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}269; CHECK-NEXT: .p2align 4270; CHECK-NEXT: @ %bb.4:271; CHECK-NEXT: .LCPI3_0:272; CHECK-NEXT: .long 2 @ 0x2273; CHECK-NEXT: .long 5 @ 0x5274; CHECK-NEXT: .long 8 @ 0x8275; CHECK-NEXT: .long 11 @ 0xb276; CHECK-NEXT: .LCPI3_1:277; CHECK-NEXT: .long 1 @ 0x1278; CHECK-NEXT: .long 4 @ 0x4279; CHECK-NEXT: .long 7 @ 0x7280; CHECK-NEXT: .long 10 @ 0xa281; CHECK-NEXT: .LCPI3_2:282; CHECK-NEXT: .long 0 @ 0x0283; CHECK-NEXT: .long 3 @ 0x3284; CHECK-NEXT: .long 6 @ 0x6285; CHECK-NEXT: .long 9 @ 0x9286entry:287 %cmp47.not = icmp eq i32 %N, 0288 br i1 %cmp47.not, label %for.cond.cleanup, label %vector.ph289 290vector.ph: ; preds = %vector.memcheck291 %n.rnd.up = add i32 %N, 3292 %n.vec = and i32 %n.rnd.up, -4293 br label %vector.body294 295vector.body: ; preds = %vector.body, %vector.ph296 %pointer.phi = phi ptr [ %r, %vector.ph ], [ %ptr.ind, %vector.body ]297 %pointer.phi55 = phi ptr [ %w, %vector.ph ], [ %ptr.ind56, %vector.body ]298 %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]299 %l1 = getelementptr i8, ptr %pointer.phi, <4 x i32> <i32 0, i32 3, i32 6, i32 9>300 %l2 = getelementptr i8, ptr %pointer.phi55, <4 x i32> <i32 0, i32 3, i32 6, i32 9>301 %l3 = getelementptr inbounds i8, <4 x ptr> %l1, i32 1302 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %N)303 %wide.masked.gather = call <4 x i8> @llvm.masked.gather.v4i8.v4p0(<4 x ptr> %l1, i32 1, <4 x i1> %active.lane.mask, <4 x i8> undef)304 %l4 = getelementptr inbounds i8, <4 x ptr> %l1, i32 2305 %wide.masked.gather57 = call <4 x i8> @llvm.masked.gather.v4i8.v4p0(<4 x ptr> %l3, i32 1, <4 x i1> %active.lane.mask, <4 x i8> undef)306 %wide.masked.gather58 = call <4 x i8> @llvm.masked.gather.v4i8.v4p0(<4 x ptr> %l4, i32 1, <4 x i1> %active.lane.mask, <4 x i8> undef)307 %l5 = zext <4 x i8> %wide.masked.gather to <4 x i32>308 %l6 = mul nuw nsw <4 x i32> %l5, <i32 19595, i32 19595, i32 19595, i32 19595>309 %l7 = zext <4 x i8> %wide.masked.gather57 to <4 x i32>310 %l8 = mul nuw nsw <4 x i32> %l7, <i32 38470, i32 38470, i32 38470, i32 38470>311 %l9 = zext <4 x i8> %wide.masked.gather58 to <4 x i32>312 %l10 = mul nuw nsw <4 x i32> %l9, <i32 7471, i32 7471, i32 7471, i32 7471>313 %l11 = add nuw nsw <4 x i32> %l6, <i32 32768, i32 32768, i32 32768, i32 32768>314 %l12 = add nuw nsw <4 x i32> %l11, %l8315 %l13 = add nuw nsw <4 x i32> %l12, %l10316 %l14 = lshr <4 x i32> %l13, <i32 16, i32 16, i32 16, i32 16>317 %l15 = trunc <4 x i32> %l14 to <4 x i8>318 %l16 = mul nuw nsw <4 x i32> %l5, <i32 32767, i32 32767, i32 32767, i32 32767>319 %l17 = mul nsw <4 x i32> %l7, <i32 -15119, i32 -15119, i32 -15119, i32 -15119>320 %l18 = mul nsw <4 x i32> %l9, <i32 -17648, i32 -17648, i32 -17648, i32 -17648>321 %l19 = add nuw nsw <4 x i32> %l16, <i32 32768, i32 32768, i32 32768, i32 32768>322 %l20 = add nsw <4 x i32> %l19, %l17323 %l21 = add nsw <4 x i32> %l20, %l18324 %l22 = lshr <4 x i32> %l21, <i32 16, i32 16, i32 16, i32 16>325 %l23 = trunc <4 x i32> %l22 to <4 x i8>326 %l24 = mul nuw nsw <4 x i32> %l5, <i32 13282, i32 13282, i32 13282, i32 13282>327 %l25 = mul nsw <4 x i32> %l7, <i32 -32767, i32 -32767, i32 -32767, i32 -32767>328 %l26 = mul nuw nsw <4 x i32> %l9, <i32 19485, i32 19485, i32 19485, i32 19485>329 %l27 = add nuw nsw <4 x i32> %l24, <i32 32768, i32 32768, i32 32768, i32 32768>330 %l28 = add nsw <4 x i32> %l27, %l25331 %l29 = add nsw <4 x i32> %l28, %l26332 %l30 = lshr <4 x i32> %l29, <i32 16, i32 16, i32 16, i32 16>333 %l31 = trunc <4 x i32> %l30 to <4 x i8>334 %l32 = getelementptr inbounds i8, <4 x ptr> %l2, i32 1335 call void @llvm.masked.scatter.v4i8.v4p0(<4 x i8> %l15, <4 x ptr> %l2, i32 1, <4 x i1> %active.lane.mask)336 %l33 = getelementptr inbounds i8, <4 x ptr> %l2, i32 2337 call void @llvm.masked.scatter.v4i8.v4p0(<4 x i8> %l23, <4 x ptr> %l32, i32 1, <4 x i1> %active.lane.mask)338 call void @llvm.masked.scatter.v4i8.v4p0(<4 x i8> %l31, <4 x ptr> %l33, i32 1, <4 x i1> %active.lane.mask)339 %index.next = add i32 %index, 4340 %l34 = icmp eq i32 %index.next, %n.vec341 %ptr.ind = getelementptr i8, ptr %pointer.phi, i32 12342 %ptr.ind56 = getelementptr i8, ptr %pointer.phi55, i32 12343 br i1 %l34, label %for.cond.cleanup, label %vector.body344 345for.cond.cleanup: ; preds = %vector.body, %for.body, %entry346 ret void347}348 349declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)350declare <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr>, i32, <4 x i1>, <4 x i32>)351declare <4 x i8> @llvm.masked.gather.v4i8.v4p0(<4 x ptr>, i32, <4 x i1>, <4 x i8>)352declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)353declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32, <4 x i1>, <4 x i32>)354declare void @llvm.masked.scatter.v4i32.v4p0(<4 x i32>, <4 x ptr>, i32, <4 x i1>)355declare void @llvm.masked.scatter.v4i8.v4p0(<4 x i8>, <4 x ptr>, i32, <4 x i1>)356