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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s3 4define arm_aapcs_vfpcc <16 x i8> @vhadds_v16i8(<16 x i8> %x, <16 x i8> %y) {5; CHECK-LABEL: vhadds_v16i8:6; CHECK: @ %bb.0:7; CHECK-NEXT: vadd.i8 q0, q0, q18; CHECK-NEXT: vshr.s8 q0, q0, #19; CHECK-NEXT: bx lr10 %add = add <16 x i8> %x, %y11 %half = ashr <16 x i8> %add, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>12 ret <16 x i8> %half13}14define arm_aapcs_vfpcc <16 x i8> @vhaddu_v16i8(<16 x i8> %x, <16 x i8> %y) {15; CHECK-LABEL: vhaddu_v16i8:16; CHECK: @ %bb.0:17; CHECK-NEXT: vadd.i8 q0, q0, q118; CHECK-NEXT: vshr.u8 q0, q0, #119; CHECK-NEXT: bx lr20 %add = add <16 x i8> %x, %y21 %half = lshr <16 x i8> %add, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>22 ret <16 x i8> %half23}24define arm_aapcs_vfpcc <8 x i16> @vhadds_v8i16(<8 x i16> %x, <8 x i16> %y) {25; CHECK-LABEL: vhadds_v8i16:26; CHECK: @ %bb.0:27; CHECK-NEXT: vadd.i16 q0, q0, q128; CHECK-NEXT: vshr.s16 q0, q0, #129; CHECK-NEXT: bx lr30 %add = add <8 x i16> %x, %y31 %half = ashr <8 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>32 ret <8 x i16> %half33}34define arm_aapcs_vfpcc <8 x i16> @vhaddu_v8i16(<8 x i16> %x, <8 x i16> %y) {35; CHECK-LABEL: vhaddu_v8i16:36; CHECK: @ %bb.0:37; CHECK-NEXT: vadd.i16 q0, q0, q138; CHECK-NEXT: vshr.u16 q0, q0, #139; CHECK-NEXT: bx lr40 %add = add <8 x i16> %x, %y41 %half = lshr <8 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>42 ret <8 x i16> %half43}44define arm_aapcs_vfpcc <4 x i32> @vhadds_v4i32(<4 x i32> %x, <4 x i32> %y) {45; CHECK-LABEL: vhadds_v4i32:46; CHECK: @ %bb.0:47; CHECK-NEXT: vadd.i32 q0, q0, q148; CHECK-NEXT: vshr.s32 q0, q0, #149; CHECK-NEXT: bx lr50 %add = add <4 x i32> %x, %y51 %half = ashr <4 x i32> %add, <i32 1, i32 1, i32 1, i32 1>52 ret <4 x i32> %half53}54define arm_aapcs_vfpcc <4 x i32> @vhaddu_v4i32(<4 x i32> %x, <4 x i32> %y) {55; CHECK-LABEL: vhaddu_v4i32:56; CHECK: @ %bb.0:57; CHECK-NEXT: vadd.i32 q0, q0, q158; CHECK-NEXT: vshr.u32 q0, q0, #159; CHECK-NEXT: bx lr60 %add = add <4 x i32> %x, %y61 %half = lshr <4 x i32> %add, <i32 1, i32 1, i32 1, i32 1>62 ret <4 x i32> %half63}64define arm_aapcs_vfpcc <16 x i8> @vhsubs_v16i8(<16 x i8> %x, <16 x i8> %y) {65; CHECK-LABEL: vhsubs_v16i8:66; CHECK: @ %bb.0:67; CHECK-NEXT: vsub.i8 q0, q0, q168; CHECK-NEXT: vshr.s8 q0, q0, #169; CHECK-NEXT: bx lr70 %sub = sub <16 x i8> %x, %y71 %half = ashr <16 x i8> %sub, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>72 ret <16 x i8> %half73}74define arm_aapcs_vfpcc <16 x i8> @vhsubu_v16i8(<16 x i8> %x, <16 x i8> %y) {75; CHECK-LABEL: vhsubu_v16i8:76; CHECK: @ %bb.0:77; CHECK-NEXT: vsub.i8 q0, q0, q178; CHECK-NEXT: vshr.u8 q0, q0, #179; CHECK-NEXT: bx lr80 %sub = sub <16 x i8> %x, %y81 %half = lshr <16 x i8> %sub, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>82 ret <16 x i8> %half83}84define arm_aapcs_vfpcc <8 x i16> @vhsubs_v8i16(<8 x i16> %x, <8 x i16> %y) {85; CHECK-LABEL: vhsubs_v8i16:86; CHECK: @ %bb.0:87; CHECK-NEXT: vsub.i16 q0, q0, q188; CHECK-NEXT: vshr.s16 q0, q0, #189; CHECK-NEXT: bx lr90 %sub = sub <8 x i16> %x, %y91 %half = ashr <8 x i16> %sub, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>92 ret <8 x i16> %half93}94define arm_aapcs_vfpcc <8 x i16> @vhsubu_v8i16(<8 x i16> %x, <8 x i16> %y) {95; CHECK-LABEL: vhsubu_v8i16:96; CHECK: @ %bb.0:97; CHECK-NEXT: vsub.i16 q0, q0, q198; CHECK-NEXT: vshr.u16 q0, q0, #199; CHECK-NEXT: bx lr100 %sub = sub <8 x i16> %x, %y101 %half = lshr <8 x i16> %sub, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>102 ret <8 x i16> %half103}104define arm_aapcs_vfpcc <4 x i32> @vhsubs_v4i32(<4 x i32> %x, <4 x i32> %y) {105; CHECK-LABEL: vhsubs_v4i32:106; CHECK: @ %bb.0:107; CHECK-NEXT: vsub.i32 q0, q0, q1108; CHECK-NEXT: vshr.s32 q0, q0, #1109; CHECK-NEXT: bx lr110 %sub = sub <4 x i32> %x, %y111 %half = ashr <4 x i32> %sub, <i32 1, i32 1, i32 1, i32 1>112 ret <4 x i32> %half113}114define arm_aapcs_vfpcc <4 x i32> @vhsubu_v4i32(<4 x i32> %x, <4 x i32> %y) {115; CHECK-LABEL: vhsubu_v4i32:116; CHECK: @ %bb.0:117; CHECK-NEXT: vsub.i32 q0, q0, q1118; CHECK-NEXT: vshr.u32 q0, q0, #1119; CHECK-NEXT: bx lr120 %sub = sub <4 x i32> %x, %y121 %half = lshr <4 x i32> %sub, <i32 1, i32 1, i32 1, i32 1>122 ret <4 x i32> %half123}124 125define arm_aapcs_vfpcc <16 x i8> @vhadds_v16i8_nw(<16 x i8> %x, <16 x i8> %y) {126; CHECK-LABEL: vhadds_v16i8_nw:127; CHECK: @ %bb.0:128; CHECK-NEXT: vhadd.s8 q0, q0, q1129; CHECK-NEXT: bx lr130 %add = add nsw <16 x i8> %x, %y131 %half = ashr <16 x i8> %add, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>132 ret <16 x i8> %half133}134define arm_aapcs_vfpcc <16 x i8> @vhaddu_v16i8_nw(<16 x i8> %x, <16 x i8> %y) {135; CHECK-LABEL: vhaddu_v16i8_nw:136; CHECK: @ %bb.0:137; CHECK-NEXT: vhadd.u8 q0, q0, q1138; CHECK-NEXT: bx lr139 %add = add nuw <16 x i8> %x, %y140 %half = lshr <16 x i8> %add, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>141 ret <16 x i8> %half142}143define arm_aapcs_vfpcc <8 x i16> @vhadds_v8i16_nw(<8 x i16> %x, <8 x i16> %y) {144; CHECK-LABEL: vhadds_v8i16_nw:145; CHECK: @ %bb.0:146; CHECK-NEXT: vhadd.s16 q0, q0, q1147; CHECK-NEXT: bx lr148 %add = add nsw <8 x i16> %x, %y149 %half = ashr <8 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>150 ret <8 x i16> %half151}152define arm_aapcs_vfpcc <8 x i16> @vhaddu_v8i16_nw(<8 x i16> %x, <8 x i16> %y) {153; CHECK-LABEL: vhaddu_v8i16_nw:154; CHECK: @ %bb.0:155; CHECK-NEXT: vhadd.u16 q0, q0, q1156; CHECK-NEXT: bx lr157 %add = add nuw <8 x i16> %x, %y158 %half = lshr <8 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>159 ret <8 x i16> %half160}161define arm_aapcs_vfpcc <4 x i32> @vhadds_v4i32_nw(<4 x i32> %x, <4 x i32> %y) {162; CHECK-LABEL: vhadds_v4i32_nw:163; CHECK: @ %bb.0:164; CHECK-NEXT: vhadd.s32 q0, q0, q1165; CHECK-NEXT: bx lr166 %add = add nsw <4 x i32> %x, %y167 %half = ashr <4 x i32> %add, <i32 1, i32 1, i32 1, i32 1>168 ret <4 x i32> %half169}170define arm_aapcs_vfpcc <4 x i32> @vhaddu_v4i32_nw(<4 x i32> %x, <4 x i32> %y) {171; CHECK-LABEL: vhaddu_v4i32_nw:172; CHECK: @ %bb.0:173; CHECK-NEXT: vhadd.u32 q0, q0, q1174; CHECK-NEXT: bx lr175 %add = add nuw <4 x i32> %x, %y176 %half = lshr <4 x i32> %add, <i32 1, i32 1, i32 1, i32 1>177 ret <4 x i32> %half178}179define arm_aapcs_vfpcc <16 x i8> @vhsubs_v16i8_nw(<16 x i8> %x, <16 x i8> %y) {180; CHECK-LABEL: vhsubs_v16i8_nw:181; CHECK: @ %bb.0:182; CHECK-NEXT: vhsub.s8 q0, q0, q1183; CHECK-NEXT: bx lr184 %sub = sub nsw <16 x i8> %x, %y185 %half = ashr <16 x i8> %sub, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>186 ret <16 x i8> %half187}188define arm_aapcs_vfpcc <16 x i8> @vhsubu_v16i8_nw(<16 x i8> %x, <16 x i8> %y) {189; CHECK-LABEL: vhsubu_v16i8_nw:190; CHECK: @ %bb.0:191; CHECK-NEXT: vhsub.u8 q0, q0, q1192; CHECK-NEXT: bx lr193 %sub = sub nuw <16 x i8> %x, %y194 %half = lshr <16 x i8> %sub, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>195 ret <16 x i8> %half196}197define arm_aapcs_vfpcc <8 x i16> @vhsubs_v8i16_nw(<8 x i16> %x, <8 x i16> %y) {198; CHECK-LABEL: vhsubs_v8i16_nw:199; CHECK: @ %bb.0:200; CHECK-NEXT: vhsub.s16 q0, q0, q1201; CHECK-NEXT: bx lr202 %sub = sub nsw <8 x i16> %x, %y203 %half = ashr <8 x i16> %sub, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>204 ret <8 x i16> %half205}206define arm_aapcs_vfpcc <8 x i16> @vhsubu_v8i16_nw(<8 x i16> %x, <8 x i16> %y) {207; CHECK-LABEL: vhsubu_v8i16_nw:208; CHECK: @ %bb.0:209; CHECK-NEXT: vhsub.u16 q0, q0, q1210; CHECK-NEXT: bx lr211 %sub = sub nuw <8 x i16> %x, %y212 %half = lshr <8 x i16> %sub, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>213 ret <8 x i16> %half214}215define arm_aapcs_vfpcc <4 x i32> @vhsubs_v4i32_nw(<4 x i32> %x, <4 x i32> %y) {216; CHECK-LABEL: vhsubs_v4i32_nw:217; CHECK: @ %bb.0:218; CHECK-NEXT: vhsub.s32 q0, q0, q1219; CHECK-NEXT: bx lr220 %sub = sub nsw <4 x i32> %x, %y221 %half = ashr <4 x i32> %sub, <i32 1, i32 1, i32 1, i32 1>222 ret <4 x i32> %half223}224define arm_aapcs_vfpcc <4 x i32> @vhsubu_v4i32_nw(<4 x i32> %x, <4 x i32> %y) {225; CHECK-LABEL: vhsubu_v4i32_nw:226; CHECK: @ %bb.0:227; CHECK-NEXT: vhsub.u32 q0, q0, q1228; CHECK-NEXT: bx lr229 %sub = sub nuw <4 x i32> %x, %y230 %half = lshr <4 x i32> %sub, <i32 1, i32 1, i32 1, i32 1>231 ret <4 x i32> %half232}233define arm_aapcs_vfpcc <16 x i8> @vrhadds_v16i8(<16 x i8> %x, <16 x i8> %y) {234; CHECK-LABEL: vrhadds_v16i8:235; CHECK: @ %bb.0:236; CHECK-NEXT: vadd.i8 q0, q0, q1237; CHECK-NEXT: movs r0, #1238; CHECK-NEXT: vadd.i8 q0, q0, r0239; CHECK-NEXT: vshr.s8 q0, q0, #1240; CHECK-NEXT: bx lr241 %add = add <16 x i8> %x, %y242 %round = add <16 x i8> %add, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>243 %half = ashr <16 x i8> %round, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>244 ret <16 x i8> %half245}246define arm_aapcs_vfpcc <16 x i8> @vrhaddu_v16i8(<16 x i8> %x, <16 x i8> %y) {247; CHECK-LABEL: vrhaddu_v16i8:248; CHECK: @ %bb.0:249; CHECK-NEXT: vadd.i8 q0, q0, q1250; CHECK-NEXT: movs r0, #1251; CHECK-NEXT: vadd.i8 q0, q0, r0252; CHECK-NEXT: vshr.u8 q0, q0, #1253; CHECK-NEXT: bx lr254 %add = add <16 x i8> %x, %y255 %round = add <16 x i8> %add, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>256 %half = lshr <16 x i8> %round, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>257 ret <16 x i8> %half258}259define arm_aapcs_vfpcc <8 x i16> @vrhadds_v8i16(<8 x i16> %x, <8 x i16> %y) {260; CHECK-LABEL: vrhadds_v8i16:261; CHECK: @ %bb.0:262; CHECK-NEXT: vadd.i16 q0, q0, q1263; CHECK-NEXT: movs r0, #1264; CHECK-NEXT: vadd.i16 q0, q0, r0265; CHECK-NEXT: vshr.s16 q0, q0, #1266; CHECK-NEXT: bx lr267 %add = add <8 x i16> %x, %y268 %round = add <8 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>269 %half = ashr <8 x i16> %round, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>270 ret <8 x i16> %half271}272define arm_aapcs_vfpcc <8 x i16> @vrhaddu_v8i16(<8 x i16> %x, <8 x i16> %y) {273; CHECK-LABEL: vrhaddu_v8i16:274; CHECK: @ %bb.0:275; CHECK-NEXT: vadd.i16 q0, q0, q1276; CHECK-NEXT: movs r0, #1277; CHECK-NEXT: vadd.i16 q0, q0, r0278; CHECK-NEXT: vshr.u16 q0, q0, #1279; CHECK-NEXT: bx lr280 %add = add <8 x i16> %x, %y281 %round = add <8 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>282 %half = lshr <8 x i16> %round, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>283 ret <8 x i16> %half284}285define arm_aapcs_vfpcc <4 x i32> @vrhadds_v4i32(<4 x i32> %x, <4 x i32> %y) {286; CHECK-LABEL: vrhadds_v4i32:287; CHECK: @ %bb.0:288; CHECK-NEXT: vadd.i32 q0, q0, q1289; CHECK-NEXT: movs r0, #1290; CHECK-NEXT: vadd.i32 q0, q0, r0291; CHECK-NEXT: vshr.s32 q0, q0, #1292; CHECK-NEXT: bx lr293 %add = add <4 x i32> %x, %y294 %round = add <4 x i32> %add, <i32 1, i32 1, i32 1, i32 1>295 %half = ashr <4 x i32> %round, <i32 1, i32 1, i32 1, i32 1>296 ret <4 x i32> %half297}298define arm_aapcs_vfpcc <4 x i32> @vrhaddu_v4i32(<4 x i32> %x, <4 x i32> %y) {299; CHECK-LABEL: vrhaddu_v4i32:300; CHECK: @ %bb.0:301; CHECK-NEXT: vadd.i32 q0, q0, q1302; CHECK-NEXT: movs r0, #1303; CHECK-NEXT: vadd.i32 q0, q0, r0304; CHECK-NEXT: vshr.u32 q0, q0, #1305; CHECK-NEXT: bx lr306 %add = add <4 x i32> %x, %y307 %round = add <4 x i32> %add, <i32 1, i32 1, i32 1, i32 1>308 %half = lshr <4 x i32> %round, <i32 1, i32 1, i32 1, i32 1>309 ret <4 x i32> %half310}311define arm_aapcs_vfpcc <16 x i8> @vrhadds_v16i8_nwop(<16 x i8> %x, <16 x i8> %y) {312; CHECK-LABEL: vrhadds_v16i8_nwop:313; CHECK: @ %bb.0:314; CHECK-NEXT: vadd.i8 q0, q0, q1315; CHECK-NEXT: movs r0, #1316; CHECK-NEXT: vadd.i8 q0, q0, r0317; CHECK-NEXT: vshr.s8 q0, q0, #1318; CHECK-NEXT: bx lr319 %add = add nsw <16 x i8> %x, %y320 %round = add <16 x i8> %add, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>321 %half = ashr <16 x i8> %round, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>322 ret <16 x i8> %half323}324define arm_aapcs_vfpcc <16 x i8> @vrhaddu_v16i8_nwop(<16 x i8> %x, <16 x i8> %y) {325; CHECK-LABEL: vrhaddu_v16i8_nwop:326; CHECK: @ %bb.0:327; CHECK-NEXT: vadd.i8 q0, q0, q1328; CHECK-NEXT: movs r0, #1329; CHECK-NEXT: vadd.i8 q0, q0, r0330; CHECK-NEXT: vshr.u8 q0, q0, #1331; CHECK-NEXT: bx lr332 %add = add nuw <16 x i8> %x, %y333 %round = add <16 x i8> %add, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>334 %half = lshr <16 x i8> %round, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>335 ret <16 x i8> %half336}337define arm_aapcs_vfpcc <8 x i16> @vrhadds_v8i16_nwop(<8 x i16> %x, <8 x i16> %y) {338; CHECK-LABEL: vrhadds_v8i16_nwop:339; CHECK: @ %bb.0:340; CHECK-NEXT: vadd.i16 q0, q0, q1341; CHECK-NEXT: movs r0, #1342; CHECK-NEXT: vadd.i16 q0, q0, r0343; CHECK-NEXT: vshr.s16 q0, q0, #1344; CHECK-NEXT: bx lr345 %add = add nsw <8 x i16> %x, %y346 %round = add <8 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>347 %half = ashr <8 x i16> %round, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>348 ret <8 x i16> %half349}350define arm_aapcs_vfpcc <8 x i16> @vrhaddu_v8i16_nwop(<8 x i16> %x, <8 x i16> %y) {351; CHECK-LABEL: vrhaddu_v8i16_nwop:352; CHECK: @ %bb.0:353; CHECK-NEXT: vadd.i16 q0, q0, q1354; CHECK-NEXT: movs r0, #1355; CHECK-NEXT: vadd.i16 q0, q0, r0356; CHECK-NEXT: vshr.u16 q0, q0, #1357; CHECK-NEXT: bx lr358 %add = add nuw <8 x i16> %x, %y359 %round = add <8 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>360 %half = lshr <8 x i16> %round, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>361 ret <8 x i16> %half362}363define arm_aapcs_vfpcc <4 x i32> @vrhadds_v4i32_nwop(<4 x i32> %x, <4 x i32> %y) {364; CHECK-LABEL: vrhadds_v4i32_nwop:365; CHECK: @ %bb.0:366; CHECK-NEXT: vadd.i32 q0, q0, q1367; CHECK-NEXT: movs r0, #1368; CHECK-NEXT: vadd.i32 q0, q0, r0369; CHECK-NEXT: vshr.s32 q0, q0, #1370; CHECK-NEXT: bx lr371 %add = add nsw <4 x i32> %x, %y372 %round = add <4 x i32> %add, <i32 1, i32 1, i32 1, i32 1>373 %half = ashr <4 x i32> %round, <i32 1, i32 1, i32 1, i32 1>374 ret <4 x i32> %half375}376define arm_aapcs_vfpcc <4 x i32> @vrhaddu_v4i32_nwop(<4 x i32> %x, <4 x i32> %y) {377; CHECK-LABEL: vrhaddu_v4i32_nwop:378; CHECK: @ %bb.0:379; CHECK-NEXT: vadd.i32 q0, q0, q1380; CHECK-NEXT: movs r0, #1381; CHECK-NEXT: vadd.i32 q0, q0, r0382; CHECK-NEXT: vshr.u32 q0, q0, #1383; CHECK-NEXT: bx lr384 %add = add nuw <4 x i32> %x, %y385 %round = add <4 x i32> %add, <i32 1, i32 1, i32 1, i32 1>386 %half = lshr <4 x i32> %round, <i32 1, i32 1, i32 1, i32 1>387 ret <4 x i32> %half388}389define arm_aapcs_vfpcc <16 x i8> @vrhadds_v16i8_nwrnd(<16 x i8> %x, <16 x i8> %y) {390; CHECK-LABEL: vrhadds_v16i8_nwrnd:391; CHECK: @ %bb.0:392; CHECK-NEXT: vadd.i8 q0, q0, q1393; CHECK-NEXT: movs r0, #1394; CHECK-NEXT: vhadd.s8 q0, q0, r0395; CHECK-NEXT: bx lr396 %add = add <16 x i8> %x, %y397 %round = add nsw <16 x i8> %add, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>398 %half = ashr <16 x i8> %round, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>399 ret <16 x i8> %half400}401define arm_aapcs_vfpcc <16 x i8> @vrhaddu_v16i8_nwrnd(<16 x i8> %x, <16 x i8> %y) {402; CHECK-LABEL: vrhaddu_v16i8_nwrnd:403; CHECK: @ %bb.0:404; CHECK-NEXT: vadd.i8 q0, q0, q1405; CHECK-NEXT: movs r0, #1406; CHECK-NEXT: vhadd.u8 q0, q0, r0407; CHECK-NEXT: bx lr408 %add = add <16 x i8> %x, %y409 %round = add nuw <16 x i8> %add, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>410 %half = lshr <16 x i8> %round, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>411 ret <16 x i8> %half412}413define arm_aapcs_vfpcc <8 x i16> @vrhadds_v8i16_nwrnd(<8 x i16> %x, <8 x i16> %y) {414; CHECK-LABEL: vrhadds_v8i16_nwrnd:415; CHECK: @ %bb.0:416; CHECK-NEXT: vadd.i16 q0, q0, q1417; CHECK-NEXT: movs r0, #1418; CHECK-NEXT: vhadd.s16 q0, q0, r0419; CHECK-NEXT: bx lr420 %add = add <8 x i16> %x, %y421 %round = add nsw <8 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>422 %half = ashr <8 x i16> %round, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>423 ret <8 x i16> %half424}425define arm_aapcs_vfpcc <8 x i16> @vrhaddu_v8i16_nwrnd(<8 x i16> %x, <8 x i16> %y) {426; CHECK-LABEL: vrhaddu_v8i16_nwrnd:427; CHECK: @ %bb.0:428; CHECK-NEXT: vadd.i16 q0, q0, q1429; CHECK-NEXT: movs r0, #1430; CHECK-NEXT: vhadd.u16 q0, q0, r0431; CHECK-NEXT: bx lr432 %add = add <8 x i16> %x, %y433 %round = add nuw <8 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>434 %half = lshr <8 x i16> %round, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>435 ret <8 x i16> %half436}437define arm_aapcs_vfpcc <4 x i32> @vrhadds_v4i32_nwrnd(<4 x i32> %x, <4 x i32> %y) {438; CHECK-LABEL: vrhadds_v4i32_nwrnd:439; CHECK: @ %bb.0:440; CHECK-NEXT: vadd.i32 q0, q0, q1441; CHECK-NEXT: movs r0, #1442; CHECK-NEXT: vhadd.s32 q0, q0, r0443; CHECK-NEXT: bx lr444 %add = add <4 x i32> %x, %y445 %round = add nsw <4 x i32> %add, <i32 1, i32 1, i32 1, i32 1>446 %half = ashr <4 x i32> %round, <i32 1, i32 1, i32 1, i32 1>447 ret <4 x i32> %half448}449define arm_aapcs_vfpcc <4 x i32> @vrhaddu_v4i32_nwrnd(<4 x i32> %x, <4 x i32> %y) {450; CHECK-LABEL: vrhaddu_v4i32_nwrnd:451; CHECK: @ %bb.0:452; CHECK-NEXT: vadd.i32 q0, q0, q1453; CHECK-NEXT: movs r0, #1454; CHECK-NEXT: vhadd.u32 q0, q0, r0455; CHECK-NEXT: bx lr456 %add = add <4 x i32> %x, %y457 %round = add nuw <4 x i32> %add, <i32 1, i32 1, i32 1, i32 1>458 %half = lshr <4 x i32> %round, <i32 1, i32 1, i32 1, i32 1>459 ret <4 x i32> %half460}461define arm_aapcs_vfpcc <16 x i8> @vrhadds_v16i8_both_nw(<16 x i8> %x, <16 x i8> %y) {462; CHECK-LABEL: vrhadds_v16i8_both_nw:463; CHECK: @ %bb.0:464; CHECK-NEXT: vrhadd.s8 q0, q0, q1465; CHECK-NEXT: bx lr466 %add = add nsw <16 x i8> %x, %y467 %round = add nsw <16 x i8> %add, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>468 %half = ashr <16 x i8> %round, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>469 ret <16 x i8> %half470}471define arm_aapcs_vfpcc <16 x i8> @vrhaddu_v16i8_both_nw(<16 x i8> %x, <16 x i8> %y) {472; CHECK-LABEL: vrhaddu_v16i8_both_nw:473; CHECK: @ %bb.0:474; CHECK-NEXT: vrhadd.u8 q0, q0, q1475; CHECK-NEXT: bx lr476 %add = add nuw <16 x i8> %x, %y477 %round = add nuw <16 x i8> %add, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>478 %half = lshr <16 x i8> %round, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>479 ret <16 x i8> %half480}481define arm_aapcs_vfpcc <8 x i16> @vrhadds_v8i16_both_nw(<8 x i16> %x, <8 x i16> %y) {482; CHECK-LABEL: vrhadds_v8i16_both_nw:483; CHECK: @ %bb.0:484; CHECK-NEXT: vrhadd.s16 q0, q0, q1485; CHECK-NEXT: bx lr486 %add = add nsw <8 x i16> %x, %y487 %round = add nsw <8 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>488 %half = ashr <8 x i16> %round, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>489 ret <8 x i16> %half490}491define arm_aapcs_vfpcc <8 x i16> @vrhaddu_v8i16_both_nw(<8 x i16> %x, <8 x i16> %y) {492; CHECK-LABEL: vrhaddu_v8i16_both_nw:493; CHECK: @ %bb.0:494; CHECK-NEXT: vrhadd.u16 q0, q0, q1495; CHECK-NEXT: bx lr496 %add = add nuw <8 x i16> %x, %y497 %round = add nuw <8 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>498 %half = lshr <8 x i16> %round, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>499 ret <8 x i16> %half500}501define arm_aapcs_vfpcc <4 x i32> @vrhadds_v4i32_both_nw(<4 x i32> %x, <4 x i32> %y) {502; CHECK-LABEL: vrhadds_v4i32_both_nw:503; CHECK: @ %bb.0:504; CHECK-NEXT: vrhadd.s32 q0, q0, q1505; CHECK-NEXT: bx lr506 %add = add nsw <4 x i32> %x, %y507 %round = add nsw <4 x i32> %add, <i32 1, i32 1, i32 1, i32 1>508 %half = ashr <4 x i32> %round, <i32 1, i32 1, i32 1, i32 1>509 ret <4 x i32> %half510}511define arm_aapcs_vfpcc <4 x i32> @vrhaddu_v4i32_both_nw(<4 x i32> %x, <4 x i32> %y) {512; CHECK-LABEL: vrhaddu_v4i32_both_nw:513; CHECK: @ %bb.0:514; CHECK-NEXT: vrhadd.u32 q0, q0, q1515; CHECK-NEXT: bx lr516 %add = add nuw <4 x i32> %x, %y517 %round = add nuw <4 x i32> %add, <i32 1, i32 1, i32 1, i32 1>518 %half = lshr <4 x i32> %round, <i32 1, i32 1, i32 1, i32 1>519 ret <4 x i32> %half520}521