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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s3; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s4 5define arm_aapcs_vfpcc <16 x i8> @test_vmvnq_m_s8(<16 x i8> %inactive, <16 x i8> %a, i16 zeroext %p) {6; CHECK-LABEL: test_vmvnq_m_s8:7; CHECK: @ %bb.0: @ %entry8; CHECK-NEXT: vmsr p0, r09; CHECK-NEXT: vpst10; CHECK-NEXT: vmvnt q0, q111; CHECK-NEXT: bx lr12entry:13 %0 = zext i16 %p to i3214 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)15 %2 = tail call <16 x i8> @llvm.arm.mve.mvn.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i1> %1, <16 x i8> %inactive)16 ret <16 x i8> %217}18 19define arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_s16(<8 x i16> %inactive, <8 x i16> %a, i16 zeroext %p) {20; CHECK-LABEL: test_vmvnq_m_s16:21; CHECK: @ %bb.0: @ %entry22; CHECK-NEXT: vmsr p0, r023; CHECK-NEXT: vpst24; CHECK-NEXT: vmvnt q0, q125; CHECK-NEXT: bx lr26entry:27 %0 = zext i16 %p to i3228 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)29 %2 = tail call <8 x i16> @llvm.arm.mve.mvn.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i1> %1, <8 x i16> %inactive)30 ret <8 x i16> %231}32 33define arm_aapcs_vfpcc <4 x i32> @test_vmvnq_m_s32(<4 x i32> %inactive, <4 x i32> %a, i16 zeroext %p) {34; CHECK-LABEL: test_vmvnq_m_s32:35; CHECK: @ %bb.0: @ %entry36; CHECK-NEXT: vmsr p0, r037; CHECK-NEXT: vpst38; CHECK-NEXT: vmvnt q0, q139; CHECK-NEXT: bx lr40entry:41 %0 = zext i16 %p to i3242 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)43 %2 = tail call <4 x i32> @llvm.arm.mve.mvn.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i1> %1, <4 x i32> %inactive)44 ret <4 x i32> %245}46 47define arm_aapcs_vfpcc <16 x i8> @test_vmvnq_m_u8(<16 x i8> %inactive, <16 x i8> %a, i16 zeroext %p) {48; CHECK-LABEL: test_vmvnq_m_u8:49; CHECK: @ %bb.0: @ %entry50; CHECK-NEXT: vmsr p0, r051; CHECK-NEXT: vpst52; CHECK-NEXT: vmvnt q0, q153; CHECK-NEXT: bx lr54entry:55 %0 = zext i16 %p to i3256 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)57 %2 = tail call <16 x i8> @llvm.arm.mve.mvn.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i1> %1, <16 x i8> %inactive)58 ret <16 x i8> %259}60 61define arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_u16(<8 x i16> %inactive, <8 x i16> %a, i16 zeroext %p) {62; CHECK-LABEL: test_vmvnq_m_u16:63; CHECK: @ %bb.0: @ %entry64; CHECK-NEXT: vmsr p0, r065; CHECK-NEXT: vpst66; CHECK-NEXT: vmvnt q0, q167; CHECK-NEXT: bx lr68entry:69 %0 = zext i16 %p to i3270 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)71 %2 = tail call <8 x i16> @llvm.arm.mve.mvn.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i1> %1, <8 x i16> %inactive)72 ret <8 x i16> %273}74 75define arm_aapcs_vfpcc <4 x i32> @test_vmvnq_m_u32(<4 x i32> %inactive, <4 x i32> %a, i16 zeroext %p) {76; CHECK-LABEL: test_vmvnq_m_u32:77; CHECK: @ %bb.0: @ %entry78; CHECK-NEXT: vmsr p0, r079; CHECK-NEXT: vpst80; CHECK-NEXT: vmvnt q0, q181; CHECK-NEXT: bx lr82entry:83 %0 = zext i16 %p to i3284 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)85 %2 = tail call <4 x i32> @llvm.arm.mve.mvn.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i1> %1, <4 x i32> %inactive)86 ret <4 x i32> %287}88 89define arm_aapcs_vfpcc <8 x half> @test_vnegq_m_f16(<8 x half> %inactive, <8 x half> %a, i16 zeroext %p) {90; CHECK-LABEL: test_vnegq_m_f16:91; CHECK: @ %bb.0: @ %entry92; CHECK-NEXT: vmsr p0, r093; CHECK-NEXT: vpst94; CHECK-NEXT: vnegt.f16 q0, q195; CHECK-NEXT: bx lr96entry:97 %0 = zext i16 %p to i3298 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)99 %2 = tail call <8 x half> @llvm.arm.mve.neg.predicated.v8f16.v8i1(<8 x half> %a, <8 x i1> %1, <8 x half> %inactive)100 ret <8 x half> %2101}102 103define arm_aapcs_vfpcc <4 x float> @test_vnegq_m_f32(<4 x float> %inactive, <4 x float> %a, i16 zeroext %p) {104; CHECK-LABEL: test_vnegq_m_f32:105; CHECK: @ %bb.0: @ %entry106; CHECK-NEXT: vmsr p0, r0107; CHECK-NEXT: vpst108; CHECK-NEXT: vnegt.f32 q0, q1109; CHECK-NEXT: bx lr110entry:111 %0 = zext i16 %p to i32112 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)113 %2 = tail call <4 x float> @llvm.arm.mve.neg.predicated.v4f32.v4i1(<4 x float> %a, <4 x i1> %1, <4 x float> %inactive)114 ret <4 x float> %2115}116 117define arm_aapcs_vfpcc <16 x i8> @test_vnegq_m_s8(<16 x i8> %inactive, <16 x i8> %a, i16 zeroext %p) {118; CHECK-LABEL: test_vnegq_m_s8:119; CHECK: @ %bb.0: @ %entry120; CHECK-NEXT: vmsr p0, r0121; CHECK-NEXT: vpst122; CHECK-NEXT: vnegt.s8 q0, q1123; CHECK-NEXT: bx lr124entry:125 %0 = zext i16 %p to i32126 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)127 %2 = tail call <16 x i8> @llvm.arm.mve.neg.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i1> %1, <16 x i8> %inactive)128 ret <16 x i8> %2129}130 131define arm_aapcs_vfpcc <8 x i16> @test_vnegq_m_s16(<8 x i16> %inactive, <8 x i16> %a, i16 zeroext %p) {132; CHECK-LABEL: test_vnegq_m_s16:133; CHECK: @ %bb.0: @ %entry134; CHECK-NEXT: vmsr p0, r0135; CHECK-NEXT: vpst136; CHECK-NEXT: vnegt.s16 q0, q1137; CHECK-NEXT: bx lr138entry:139 %0 = zext i16 %p to i32140 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)141 %2 = tail call <8 x i16> @llvm.arm.mve.neg.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i1> %1, <8 x i16> %inactive)142 ret <8 x i16> %2143}144 145define arm_aapcs_vfpcc <4 x i32> @test_vnegq_m_s32(<4 x i32> %inactive, <4 x i32> %a, i16 zeroext %p) {146; CHECK-LABEL: test_vnegq_m_s32:147; CHECK: @ %bb.0: @ %entry148; CHECK-NEXT: vmsr p0, r0149; CHECK-NEXT: vpst150; CHECK-NEXT: vnegt.s32 q0, q1151; CHECK-NEXT: bx lr152entry:153 %0 = zext i16 %p to i32154 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)155 %2 = tail call <4 x i32> @llvm.arm.mve.neg.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i1> %1, <4 x i32> %inactive)156 ret <4 x i32> %2157}158 159define arm_aapcs_vfpcc <8 x half> @test_vabsq_m_f16(<8 x half> %inactive, <8 x half> %a, i16 zeroext %p) {160; CHECK-LABEL: test_vabsq_m_f16:161; CHECK: @ %bb.0: @ %entry162; CHECK-NEXT: vmsr p0, r0163; CHECK-NEXT: vpst164; CHECK-NEXT: vabst.f16 q0, q1165; CHECK-NEXT: bx lr166entry:167 %0 = zext i16 %p to i32168 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)169 %2 = tail call <8 x half> @llvm.arm.mve.abs.predicated.v8f16.v8i1(<8 x half> %a, <8 x i1> %1, <8 x half> %inactive)170 ret <8 x half> %2171}172 173define arm_aapcs_vfpcc <4 x float> @test_vabsq_m_f32(<4 x float> %inactive, <4 x float> %a, i16 zeroext %p) {174; CHECK-LABEL: test_vabsq_m_f32:175; CHECK: @ %bb.0: @ %entry176; CHECK-NEXT: vmsr p0, r0177; CHECK-NEXT: vpst178; CHECK-NEXT: vabst.f32 q0, q1179; CHECK-NEXT: bx lr180entry:181 %0 = zext i16 %p to i32182 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)183 %2 = tail call <4 x float> @llvm.arm.mve.abs.predicated.v4f32.v4i1(<4 x float> %a, <4 x i1> %1, <4 x float> %inactive)184 ret <4 x float> %2185}186 187define arm_aapcs_vfpcc <16 x i8> @test_vabsq_m_s8(<16 x i8> %inactive, <16 x i8> %a, i16 zeroext %p) {188; CHECK-LABEL: test_vabsq_m_s8:189; CHECK: @ %bb.0: @ %entry190; CHECK-NEXT: vmsr p0, r0191; CHECK-NEXT: vpst192; CHECK-NEXT: vabst.s8 q0, q1193; CHECK-NEXT: bx lr194entry:195 %0 = zext i16 %p to i32196 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)197 %2 = tail call <16 x i8> @llvm.arm.mve.abs.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i1> %1, <16 x i8> %inactive)198 ret <16 x i8> %2199}200 201define arm_aapcs_vfpcc <8 x i16> @test_vabsq_m_s16(<8 x i16> %inactive, <8 x i16> %a, i16 zeroext %p) {202; CHECK-LABEL: test_vabsq_m_s16:203; CHECK: @ %bb.0: @ %entry204; CHECK-NEXT: vmsr p0, r0205; CHECK-NEXT: vpst206; CHECK-NEXT: vabst.s16 q0, q1207; CHECK-NEXT: bx lr208entry:209 %0 = zext i16 %p to i32210 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)211 %2 = tail call <8 x i16> @llvm.arm.mve.abs.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i1> %1, <8 x i16> %inactive)212 ret <8 x i16> %2213}214 215define arm_aapcs_vfpcc <4 x i32> @test_vabsq_m_s32(<4 x i32> %inactive, <4 x i32> %a, i16 zeroext %p) {216; CHECK-LABEL: test_vabsq_m_s32:217; CHECK: @ %bb.0: @ %entry218; CHECK-NEXT: vmsr p0, r0219; CHECK-NEXT: vpst220; CHECK-NEXT: vabst.s32 q0, q1221; CHECK-NEXT: bx lr222entry:223 %0 = zext i16 %p to i32224 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)225 %2 = tail call <4 x i32> @llvm.arm.mve.abs.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i1> %1, <4 x i32> %inactive)226 ret <4 x i32> %2227}228 229define arm_aapcs_vfpcc <16 x i8> @test_vqnegq_m_s8(<16 x i8> %inactive, <16 x i8> %a, i16 zeroext %p) {230; CHECK-LABEL: test_vqnegq_m_s8:231; CHECK: @ %bb.0: @ %entry232; CHECK-NEXT: vmsr p0, r0233; CHECK-NEXT: vpst234; CHECK-NEXT: vqnegt.s8 q0, q1235; CHECK-NEXT: bx lr236entry:237 %0 = zext i16 %p to i32238 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)239 %2 = tail call <16 x i8> @llvm.arm.mve.qneg.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i1> %1, <16 x i8> %inactive)240 ret <16 x i8> %2241}242 243define arm_aapcs_vfpcc <8 x i16> @test_vqnegq_m_s16(<8 x i16> %inactive, <8 x i16> %a, i16 zeroext %p) {244; CHECK-LABEL: test_vqnegq_m_s16:245; CHECK: @ %bb.0: @ %entry246; CHECK-NEXT: vmsr p0, r0247; CHECK-NEXT: vpst248; CHECK-NEXT: vqnegt.s16 q0, q1249; CHECK-NEXT: bx lr250entry:251 %0 = zext i16 %p to i32252 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)253 %2 = tail call <8 x i16> @llvm.arm.mve.qneg.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i1> %1, <8 x i16> %inactive)254 ret <8 x i16> %2255}256 257define arm_aapcs_vfpcc <4 x i32> @test_vqnegq_m_s32(<4 x i32> %inactive, <4 x i32> %a, i16 zeroext %p) {258; CHECK-LABEL: test_vqnegq_m_s32:259; CHECK: @ %bb.0: @ %entry260; CHECK-NEXT: vmsr p0, r0261; CHECK-NEXT: vpst262; CHECK-NEXT: vqnegt.s32 q0, q1263; CHECK-NEXT: bx lr264entry:265 %0 = zext i16 %p to i32266 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)267 %2 = tail call <4 x i32> @llvm.arm.mve.qneg.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i1> %1, <4 x i32> %inactive)268 ret <4 x i32> %2269}270 271define arm_aapcs_vfpcc <16 x i8> @test_vqabsq_m_s8(<16 x i8> %inactive, <16 x i8> %a, i16 zeroext %p) {272; CHECK-LABEL: test_vqabsq_m_s8:273; CHECK: @ %bb.0: @ %entry274; CHECK-NEXT: vmsr p0, r0275; CHECK-NEXT: vpst276; CHECK-NEXT: vqabst.s8 q0, q1277; CHECK-NEXT: bx lr278entry:279 %0 = zext i16 %p to i32280 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)281 %2 = tail call <16 x i8> @llvm.arm.mve.qabs.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i1> %1, <16 x i8> %inactive)282 ret <16 x i8> %2283}284 285define arm_aapcs_vfpcc <8 x i16> @test_vqabsq_m_s16(<8 x i16> %inactive, <8 x i16> %a, i16 zeroext %p) {286; CHECK-LABEL: test_vqabsq_m_s16:287; CHECK: @ %bb.0: @ %entry288; CHECK-NEXT: vmsr p0, r0289; CHECK-NEXT: vpst290; CHECK-NEXT: vqabst.s16 q0, q1291; CHECK-NEXT: bx lr292entry:293 %0 = zext i16 %p to i32294 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)295 %2 = tail call <8 x i16> @llvm.arm.mve.qabs.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i1> %1, <8 x i16> %inactive)296 ret <8 x i16> %2297}298 299define arm_aapcs_vfpcc <4 x i32> @test_vqabsq_m_s32(<4 x i32> %inactive, <4 x i32> %a, i16 zeroext %p) {300; CHECK-LABEL: test_vqabsq_m_s32:301; CHECK: @ %bb.0: @ %entry302; CHECK-NEXT: vmsr p0, r0303; CHECK-NEXT: vpst304; CHECK-NEXT: vqabst.s32 q0, q1305; CHECK-NEXT: bx lr306entry:307 %0 = zext i16 %p to i32308 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)309 %2 = tail call <4 x i32> @llvm.arm.mve.qabs.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i1> %1, <4 x i32> %inactive)310 ret <4 x i32> %2311}312 313declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)314declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)315declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)316 317declare <16 x i8> @llvm.arm.mve.mvn.predicated.v16i8.v16i1(<16 x i8>, <16 x i1>, <16 x i8>)318declare <8 x i16> @llvm.arm.mve.mvn.predicated.v8i16.v8i1(<8 x i16>, <8 x i1>, <8 x i16>)319declare <4 x i32> @llvm.arm.mve.mvn.predicated.v4i32.v4i1(<4 x i32>, <4 x i1>, <4 x i32>)320declare <8 x half> @llvm.arm.mve.neg.predicated.v8f16.v8i1(<8 x half>, <8 x i1>, <8 x half>)321declare <4 x float> @llvm.arm.mve.neg.predicated.v4f32.v4i1(<4 x float>, <4 x i1>, <4 x float>)322declare <16 x i8> @llvm.arm.mve.neg.predicated.v16i8.v16i1(<16 x i8>, <16 x i1>, <16 x i8>)323declare <8 x i16> @llvm.arm.mve.neg.predicated.v8i16.v8i1(<8 x i16>, <8 x i1>, <8 x i16>)324declare <4 x i32> @llvm.arm.mve.neg.predicated.v4i32.v4i1(<4 x i32>, <4 x i1>, <4 x i32>)325declare <8 x half> @llvm.arm.mve.abs.predicated.v8f16.v8i1(<8 x half>, <8 x i1>, <8 x half>)326declare <4 x float> @llvm.arm.mve.abs.predicated.v4f32.v4i1(<4 x float>, <4 x i1>, <4 x float>)327declare <16 x i8> @llvm.arm.mve.abs.predicated.v16i8.v16i1(<16 x i8>, <16 x i1>, <16 x i8>)328declare <8 x i16> @llvm.arm.mve.abs.predicated.v8i16.v8i1(<8 x i16>, <8 x i1>, <8 x i16>)329declare <4 x i32> @llvm.arm.mve.abs.predicated.v4i32.v4i1(<4 x i32>, <4 x i1>, <4 x i32>)330declare <16 x i8> @llvm.arm.mve.qneg.predicated.v16i8.v16i1(<16 x i8>, <16 x i1>, <16 x i8>)331declare <8 x i16> @llvm.arm.mve.qneg.predicated.v8i16.v8i1(<8 x i16>, <8 x i1>, <8 x i16>)332declare <4 x i32> @llvm.arm.mve.qneg.predicated.v4i32.v4i1(<4 x i32>, <4 x i1>, <4 x i32>)333declare <16 x i8> @llvm.arm.mve.qabs.predicated.v16i8.v16i1(<16 x i8>, <16 x i1>, <16 x i8>)334declare <8 x i16> @llvm.arm.mve.qabs.predicated.v8i16.v8i1(<8 x i16>, <8 x i1>, <8 x i16>)335declare <4 x i32> @llvm.arm.mve.qabs.predicated.v4i32.v4i1(<4 x i32>, <4 x i1>, <4 x i32>)336