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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -verify-machineinstrs -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-LE3; RUN: llc -mtriple=thumbebv8.1m.main -mattr=+mve -verify-machineinstrs -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-BE4 5define arm_aapcs_vfpcc <8 x i16> @test_vbicq_n_u16_sh0(<8 x i16> %a) {6; CHECK-LE-LABEL: test_vbicq_n_u16_sh0:7; CHECK-LE: @ %bb.0: @ %entry8; CHECK-LE-NEXT: vbic.i16 q0, #0x649; CHECK-LE-NEXT: bx lr10;11; CHECK-BE-LABEL: test_vbicq_n_u16_sh0:12; CHECK-BE: @ %bb.0: @ %entry13; CHECK-BE-NEXT: vrev64.16 q1, q014; CHECK-BE-NEXT: vbic.i16 q1, #0x6415; CHECK-BE-NEXT: vrev64.16 q0, q116; CHECK-BE-NEXT: bx lr17entry:18 %0 = and <8 x i16> %a, <i16 -101, i16 -101, i16 -101, i16 -101, i16 -101, i16 -101, i16 -101, i16 -101>19 ret <8 x i16> %020}21 22define arm_aapcs_vfpcc <8 x i16> @test_vbicq_n_u16_sh8(<8 x i16> %a) {23; CHECK-LE-LABEL: test_vbicq_n_u16_sh8:24; CHECK-LE: @ %bb.0: @ %entry25; CHECK-LE-NEXT: vbic.i16 q0, #0x640026; CHECK-LE-NEXT: bx lr27;28; CHECK-BE-LABEL: test_vbicq_n_u16_sh8:29; CHECK-BE: @ %bb.0: @ %entry30; CHECK-BE-NEXT: vrev64.16 q1, q031; CHECK-BE-NEXT: vbic.i16 q1, #0x640032; CHECK-BE-NEXT: vrev64.16 q0, q133; CHECK-BE-NEXT: bx lr34entry:35 %0 = and <8 x i16> %a, <i16 -25601, i16 -25601, i16 -25601, i16 -25601, i16 -25601, i16 -25601, i16 -25601, i16 -25601>36 ret <8 x i16> %037}38 39define arm_aapcs_vfpcc <4 x i32> @test_vbicq_n_u32_sh0(<4 x i32> %a) {40; CHECK-LE-LABEL: test_vbicq_n_u32_sh0:41; CHECK-LE: @ %bb.0: @ %entry42; CHECK-LE-NEXT: vbic.i32 q0, #0x6443; CHECK-LE-NEXT: bx lr44;45; CHECK-BE-LABEL: test_vbicq_n_u32_sh0:46; CHECK-BE: @ %bb.0: @ %entry47; CHECK-BE-NEXT: vrev64.32 q1, q048; CHECK-BE-NEXT: vbic.i32 q1, #0x6449; CHECK-BE-NEXT: vrev64.32 q0, q150; CHECK-BE-NEXT: bx lr51entry:52 %0 = and <4 x i32> %a, <i32 -101, i32 -101, i32 -101, i32 -101>53 ret <4 x i32> %054}55 56define arm_aapcs_vfpcc <4 x i32> @test_vbicq_n_u32_sh8(<4 x i32> %a) {57; CHECK-LE-LABEL: test_vbicq_n_u32_sh8:58; CHECK-LE: @ %bb.0: @ %entry59; CHECK-LE-NEXT: vbic.i32 q0, #0x640060; CHECK-LE-NEXT: bx lr61;62; CHECK-BE-LABEL: test_vbicq_n_u32_sh8:63; CHECK-BE: @ %bb.0: @ %entry64; CHECK-BE-NEXT: vrev64.32 q1, q065; CHECK-BE-NEXT: vbic.i32 q1, #0x640066; CHECK-BE-NEXT: vrev64.32 q0, q167; CHECK-BE-NEXT: bx lr68entry:69 %0 = and <4 x i32> %a, <i32 -25601, i32 -25601, i32 -25601, i32 -25601>70 ret <4 x i32> %071}72 73define arm_aapcs_vfpcc <4 x i32> @test_vbicq_n_u32_sh16(<4 x i32> %a) {74; CHECK-LE-LABEL: test_vbicq_n_u32_sh16:75; CHECK-LE: @ %bb.0: @ %entry76; CHECK-LE-NEXT: vbic.i32 q0, #0x64000077; CHECK-LE-NEXT: bx lr78;79; CHECK-BE-LABEL: test_vbicq_n_u32_sh16:80; CHECK-BE: @ %bb.0: @ %entry81; CHECK-BE-NEXT: vrev64.32 q1, q082; CHECK-BE-NEXT: vbic.i32 q1, #0x64000083; CHECK-BE-NEXT: vrev64.32 q0, q184; CHECK-BE-NEXT: bx lr85entry:86 %0 = and <4 x i32> %a, <i32 -6553601, i32 -6553601, i32 -6553601, i32 -6553601>87 ret <4 x i32> %088}89 90define arm_aapcs_vfpcc <4 x i32> @test_vbicq_n_u32_sh24(<4 x i32> %a) {91; CHECK-LE-LABEL: test_vbicq_n_u32_sh24:92; CHECK-LE: @ %bb.0: @ %entry93; CHECK-LE-NEXT: vbic.i32 q0, #0x6400000094; CHECK-LE-NEXT: bx lr95;96; CHECK-BE-LABEL: test_vbicq_n_u32_sh24:97; CHECK-BE: @ %bb.0: @ %entry98; CHECK-BE-NEXT: vrev64.32 q1, q099; CHECK-BE-NEXT: vbic.i32 q1, #0x64000000100; CHECK-BE-NEXT: vrev64.32 q0, q1101; CHECK-BE-NEXT: bx lr102entry:103 %0 = and <4 x i32> %a, <i32 -1677721601, i32 -1677721601, i32 -1677721601, i32 -1677721601>104 ret <4 x i32> %0105}106 107; The immediate in this case is legal for a VMVN but not for a VBIC,108; so in this case we expect to see the constant being prepared in109; another register.110define arm_aapcs_vfpcc <4 x i32> @test_vbicq_n_u32_illegal(<4 x i32> %a) {111; CHECK-LE-LABEL: test_vbicq_n_u32_illegal:112; CHECK-LE: @ %bb.0: @ %entry113; CHECK-LE-NEXT: vmvn.i32 q1, #0x54ff114; CHECK-LE-NEXT: vand q0, q0, q1115; CHECK-LE-NEXT: bx lr116;117; CHECK-BE-LABEL: test_vbicq_n_u32_illegal:118; CHECK-BE: @ %bb.0: @ %entry119; CHECK-BE-NEXT: vrev64.32 q1, q0120; CHECK-BE-NEXT: vmvn.i32 q0, #0x54ff121; CHECK-BE-NEXT: vand q1, q1, q0122; CHECK-BE-NEXT: vrev64.32 q0, q1123; CHECK-BE-NEXT: bx lr124entry:125 %0 = and <4 x i32> %a, <i32 -21760, i32 -21760, i32 -21760, i32 -21760>126 ret <4 x i32> %0127}128 129define arm_aapcs_vfpcc <8 x i16> @test_vorrq_n_u16_sh0(<8 x i16> %a) {130; CHECK-LE-LABEL: test_vorrq_n_u16_sh0:131; CHECK-LE: @ %bb.0: @ %entry132; CHECK-LE-NEXT: vorr.i16 q0, #0x64133; CHECK-LE-NEXT: bx lr134;135; CHECK-BE-LABEL: test_vorrq_n_u16_sh0:136; CHECK-BE: @ %bb.0: @ %entry137; CHECK-BE-NEXT: vrev64.16 q1, q0138; CHECK-BE-NEXT: vorr.i16 q1, #0x64139; CHECK-BE-NEXT: vrev64.16 q0, q1140; CHECK-BE-NEXT: bx lr141entry:142 %0 = or <8 x i16> %a, <i16 100, i16 100, i16 100, i16 100, i16 100, i16 100, i16 100, i16 100>143 ret <8 x i16> %0144}145 146define arm_aapcs_vfpcc <8 x i16> @test_vorrq_n_u16_sh8(<8 x i16> %a) {147; CHECK-LE-LABEL: test_vorrq_n_u16_sh8:148; CHECK-LE: @ %bb.0: @ %entry149; CHECK-LE-NEXT: vorr.i16 q0, #0x6400150; CHECK-LE-NEXT: bx lr151;152; CHECK-BE-LABEL: test_vorrq_n_u16_sh8:153; CHECK-BE: @ %bb.0: @ %entry154; CHECK-BE-NEXT: vrev64.16 q1, q0155; CHECK-BE-NEXT: vorr.i16 q1, #0x6400156; CHECK-BE-NEXT: vrev64.16 q0, q1157; CHECK-BE-NEXT: bx lr158entry:159 %0 = or <8 x i16> %a, <i16 25600, i16 25600, i16 25600, i16 25600, i16 25600, i16 25600, i16 25600, i16 25600>160 ret <8 x i16> %0161}162 163define arm_aapcs_vfpcc <4 x i32> @test_vorrq_n_u32_sh0(<4 x i32> %a) {164; CHECK-LE-LABEL: test_vorrq_n_u32_sh0:165; CHECK-LE: @ %bb.0: @ %entry166; CHECK-LE-NEXT: vorr.i32 q0, #0x64167; CHECK-LE-NEXT: bx lr168;169; CHECK-BE-LABEL: test_vorrq_n_u32_sh0:170; CHECK-BE: @ %bb.0: @ %entry171; CHECK-BE-NEXT: vrev64.32 q1, q0172; CHECK-BE-NEXT: vorr.i32 q1, #0x64173; CHECK-BE-NEXT: vrev64.32 q0, q1174; CHECK-BE-NEXT: bx lr175entry:176 %0 = or <4 x i32> %a, <i32 100, i32 100, i32 100, i32 100>177 ret <4 x i32> %0178}179 180define arm_aapcs_vfpcc <4 x i32> @test_vorrq_n_u32_sh8(<4 x i32> %a) {181; CHECK-LE-LABEL: test_vorrq_n_u32_sh8:182; CHECK-LE: @ %bb.0: @ %entry183; CHECK-LE-NEXT: vorr.i32 q0, #0x6400184; CHECK-LE-NEXT: bx lr185;186; CHECK-BE-LABEL: test_vorrq_n_u32_sh8:187; CHECK-BE: @ %bb.0: @ %entry188; CHECK-BE-NEXT: vrev64.32 q1, q0189; CHECK-BE-NEXT: vorr.i32 q1, #0x6400190; CHECK-BE-NEXT: vrev64.32 q0, q1191; CHECK-BE-NEXT: bx lr192entry:193 %0 = or <4 x i32> %a, <i32 25600, i32 25600, i32 25600, i32 25600>194 ret <4 x i32> %0195}196 197define arm_aapcs_vfpcc <4 x i32> @test_vorrq_n_u32_sh16(<4 x i32> %a) {198; CHECK-LE-LABEL: test_vorrq_n_u32_sh16:199; CHECK-LE: @ %bb.0: @ %entry200; CHECK-LE-NEXT: vorr.i32 q0, #0x640000201; CHECK-LE-NEXT: bx lr202;203; CHECK-BE-LABEL: test_vorrq_n_u32_sh16:204; CHECK-BE: @ %bb.0: @ %entry205; CHECK-BE-NEXT: vrev64.32 q1, q0206; CHECK-BE-NEXT: vorr.i32 q1, #0x640000207; CHECK-BE-NEXT: vrev64.32 q0, q1208; CHECK-BE-NEXT: bx lr209entry:210 %0 = or <4 x i32> %a, <i32 6553600, i32 6553600, i32 6553600, i32 6553600>211 ret <4 x i32> %0212}213 214define arm_aapcs_vfpcc <4 x i32> @test_vorrq_n_u32_sh24(<4 x i32> %a) {215; CHECK-LE-LABEL: test_vorrq_n_u32_sh24:216; CHECK-LE: @ %bb.0: @ %entry217; CHECK-LE-NEXT: vorr.i32 q0, #0x64000000218; CHECK-LE-NEXT: bx lr219;220; CHECK-BE-LABEL: test_vorrq_n_u32_sh24:221; CHECK-BE: @ %bb.0: @ %entry222; CHECK-BE-NEXT: vrev64.32 q1, q0223; CHECK-BE-NEXT: vorr.i32 q1, #0x64000000224; CHECK-BE-NEXT: vrev64.32 q0, q1225; CHECK-BE-NEXT: bx lr226entry:227 %0 = or <4 x i32> %a, <i32 1677721600, i32 1677721600, i32 1677721600, i32 1677721600>228 ret <4 x i32> %0229}230 231define arm_aapcs_vfpcc <8 x i16> @test_vbicq_m_n_u16_sh0(<8 x i16> %a, i16 zeroext %p) {232; CHECK-LE-LABEL: test_vbicq_m_n_u16_sh0:233; CHECK-LE: @ %bb.0: @ %entry234; CHECK-LE-NEXT: vmsr p0, r0235; CHECK-LE-NEXT: vpst236; CHECK-LE-NEXT: vbict.i16 q0, #0x64237; CHECK-LE-NEXT: bx lr238;239; CHECK-BE-LABEL: test_vbicq_m_n_u16_sh0:240; CHECK-BE: @ %bb.0: @ %entry241; CHECK-BE-NEXT: vrev64.16 q1, q0242; CHECK-BE-NEXT: vmsr p0, r0243; CHECK-BE-NEXT: vpst244; CHECK-BE-NEXT: vbict.i16 q1, #0x64245; CHECK-BE-NEXT: vrev64.16 q0, q1246; CHECK-BE-NEXT: bx lr247entry:248 %0 = zext i16 %p to i32249 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)250 %2 = and <8 x i16> %a, <i16 -101, i16 -101, i16 -101, i16 -101, i16 -101, i16 -101, i16 -101, i16 -101>251 %3 = select <8 x i1> %1, <8 x i16> %2, <8 x i16> %a252 ret <8 x i16> %3253}254 255define arm_aapcs_vfpcc <8 x i16> @test_vbicq_m_n_u16_sh8(<8 x i16> %a, i16 zeroext %p) {256; CHECK-LE-LABEL: test_vbicq_m_n_u16_sh8:257; CHECK-LE: @ %bb.0: @ %entry258; CHECK-LE-NEXT: vmsr p0, r0259; CHECK-LE-NEXT: vpst260; CHECK-LE-NEXT: vbict.i16 q0, #0x6400261; CHECK-LE-NEXT: bx lr262;263; CHECK-BE-LABEL: test_vbicq_m_n_u16_sh8:264; CHECK-BE: @ %bb.0: @ %entry265; CHECK-BE-NEXT: vrev64.16 q1, q0266; CHECK-BE-NEXT: vmsr p0, r0267; CHECK-BE-NEXT: vpst268; CHECK-BE-NEXT: vbict.i16 q1, #0x6400269; CHECK-BE-NEXT: vrev64.16 q0, q1270; CHECK-BE-NEXT: bx lr271entry:272 %0 = zext i16 %p to i32273 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)274 %2 = and <8 x i16> %a, <i16 -25601, i16 -25601, i16 -25601, i16 -25601, i16 -25601, i16 -25601, i16 -25601, i16 -25601>275 %3 = select <8 x i1> %1, <8 x i16> %2, <8 x i16> %a276 ret <8 x i16> %3277}278 279define arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_n_u32_sh0(<4 x i32> %a, i16 zeroext %p) {280; CHECK-LE-LABEL: test_vbicq_m_n_u32_sh0:281; CHECK-LE: @ %bb.0: @ %entry282; CHECK-LE-NEXT: vmsr p0, r0283; CHECK-LE-NEXT: vpst284; CHECK-LE-NEXT: vbict.i32 q0, #0x64285; CHECK-LE-NEXT: bx lr286;287; CHECK-BE-LABEL: test_vbicq_m_n_u32_sh0:288; CHECK-BE: @ %bb.0: @ %entry289; CHECK-BE-NEXT: vrev64.32 q1, q0290; CHECK-BE-NEXT: vmsr p0, r0291; CHECK-BE-NEXT: vpst292; CHECK-BE-NEXT: vbict.i32 q1, #0x64293; CHECK-BE-NEXT: vrev64.32 q0, q1294; CHECK-BE-NEXT: bx lr295entry:296 %0 = zext i16 %p to i32297 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)298 %2 = and <4 x i32> %a, <i32 -101, i32 -101, i32 -101, i32 -101>299 %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %a300 ret <4 x i32> %3301}302 303define arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_n_u32_sh8(<4 x i32> %a, i16 zeroext %p) {304; CHECK-LE-LABEL: test_vbicq_m_n_u32_sh8:305; CHECK-LE: @ %bb.0: @ %entry306; CHECK-LE-NEXT: vmsr p0, r0307; CHECK-LE-NEXT: vpst308; CHECK-LE-NEXT: vbict.i32 q0, #0x6400309; CHECK-LE-NEXT: bx lr310;311; CHECK-BE-LABEL: test_vbicq_m_n_u32_sh8:312; CHECK-BE: @ %bb.0: @ %entry313; CHECK-BE-NEXT: vrev64.32 q1, q0314; CHECK-BE-NEXT: vmsr p0, r0315; CHECK-BE-NEXT: vpst316; CHECK-BE-NEXT: vbict.i32 q1, #0x6400317; CHECK-BE-NEXT: vrev64.32 q0, q1318; CHECK-BE-NEXT: bx lr319entry:320 %0 = zext i16 %p to i32321 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)322 %2 = and <4 x i32> %a, <i32 -25601, i32 -25601, i32 -25601, i32 -25601>323 %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %a324 ret <4 x i32> %3325}326 327define arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_n_u32_sh16(<4 x i32> %a, i16 zeroext %p) {328; CHECK-LE-LABEL: test_vbicq_m_n_u32_sh16:329; CHECK-LE: @ %bb.0: @ %entry330; CHECK-LE-NEXT: vmsr p0, r0331; CHECK-LE-NEXT: vpst332; CHECK-LE-NEXT: vbict.i32 q0, #0x640000333; CHECK-LE-NEXT: bx lr334;335; CHECK-BE-LABEL: test_vbicq_m_n_u32_sh16:336; CHECK-BE: @ %bb.0: @ %entry337; CHECK-BE-NEXT: vrev64.32 q1, q0338; CHECK-BE-NEXT: vmsr p0, r0339; CHECK-BE-NEXT: vpst340; CHECK-BE-NEXT: vbict.i32 q1, #0x640000341; CHECK-BE-NEXT: vrev64.32 q0, q1342; CHECK-BE-NEXT: bx lr343entry:344 %0 = zext i16 %p to i32345 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)346 %2 = and <4 x i32> %a, <i32 -6553601, i32 -6553601, i32 -6553601, i32 -6553601>347 %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %a348 ret <4 x i32> %3349}350 351define arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_n_u32_sh24(<4 x i32> %a, i16 zeroext %p) {352; CHECK-LE-LABEL: test_vbicq_m_n_u32_sh24:353; CHECK-LE: @ %bb.0: @ %entry354; CHECK-LE-NEXT: vmsr p0, r0355; CHECK-LE-NEXT: vpst356; CHECK-LE-NEXT: vbict.i32 q0, #0x64000000357; CHECK-LE-NEXT: bx lr358;359; CHECK-BE-LABEL: test_vbicq_m_n_u32_sh24:360; CHECK-BE: @ %bb.0: @ %entry361; CHECK-BE-NEXT: vrev64.32 q1, q0362; CHECK-BE-NEXT: vmsr p0, r0363; CHECK-BE-NEXT: vpst364; CHECK-BE-NEXT: vbict.i32 q1, #0x64000000365; CHECK-BE-NEXT: vrev64.32 q0, q1366; CHECK-BE-NEXT: bx lr367entry:368 %0 = zext i16 %p to i32369 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)370 %2 = and <4 x i32> %a, <i32 -1677721601, i32 -1677721601, i32 -1677721601, i32 -1677721601>371 %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %a372 ret <4 x i32> %3373}374 375define arm_aapcs_vfpcc <8 x i16> @test_vorrq_m_n_u16_sh0(<8 x i16> %a, i16 zeroext %p) {376; CHECK-LE-LABEL: test_vorrq_m_n_u16_sh0:377; CHECK-LE: @ %bb.0: @ %entry378; CHECK-LE-NEXT: vmsr p0, r0379; CHECK-LE-NEXT: vpst380; CHECK-LE-NEXT: vorrt.i16 q0, #0x64381; CHECK-LE-NEXT: bx lr382;383; CHECK-BE-LABEL: test_vorrq_m_n_u16_sh0:384; CHECK-BE: @ %bb.0: @ %entry385; CHECK-BE-NEXT: vrev64.16 q1, q0386; CHECK-BE-NEXT: vmsr p0, r0387; CHECK-BE-NEXT: vpst388; CHECK-BE-NEXT: vorrt.i16 q1, #0x64389; CHECK-BE-NEXT: vrev64.16 q0, q1390; CHECK-BE-NEXT: bx lr391entry:392 %0 = zext i16 %p to i32393 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)394 %2 = or <8 x i16> %a, <i16 100, i16 100, i16 100, i16 100, i16 100, i16 100, i16 100, i16 100>395 %3 = select <8 x i1> %1, <8 x i16> %2, <8 x i16> %a396 ret <8 x i16> %3397}398 399define arm_aapcs_vfpcc <8 x i16> @test_vorrq_m_n_u16_sh8(<8 x i16> %a, i16 zeroext %p) {400; CHECK-LE-LABEL: test_vorrq_m_n_u16_sh8:401; CHECK-LE: @ %bb.0: @ %entry402; CHECK-LE-NEXT: vmsr p0, r0403; CHECK-LE-NEXT: vpst404; CHECK-LE-NEXT: vorrt.i16 q0, #0x6400405; CHECK-LE-NEXT: bx lr406;407; CHECK-BE-LABEL: test_vorrq_m_n_u16_sh8:408; CHECK-BE: @ %bb.0: @ %entry409; CHECK-BE-NEXT: vrev64.16 q1, q0410; CHECK-BE-NEXT: vmsr p0, r0411; CHECK-BE-NEXT: vpst412; CHECK-BE-NEXT: vorrt.i16 q1, #0x6400413; CHECK-BE-NEXT: vrev64.16 q0, q1414; CHECK-BE-NEXT: bx lr415entry:416 %0 = zext i16 %p to i32417 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)418 %2 = or <8 x i16> %a, <i16 25600, i16 25600, i16 25600, i16 25600, i16 25600, i16 25600, i16 25600, i16 25600>419 %3 = select <8 x i1> %1, <8 x i16> %2, <8 x i16> %a420 ret <8 x i16> %3421}422 423define arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_n_u32_sh0(<4 x i32> %a, i16 zeroext %p) {424; CHECK-LE-LABEL: test_vorrq_m_n_u32_sh0:425; CHECK-LE: @ %bb.0: @ %entry426; CHECK-LE-NEXT: vmsr p0, r0427; CHECK-LE-NEXT: vpst428; CHECK-LE-NEXT: vorrt.i32 q0, #0x64429; CHECK-LE-NEXT: bx lr430;431; CHECK-BE-LABEL: test_vorrq_m_n_u32_sh0:432; CHECK-BE: @ %bb.0: @ %entry433; CHECK-BE-NEXT: vrev64.32 q1, q0434; CHECK-BE-NEXT: vmsr p0, r0435; CHECK-BE-NEXT: vpst436; CHECK-BE-NEXT: vorrt.i32 q1, #0x64437; CHECK-BE-NEXT: vrev64.32 q0, q1438; CHECK-BE-NEXT: bx lr439entry:440 %0 = zext i16 %p to i32441 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)442 %2 = or <4 x i32> %a, <i32 100, i32 100, i32 100, i32 100>443 %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %a444 ret <4 x i32> %3445}446 447define arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_n_u32_sh8(<4 x i32> %a, i16 zeroext %p) {448; CHECK-LE-LABEL: test_vorrq_m_n_u32_sh8:449; CHECK-LE: @ %bb.0: @ %entry450; CHECK-LE-NEXT: vmsr p0, r0451; CHECK-LE-NEXT: vpst452; CHECK-LE-NEXT: vorrt.i32 q0, #0x6400453; CHECK-LE-NEXT: bx lr454;455; CHECK-BE-LABEL: test_vorrq_m_n_u32_sh8:456; CHECK-BE: @ %bb.0: @ %entry457; CHECK-BE-NEXT: vrev64.32 q1, q0458; CHECK-BE-NEXT: vmsr p0, r0459; CHECK-BE-NEXT: vpst460; CHECK-BE-NEXT: vorrt.i32 q1, #0x6400461; CHECK-BE-NEXT: vrev64.32 q0, q1462; CHECK-BE-NEXT: bx lr463entry:464 %0 = zext i16 %p to i32465 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)466 %2 = or <4 x i32> %a, <i32 25600, i32 25600, i32 25600, i32 25600>467 %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %a468 ret <4 x i32> %3469}470 471define arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_n_u32_sh16(<4 x i32> %a, i16 zeroext %p) {472; CHECK-LE-LABEL: test_vorrq_m_n_u32_sh16:473; CHECK-LE: @ %bb.0: @ %entry474; CHECK-LE-NEXT: vmsr p0, r0475; CHECK-LE-NEXT: vpst476; CHECK-LE-NEXT: vorrt.i32 q0, #0x640000477; CHECK-LE-NEXT: bx lr478;479; CHECK-BE-LABEL: test_vorrq_m_n_u32_sh16:480; CHECK-BE: @ %bb.0: @ %entry481; CHECK-BE-NEXT: vrev64.32 q1, q0482; CHECK-BE-NEXT: vmsr p0, r0483; CHECK-BE-NEXT: vpst484; CHECK-BE-NEXT: vorrt.i32 q1, #0x640000485; CHECK-BE-NEXT: vrev64.32 q0, q1486; CHECK-BE-NEXT: bx lr487entry:488 %0 = zext i16 %p to i32489 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)490 %2 = or <4 x i32> %a, <i32 6553600, i32 6553600, i32 6553600, i32 6553600>491 %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %a492 ret <4 x i32> %3493}494 495define arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_n_u32_sh24(<4 x i32> %a, i16 zeroext %p) {496; CHECK-LE-LABEL: test_vorrq_m_n_u32_sh24:497; CHECK-LE: @ %bb.0: @ %entry498; CHECK-LE-NEXT: vmsr p0, r0499; CHECK-LE-NEXT: vpst500; CHECK-LE-NEXT: vorrt.i32 q0, #0x64000000501; CHECK-LE-NEXT: bx lr502;503; CHECK-BE-LABEL: test_vorrq_m_n_u32_sh24:504; CHECK-BE: @ %bb.0: @ %entry505; CHECK-BE-NEXT: vrev64.32 q1, q0506; CHECK-BE-NEXT: vmsr p0, r0507; CHECK-BE-NEXT: vpst508; CHECK-BE-NEXT: vorrt.i32 q1, #0x64000000509; CHECK-BE-NEXT: vrev64.32 q0, q1510; CHECK-BE-NEXT: bx lr511entry:512 %0 = zext i16 %p to i32513 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)514 %2 = or <4 x i32> %a, <i32 1677721600, i32 1677721600, i32 1677721600, i32 1677721600>515 %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %a516 ret <4 x i32> %3517}518 519define arm_aapcs_vfpcc <8 x i16> @test_vmvnq_n_u16() {520; CHECK-LABEL: test_vmvnq_n_u16:521; CHECK: @ %bb.0: @ %entry522; CHECK-NEXT: vmvn.i16 q0, #0xaa00523; CHECK-NEXT: bx lr524entry:525 ret <8 x i16> <i16 -43521, i16 -43521, i16 -43521, i16 -43521, i16 -43521, i16 -43521, i16 -43521, i16 -43521>526}527 528define arm_aapcs_vfpcc <4 x i32> @test_vmvnq_n_u32() {529; CHECK-LABEL: test_vmvnq_n_u32:530; CHECK: @ %bb.0: @ %entry531; CHECK-NEXT: vmvn.i32 q0, #0xaa00532; CHECK-NEXT: bx lr533entry:534 ret <4 x i32> <i32 -43521, i32 -43521, i32 -43521, i32 -43521>535}536 537define arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_n_u16(<8 x i16> %inactive, i16 zeroext %p) {538; CHECK-LE-LABEL: test_vmvnq_m_n_u16:539; CHECK-LE: @ %bb.0: @ %entry540; CHECK-LE-NEXT: vmsr p0, r0541; CHECK-LE-NEXT: vpst542; CHECK-LE-NEXT: vmvnt.i16 q0, #0xaa00543; CHECK-LE-NEXT: bx lr544;545; CHECK-BE-LABEL: test_vmvnq_m_n_u16:546; CHECK-BE: @ %bb.0: @ %entry547; CHECK-BE-NEXT: vrev64.16 q1, q0548; CHECK-BE-NEXT: vmsr p0, r0549; CHECK-BE-NEXT: vpst550; CHECK-BE-NEXT: vmvnt.i16 q1, #0xaa00551; CHECK-BE-NEXT: vrev64.16 q0, q1552; CHECK-BE-NEXT: bx lr553entry:554 %0 = zext i16 %p to i32555 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)556 %2 = select <8 x i1> %1, <8 x i16> <i16 -43521, i16 -43521, i16 -43521, i16 -43521, i16 -43521, i16 -43521, i16 -43521, i16 -43521>, <8 x i16> %inactive557 ret <8 x i16> %2558}559 560define arm_aapcs_vfpcc <4 x i32> @test_vmvnq_m_n_u32(<4 x i32> %inactive, i16 zeroext %p) {561; CHECK-LE-LABEL: test_vmvnq_m_n_u32:562; CHECK-LE: @ %bb.0: @ %entry563; CHECK-LE-NEXT: vmsr p0, r0564; CHECK-LE-NEXT: vpst565; CHECK-LE-NEXT: vmvnt.i32 q0, #0xaa00566; CHECK-LE-NEXT: bx lr567;568; CHECK-BE-LABEL: test_vmvnq_m_n_u32:569; CHECK-BE: @ %bb.0: @ %entry570; CHECK-BE-NEXT: vrev64.32 q1, q0571; CHECK-BE-NEXT: vmsr p0, r0572; CHECK-BE-NEXT: vpst573; CHECK-BE-NEXT: vmvnt.i32 q1, #0xaa00574; CHECK-BE-NEXT: vrev64.32 q0, q1575; CHECK-BE-NEXT: bx lr576entry:577 %0 = zext i16 %p to i32578 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)579 %2 = select <4 x i1> %1, <4 x i32> <i32 -43521, i32 -43521, i32 -43521, i32 -43521>, <4 x i32> %inactive580 ret <4 x i32> %2581}582 583declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)584declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)585