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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s3 4define arm_aapcs_vfpcc <8 x half> @test_vdupq_n_f16(float %a.coerce) {5; CHECK-LABEL: test_vdupq_n_f16:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vmov r0, s08; CHECK-NEXT: vdup.16 q0, r09; CHECK-NEXT: bx lr10entry:11 %0 = bitcast float %a.coerce to i3212 %tmp.0.extract.trunc = trunc i32 %0 to i1613 %1 = bitcast i16 %tmp.0.extract.trunc to half14 %.splatinsert = insertelement <8 x half> undef, half %1, i32 015 %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> undef, <8 x i32> zeroinitializer16 ret <8 x half> %.splat17}18 19define arm_aapcs_vfpcc <4 x float> @test_vdupq_n_f32(float %a) {20; CHECK-LABEL: test_vdupq_n_f32:21; CHECK: @ %bb.0: @ %entry22; CHECK-NEXT: vmov r0, s023; CHECK-NEXT: vdup.32 q0, r024; CHECK-NEXT: bx lr25entry:26 %.splatinsert = insertelement <4 x float> undef, float %a, i32 027 %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer28 ret <4 x float> %.splat29}30 31define arm_aapcs_vfpcc <16 x i8> @test_vdupq_n_s8(i8 signext %a) {32; CHECK-LABEL: test_vdupq_n_s8:33; CHECK: @ %bb.0: @ %entry34; CHECK-NEXT: vdup.8 q0, r035; CHECK-NEXT: bx lr36entry:37 %.splatinsert = insertelement <16 x i8> undef, i8 %a, i32 038 %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer39 ret <16 x i8> %.splat40}41 42define arm_aapcs_vfpcc <8 x i16> @test_vdupq_n_s16(i16 signext %a) {43; CHECK-LABEL: test_vdupq_n_s16:44; CHECK: @ %bb.0: @ %entry45; CHECK-NEXT: vdup.16 q0, r046; CHECK-NEXT: bx lr47entry:48 %.splatinsert = insertelement <8 x i16> undef, i16 %a, i32 049 %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer50 ret <8 x i16> %.splat51}52 53define arm_aapcs_vfpcc <4 x i32> @test_vdupq_n_s32(i32 %a) {54; CHECK-LABEL: test_vdupq_n_s32:55; CHECK: @ %bb.0: @ %entry56; CHECK-NEXT: vdup.32 q0, r057; CHECK-NEXT: bx lr58entry:59 %.splatinsert = insertelement <4 x i32> undef, i32 %a, i32 060 %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer61 ret <4 x i32> %.splat62}63 64define arm_aapcs_vfpcc <16 x i8> @test_vdupq_n_u8(i8 zeroext %a) {65; CHECK-LABEL: test_vdupq_n_u8:66; CHECK: @ %bb.0: @ %entry67; CHECK-NEXT: vdup.8 q0, r068; CHECK-NEXT: bx lr69entry:70 %.splatinsert = insertelement <16 x i8> undef, i8 %a, i32 071 %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer72 ret <16 x i8> %.splat73}74 75define arm_aapcs_vfpcc <8 x i16> @test_vdupq_n_u16(i16 zeroext %a) {76; CHECK-LABEL: test_vdupq_n_u16:77; CHECK: @ %bb.0: @ %entry78; CHECK-NEXT: vdup.16 q0, r079; CHECK-NEXT: bx lr80entry:81 %.splatinsert = insertelement <8 x i16> undef, i16 %a, i32 082 %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer83 ret <8 x i16> %.splat84}85 86define arm_aapcs_vfpcc <4 x i32> @test_vdupq_n_u32(i32 %a) {87; CHECK-LABEL: test_vdupq_n_u32:88; CHECK: @ %bb.0: @ %entry89; CHECK-NEXT: vdup.32 q0, r090; CHECK-NEXT: bx lr91entry:92 %.splatinsert = insertelement <4 x i32> undef, i32 %a, i32 093 %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer94 ret <4 x i32> %.splat95}96 97define arm_aapcs_vfpcc <8 x half> @test_vdupq_m_n_f16(<8 x half> %inactive, float %a.coerce, i16 zeroext %p) {98; CHECK-LABEL: test_vdupq_m_n_f16:99; CHECK: @ %bb.0: @ %entry100; CHECK-NEXT: vmov r1, s4101; CHECK-NEXT: vmsr p0, r0102; CHECK-NEXT: vpst103; CHECK-NEXT: vdupt.16 q0, r1104; CHECK-NEXT: bx lr105entry:106 %0 = bitcast float %a.coerce to i32107 %tmp.0.extract.trunc = trunc i32 %0 to i16108 %1 = bitcast i16 %tmp.0.extract.trunc to half109 %2 = zext i16 %p to i32110 %3 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)111 %.splatinsert = insertelement <8 x half> undef, half %1, i32 0112 %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> undef, <8 x i32> zeroinitializer113 %4 = select <8 x i1> %3, <8 x half> %.splat, <8 x half> %inactive114 ret <8 x half> %4115}116 117define arm_aapcs_vfpcc <4 x float> @test_vdupq_m_n_f32(<4 x float> %inactive, float %a, i16 zeroext %p) {118; CHECK-LABEL: test_vdupq_m_n_f32:119; CHECK: @ %bb.0: @ %entry120; CHECK-NEXT: vmov r1, s4121; CHECK-NEXT: vmsr p0, r0122; CHECK-NEXT: vpst123; CHECK-NEXT: vdupt.32 q0, r1124; CHECK-NEXT: bx lr125entry:126 %0 = zext i16 %p to i32127 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)128 %.splatinsert = insertelement <4 x float> undef, float %a, i32 0129 %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer130 %2 = select <4 x i1> %1, <4 x float> %.splat, <4 x float> %inactive131 ret <4 x float> %2132}133 134define arm_aapcs_vfpcc <16 x i8> @test_vdupq_m_n_s8(<16 x i8> %inactive, i8 signext %a, i16 zeroext %p) {135; CHECK-LABEL: test_vdupq_m_n_s8:136; CHECK: @ %bb.0: @ %entry137; CHECK-NEXT: vmsr p0, r1138; CHECK-NEXT: vpst139; CHECK-NEXT: vdupt.8 q0, r0140; CHECK-NEXT: bx lr141entry:142 %0 = zext i16 %p to i32143 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)144 %.splatinsert = insertelement <16 x i8> undef, i8 %a, i32 0145 %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer146 %2 = select <16 x i1> %1, <16 x i8> %.splat, <16 x i8> %inactive147 ret <16 x i8> %2148}149 150define arm_aapcs_vfpcc <8 x i16> @test_vdupq_m_n_s16(<8 x i16> %inactive, i16 signext %a, i16 zeroext %p) {151; CHECK-LABEL: test_vdupq_m_n_s16:152; CHECK: @ %bb.0: @ %entry153; CHECK-NEXT: vmsr p0, r1154; CHECK-NEXT: vpst155; CHECK-NEXT: vdupt.16 q0, r0156; CHECK-NEXT: bx lr157entry:158 %0 = zext i16 %p to i32159 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)160 %.splatinsert = insertelement <8 x i16> undef, i16 %a, i32 0161 %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer162 %2 = select <8 x i1> %1, <8 x i16> %.splat, <8 x i16> %inactive163 ret <8 x i16> %2164}165 166define arm_aapcs_vfpcc <4 x i32> @test_vdupq_m_n_s32(<4 x i32> %inactive, i32 %a, i16 zeroext %p) {167; CHECK-LABEL: test_vdupq_m_n_s32:168; CHECK: @ %bb.0: @ %entry169; CHECK-NEXT: vmsr p0, r1170; CHECK-NEXT: vpst171; CHECK-NEXT: vdupt.32 q0, r0172; CHECK-NEXT: bx lr173entry:174 %0 = zext i16 %p to i32175 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)176 %.splatinsert = insertelement <4 x i32> undef, i32 %a, i32 0177 %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer178 %2 = select <4 x i1> %1, <4 x i32> %.splat, <4 x i32> %inactive179 ret <4 x i32> %2180}181 182define arm_aapcs_vfpcc <16 x i8> @test_vdupq_m_n_u8(<16 x i8> %inactive, i8 zeroext %a, i16 zeroext %p) {183; CHECK-LABEL: test_vdupq_m_n_u8:184; CHECK: @ %bb.0: @ %entry185; CHECK-NEXT: vmsr p0, r1186; CHECK-NEXT: vpst187; CHECK-NEXT: vdupt.8 q0, r0188; CHECK-NEXT: bx lr189entry:190 %0 = zext i16 %p to i32191 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)192 %.splatinsert = insertelement <16 x i8> undef, i8 %a, i32 0193 %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer194 %2 = select <16 x i1> %1, <16 x i8> %.splat, <16 x i8> %inactive195 ret <16 x i8> %2196}197 198define arm_aapcs_vfpcc <8 x i16> @test_vdupq_m_n_u16(<8 x i16> %inactive, i16 zeroext %a, i16 zeroext %p) {199; CHECK-LABEL: test_vdupq_m_n_u16:200; CHECK: @ %bb.0: @ %entry201; CHECK-NEXT: vmsr p0, r1202; CHECK-NEXT: vpst203; CHECK-NEXT: vdupt.16 q0, r0204; CHECK-NEXT: bx lr205entry:206 %0 = zext i16 %p to i32207 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)208 %.splatinsert = insertelement <8 x i16> undef, i16 %a, i32 0209 %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer210 %2 = select <8 x i1> %1, <8 x i16> %.splat, <8 x i16> %inactive211 ret <8 x i16> %2212}213 214define arm_aapcs_vfpcc <4 x i32> @test_vdupq_m_n_u32(<4 x i32> %inactive, i32 %a, i16 zeroext %p) {215; CHECK-LABEL: test_vdupq_m_n_u32:216; CHECK: @ %bb.0: @ %entry217; CHECK-NEXT: vmsr p0, r1218; CHECK-NEXT: vpst219; CHECK-NEXT: vdupt.32 q0, r0220; CHECK-NEXT: bx lr221entry:222 %0 = zext i16 %p to i32223 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)224 %.splatinsert = insertelement <4 x i32> undef, i32 %a, i32 0225 %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer226 %2 = select <4 x i1> %1, <4 x i32> %.splat, <4 x i32> %inactive227 ret <4 x i32> %2228}229 230declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)231declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)232declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)233