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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s3 4define arm_aapcs_vfpcc <16 x i8> @test_vidupq_n_u8(i32 %a) {5; CHECK-LABEL: test_vidupq_n_u8:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vidup.u8 q0, r0, #48; CHECK-NEXT: bx lr9entry:10 %0 = tail call { <16 x i8>, i32 } @llvm.arm.mve.vidup.v16i8(i32 %a, i32 4)11 %1 = extractvalue { <16 x i8>, i32 } %0, 012 ret <16 x i8> %113}14 15define arm_aapcs_vfpcc <8 x i16> @test_vidupq_n_u16(i32 %a) {16; CHECK-LABEL: test_vidupq_n_u16:17; CHECK: @ %bb.0: @ %entry18; CHECK-NEXT: vidup.u16 q0, r0, #119; CHECK-NEXT: bx lr20entry:21 %0 = tail call { <8 x i16>, i32 } @llvm.arm.mve.vidup.v8i16(i32 %a, i32 1)22 %1 = extractvalue { <8 x i16>, i32 } %0, 023 ret <8 x i16> %124}25 26define arm_aapcs_vfpcc <4 x i32> @test_vidupq_n_u32(i32 %a) {27; CHECK-LABEL: test_vidupq_n_u32:28; CHECK: @ %bb.0: @ %entry29; CHECK-NEXT: vidup.u32 q0, r0, #430; CHECK-NEXT: bx lr31entry:32 %0 = tail call { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32 %a, i32 4)33 %1 = extractvalue { <4 x i32>, i32 } %0, 034 ret <4 x i32> %135}36 37define arm_aapcs_vfpcc <16 x i8> @test_vddupq_n_u8(i32 %a) {38; CHECK-LABEL: test_vddupq_n_u8:39; CHECK: @ %bb.0: @ %entry40; CHECK-NEXT: vddup.u8 q0, r0, #241; CHECK-NEXT: bx lr42entry:43 %0 = tail call { <16 x i8>, i32 } @llvm.arm.mve.vddup.v16i8(i32 %a, i32 2)44 %1 = extractvalue { <16 x i8>, i32 } %0, 045 ret <16 x i8> %146}47 48define arm_aapcs_vfpcc <8 x i16> @test_vddupq_n_u16(i32 %a) {49; CHECK-LABEL: test_vddupq_n_u16:50; CHECK: @ %bb.0: @ %entry51; CHECK-NEXT: vddup.u16 q0, r0, #452; CHECK-NEXT: bx lr53entry:54 %0 = tail call { <8 x i16>, i32 } @llvm.arm.mve.vddup.v8i16(i32 %a, i32 4)55 %1 = extractvalue { <8 x i16>, i32 } %0, 056 ret <8 x i16> %157}58 59define arm_aapcs_vfpcc <4 x i32> @test_vddupq_n_u32(i32 %a) {60; CHECK-LABEL: test_vddupq_n_u32:61; CHECK: @ %bb.0: @ %entry62; CHECK-NEXT: vddup.u32 q0, r0, #263; CHECK-NEXT: bx lr64entry:65 %0 = tail call { <4 x i32>, i32 } @llvm.arm.mve.vddup.v4i32(i32 %a, i32 2)66 %1 = extractvalue { <4 x i32>, i32 } %0, 067 ret <4 x i32> %168}69 70define arm_aapcs_vfpcc <16 x i8> @test_viwdupq_n_u8(i32 %a, i32 %b) {71; CHECK-LABEL: test_viwdupq_n_u8:72; CHECK: @ %bb.0: @ %entry73; CHECK-NEXT: viwdup.u8 q0, r0, r1, #474; CHECK-NEXT: bx lr75entry:76 %0 = tail call { <16 x i8>, i32 } @llvm.arm.mve.viwdup.v16i8(i32 %a, i32 %b, i32 4)77 %1 = extractvalue { <16 x i8>, i32 } %0, 078 ret <16 x i8> %179}80 81define arm_aapcs_vfpcc <8 x i16> @test_viwdupq_n_u16(i32 %a, i32 %b) {82; CHECK-LABEL: test_viwdupq_n_u16:83; CHECK: @ %bb.0: @ %entry84; CHECK-NEXT: viwdup.u16 q0, r0, r1, #285; CHECK-NEXT: bx lr86entry:87 %0 = tail call { <8 x i16>, i32 } @llvm.arm.mve.viwdup.v8i16(i32 %a, i32 %b, i32 2)88 %1 = extractvalue { <8 x i16>, i32 } %0, 089 ret <8 x i16> %190}91 92define arm_aapcs_vfpcc <4 x i32> @test_viwdupq_n_u32(i32 %a, i32 %b) {93; CHECK-LABEL: test_viwdupq_n_u32:94; CHECK: @ %bb.0: @ %entry95; CHECK-NEXT: viwdup.u32 q0, r0, r1, #896; CHECK-NEXT: bx lr97entry:98 %0 = tail call { <4 x i32>, i32 } @llvm.arm.mve.viwdup.v4i32(i32 %a, i32 %b, i32 8)99 %1 = extractvalue { <4 x i32>, i32 } %0, 0100 ret <4 x i32> %1101}102 103define arm_aapcs_vfpcc <16 x i8> @test_vdwdupq_n_u8(i32 %a, i32 %b) {104; CHECK-LABEL: test_vdwdupq_n_u8:105; CHECK: @ %bb.0: @ %entry106; CHECK-NEXT: vdwdup.u8 q0, r0, r1, #4107; CHECK-NEXT: bx lr108entry:109 %0 = tail call { <16 x i8>, i32 } @llvm.arm.mve.vdwdup.v16i8(i32 %a, i32 %b, i32 4)110 %1 = extractvalue { <16 x i8>, i32 } %0, 0111 ret <16 x i8> %1112}113 114define arm_aapcs_vfpcc <8 x i16> @test_vdwdupq_n_u16(i32 %a, i32 %b) {115; CHECK-LABEL: test_vdwdupq_n_u16:116; CHECK: @ %bb.0: @ %entry117; CHECK-NEXT: vdwdup.u16 q0, r0, r1, #8118; CHECK-NEXT: bx lr119entry:120 %0 = tail call { <8 x i16>, i32 } @llvm.arm.mve.vdwdup.v8i16(i32 %a, i32 %b, i32 8)121 %1 = extractvalue { <8 x i16>, i32 } %0, 0122 ret <8 x i16> %1123}124 125define arm_aapcs_vfpcc <4 x i32> @test_vdwdupq_n_u32(i32 %a, i32 %b) {126; CHECK-LABEL: test_vdwdupq_n_u32:127; CHECK: @ %bb.0: @ %entry128; CHECK-NEXT: vdwdup.u32 q0, r0, r1, #1129; CHECK-NEXT: bx lr130entry:131 %0 = tail call { <4 x i32>, i32 } @llvm.arm.mve.vdwdup.v4i32(i32 %a, i32 %b, i32 1)132 %1 = extractvalue { <4 x i32>, i32 } %0, 0133 ret <4 x i32> %1134}135 136define arm_aapcs_vfpcc <16 x i8> @test_vidupq_wb_u8(ptr nocapture %a) {137; CHECK-LABEL: test_vidupq_wb_u8:138; CHECK: @ %bb.0: @ %entry139; CHECK-NEXT: ldr r2, [r0]140; CHECK-NEXT: vidup.u8 q0, r2, #8141; CHECK-NEXT: str r2, [r0]142; CHECK-NEXT: bx lr143entry:144 %0 = load i32, ptr %a, align 4145 %1 = tail call { <16 x i8>, i32 } @llvm.arm.mve.vidup.v16i8(i32 %0, i32 8)146 %2 = extractvalue { <16 x i8>, i32 } %1, 1147 store i32 %2, ptr %a, align 4148 %3 = extractvalue { <16 x i8>, i32 } %1, 0149 ret <16 x i8> %3150}151 152define arm_aapcs_vfpcc <8 x i16> @test_vidupq_wb_u16(ptr nocapture %a) {153; CHECK-LABEL: test_vidupq_wb_u16:154; CHECK: @ %bb.0: @ %entry155; CHECK-NEXT: ldr r2, [r0]156; CHECK-NEXT: vidup.u16 q0, r2, #1157; CHECK-NEXT: str r2, [r0]158; CHECK-NEXT: bx lr159entry:160 %0 = load i32, ptr %a, align 4161 %1 = tail call { <8 x i16>, i32 } @llvm.arm.mve.vidup.v8i16(i32 %0, i32 1)162 %2 = extractvalue { <8 x i16>, i32 } %1, 1163 store i32 %2, ptr %a, align 4164 %3 = extractvalue { <8 x i16>, i32 } %1, 0165 ret <8 x i16> %3166}167 168define arm_aapcs_vfpcc <4 x i32> @test_vidupq_wb_u32(ptr nocapture %a) {169; CHECK-LABEL: test_vidupq_wb_u32:170; CHECK: @ %bb.0: @ %entry171; CHECK-NEXT: ldr r2, [r0]172; CHECK-NEXT: vidup.u32 q0, r2, #4173; CHECK-NEXT: str r2, [r0]174; CHECK-NEXT: bx lr175entry:176 %0 = load i32, ptr %a, align 4177 %1 = tail call { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32 %0, i32 4)178 %2 = extractvalue { <4 x i32>, i32 } %1, 1179 store i32 %2, ptr %a, align 4180 %3 = extractvalue { <4 x i32>, i32 } %1, 0181 ret <4 x i32> %3182}183 184define arm_aapcs_vfpcc <16 x i8> @test_vddupq_wb_u8(ptr nocapture %a) {185; CHECK-LABEL: test_vddupq_wb_u8:186; CHECK: @ %bb.0: @ %entry187; CHECK-NEXT: ldr r2, [r0]188; CHECK-NEXT: vddup.u8 q0, r2, #2189; CHECK-NEXT: str r2, [r0]190; CHECK-NEXT: bx lr191entry:192 %0 = load i32, ptr %a, align 4193 %1 = tail call { <16 x i8>, i32 } @llvm.arm.mve.vddup.v16i8(i32 %0, i32 2)194 %2 = extractvalue { <16 x i8>, i32 } %1, 1195 store i32 %2, ptr %a, align 4196 %3 = extractvalue { <16 x i8>, i32 } %1, 0197 ret <16 x i8> %3198}199 200define arm_aapcs_vfpcc <8 x i16> @test_vddupq_wb_u16(ptr nocapture %a) {201; CHECK-LABEL: test_vddupq_wb_u16:202; CHECK: @ %bb.0: @ %entry203; CHECK-NEXT: ldr r2, [r0]204; CHECK-NEXT: vddup.u16 q0, r2, #8205; CHECK-NEXT: str r2, [r0]206; CHECK-NEXT: bx lr207entry:208 %0 = load i32, ptr %a, align 4209 %1 = tail call { <8 x i16>, i32 } @llvm.arm.mve.vddup.v8i16(i32 %0, i32 8)210 %2 = extractvalue { <8 x i16>, i32 } %1, 1211 store i32 %2, ptr %a, align 4212 %3 = extractvalue { <8 x i16>, i32 } %1, 0213 ret <8 x i16> %3214}215 216define arm_aapcs_vfpcc <4 x i32> @test_vddupq_wb_u32(ptr nocapture %a) {217; CHECK-LABEL: test_vddupq_wb_u32:218; CHECK: @ %bb.0: @ %entry219; CHECK-NEXT: ldr r2, [r0]220; CHECK-NEXT: vddup.u32 q0, r2, #2221; CHECK-NEXT: str r2, [r0]222; CHECK-NEXT: bx lr223entry:224 %0 = load i32, ptr %a, align 4225 %1 = tail call { <4 x i32>, i32 } @llvm.arm.mve.vddup.v4i32(i32 %0, i32 2)226 %2 = extractvalue { <4 x i32>, i32 } %1, 1227 store i32 %2, ptr %a, align 4228 %3 = extractvalue { <4 x i32>, i32 } %1, 0229 ret <4 x i32> %3230}231 232define arm_aapcs_vfpcc <16 x i8> @test_vdwdupq_wb_u8(ptr nocapture %a, i32 %b) {233; CHECK-LABEL: test_vdwdupq_wb_u8:234; CHECK: @ %bb.0: @ %entry235; CHECK-NEXT: ldr r2, [r0]236; CHECK-NEXT: vdwdup.u8 q0, r2, r1, #4237; CHECK-NEXT: str r2, [r0]238; CHECK-NEXT: bx lr239entry:240 %0 = load i32, ptr %a, align 4241 %1 = tail call { <16 x i8>, i32 } @llvm.arm.mve.vdwdup.v16i8(i32 %0, i32 %b, i32 4)242 %2 = extractvalue { <16 x i8>, i32 } %1, 1243 store i32 %2, ptr %a, align 4244 %3 = extractvalue { <16 x i8>, i32 } %1, 0245 ret <16 x i8> %3246}247 248define arm_aapcs_vfpcc <8 x i16> @test_vdwdupq_wb_u16(ptr nocapture %a, i32 %b) {249; CHECK-LABEL: test_vdwdupq_wb_u16:250; CHECK: @ %bb.0: @ %entry251; CHECK-NEXT: ldr r2, [r0]252; CHECK-NEXT: vdwdup.u16 q0, r2, r1, #4253; CHECK-NEXT: str r2, [r0]254; CHECK-NEXT: bx lr255entry:256 %0 = load i32, ptr %a, align 4257 %1 = tail call { <8 x i16>, i32 } @llvm.arm.mve.vdwdup.v8i16(i32 %0, i32 %b, i32 4)258 %2 = extractvalue { <8 x i16>, i32 } %1, 1259 store i32 %2, ptr %a, align 4260 %3 = extractvalue { <8 x i16>, i32 } %1, 0261 ret <8 x i16> %3262}263 264define arm_aapcs_vfpcc <16 x i8> @test_viwdupq_wb_u8(ptr nocapture %a, i32 %b) {265; CHECK-LABEL: test_viwdupq_wb_u8:266; CHECK: @ %bb.0: @ %entry267; CHECK-NEXT: ldr r2, [r0]268; CHECK-NEXT: viwdup.u8 q0, r2, r1, #1269; CHECK-NEXT: str r2, [r0]270; CHECK-NEXT: bx lr271entry:272 %0 = load i32, ptr %a, align 4273 %1 = tail call { <16 x i8>, i32 } @llvm.arm.mve.viwdup.v16i8(i32 %0, i32 %b, i32 1)274 %2 = extractvalue { <16 x i8>, i32 } %1, 1275 store i32 %2, ptr %a, align 4276 %3 = extractvalue { <16 x i8>, i32 } %1, 0277 ret <16 x i8> %3278}279 280define arm_aapcs_vfpcc <8 x i16> @test_viwdupq_wb_u16(ptr nocapture %a, i32 %b) {281; CHECK-LABEL: test_viwdupq_wb_u16:282; CHECK: @ %bb.0: @ %entry283; CHECK-NEXT: ldr r2, [r0]284; CHECK-NEXT: viwdup.u16 q0, r2, r1, #1285; CHECK-NEXT: str r2, [r0]286; CHECK-NEXT: bx lr287entry:288 %0 = load i32, ptr %a, align 4289 %1 = tail call { <8 x i16>, i32 } @llvm.arm.mve.viwdup.v8i16(i32 %0, i32 %b, i32 1)290 %2 = extractvalue { <8 x i16>, i32 } %1, 1291 store i32 %2, ptr %a, align 4292 %3 = extractvalue { <8 x i16>, i32 } %1, 0293 ret <8 x i16> %3294}295 296define arm_aapcs_vfpcc <4 x i32> @test_viwdupq_wb_u32(ptr nocapture %a, i32 %b) {297; CHECK-LABEL: test_viwdupq_wb_u32:298; CHECK: @ %bb.0: @ %entry299; CHECK-NEXT: ldr r2, [r0]300; CHECK-NEXT: viwdup.u32 q0, r2, r1, #8301; CHECK-NEXT: str r2, [r0]302; CHECK-NEXT: bx lr303entry:304 %0 = load i32, ptr %a, align 4305 %1 = tail call { <4 x i32>, i32 } @llvm.arm.mve.viwdup.v4i32(i32 %0, i32 %b, i32 8)306 %2 = extractvalue { <4 x i32>, i32 } %1, 1307 store i32 %2, ptr %a, align 4308 %3 = extractvalue { <4 x i32>, i32 } %1, 0309 ret <4 x i32> %3310}311 312define arm_aapcs_vfpcc <4 x i32> @test_vdwdupq_wb_u32(ptr nocapture %a, i32 %b) {313; CHECK-LABEL: test_vdwdupq_wb_u32:314; CHECK: @ %bb.0: @ %entry315; CHECK-NEXT: ldr r2, [r0]316; CHECK-NEXT: vdwdup.u32 q0, r2, r1, #2317; CHECK-NEXT: str r2, [r0]318; CHECK-NEXT: bx lr319entry:320 %0 = load i32, ptr %a, align 4321 %1 = tail call { <4 x i32>, i32 } @llvm.arm.mve.vdwdup.v4i32(i32 %0, i32 %b, i32 2)322 %2 = extractvalue { <4 x i32>, i32 } %1, 1323 store i32 %2, ptr %a, align 4324 %3 = extractvalue { <4 x i32>, i32 } %1, 0325 ret <4 x i32> %3326}327 328define arm_aapcs_vfpcc <16 x i8> @test_vidupq_m_n_u8(<16 x i8> %inactive, i32 %a, i16 zeroext %p) {329; CHECK-LABEL: test_vidupq_m_n_u8:330; CHECK: @ %bb.0: @ %entry331; CHECK-NEXT: vmsr p0, r1332; CHECK-NEXT: vpst333; CHECK-NEXT: vidupt.u8 q0, r0, #8334; CHECK-NEXT: bx lr335entry:336 %0 = zext i16 %p to i32337 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)338 %2 = tail call { <16 x i8>, i32 } @llvm.arm.mve.vidup.predicated.v16i8.v16i1(<16 x i8> %inactive, i32 %a, i32 8, <16 x i1> %1)339 %3 = extractvalue { <16 x i8>, i32 } %2, 0340 ret <16 x i8> %3341}342 343define arm_aapcs_vfpcc <8 x i16> @test_vidupq_m_n_u16(<8 x i16> %inactive, i32 %a, i16 zeroext %p) {344; CHECK-LABEL: test_vidupq_m_n_u16:345; CHECK: @ %bb.0: @ %entry346; CHECK-NEXT: vmsr p0, r1347; CHECK-NEXT: vpst348; CHECK-NEXT: vidupt.u16 q0, r0, #8349; CHECK-NEXT: bx lr350entry:351 %0 = zext i16 %p to i32352 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)353 %2 = tail call { <8 x i16>, i32 } @llvm.arm.mve.vidup.predicated.v8i16.v8i1(<8 x i16> %inactive, i32 %a, i32 8, <8 x i1> %1)354 %3 = extractvalue { <8 x i16>, i32 } %2, 0355 ret <8 x i16> %3356}357 358define arm_aapcs_vfpcc <4 x i32> @test_vidupq_m_n_u32(<4 x i32> %inactive, i32 %a, i16 zeroext %p) {359; CHECK-LABEL: test_vidupq_m_n_u32:360; CHECK: @ %bb.0: @ %entry361; CHECK-NEXT: vmsr p0, r1362; CHECK-NEXT: vpst363; CHECK-NEXT: vidupt.u32 q0, r0, #2364; CHECK-NEXT: bx lr365entry:366 %0 = zext i16 %p to i32367 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)368 %2 = tail call { <4 x i32>, i32 } @llvm.arm.mve.vidup.predicated.v4i32.v4i1(<4 x i32> %inactive, i32 %a, i32 2, <4 x i1> %1)369 %3 = extractvalue { <4 x i32>, i32 } %2, 0370 ret <4 x i32> %3371}372 373define arm_aapcs_vfpcc <16 x i8> @test_vddupq_m_n_u8(<16 x i8> %inactive, i32 %a, i16 zeroext %p) {374; CHECK-LABEL: test_vddupq_m_n_u8:375; CHECK: @ %bb.0: @ %entry376; CHECK-NEXT: vmsr p0, r1377; CHECK-NEXT: vpst378; CHECK-NEXT: vddupt.u8 q0, r0, #8379; CHECK-NEXT: bx lr380entry:381 %0 = zext i16 %p to i32382 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)383 %2 = tail call { <16 x i8>, i32 } @llvm.arm.mve.vddup.predicated.v16i8.v16i1(<16 x i8> %inactive, i32 %a, i32 8, <16 x i1> %1)384 %3 = extractvalue { <16 x i8>, i32 } %2, 0385 ret <16 x i8> %3386}387 388define arm_aapcs_vfpcc <8 x i16> @test_vddupq_m_n_u16(<8 x i16> %inactive, i32 %a, i16 zeroext %p) {389; CHECK-LABEL: test_vddupq_m_n_u16:390; CHECK: @ %bb.0: @ %entry391; CHECK-NEXT: vmsr p0, r1392; CHECK-NEXT: vpst393; CHECK-NEXT: vddupt.u16 q0, r0, #2394; CHECK-NEXT: bx lr395entry:396 %0 = zext i16 %p to i32397 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)398 %2 = tail call { <8 x i16>, i32 } @llvm.arm.mve.vddup.predicated.v8i16.v8i1(<8 x i16> %inactive, i32 %a, i32 2, <8 x i1> %1)399 %3 = extractvalue { <8 x i16>, i32 } %2, 0400 ret <8 x i16> %3401}402 403define arm_aapcs_vfpcc <4 x i32> @test_vddupq_m_n_u32(<4 x i32> %inactive, i32 %a, i16 zeroext %p) {404; CHECK-LABEL: test_vddupq_m_n_u32:405; CHECK: @ %bb.0: @ %entry406; CHECK-NEXT: vmsr p0, r1407; CHECK-NEXT: vpst408; CHECK-NEXT: vddupt.u32 q0, r0, #8409; CHECK-NEXT: bx lr410entry:411 %0 = zext i16 %p to i32412 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)413 %2 = tail call { <4 x i32>, i32 } @llvm.arm.mve.vddup.predicated.v4i32.v4i1(<4 x i32> %inactive, i32 %a, i32 8, <4 x i1> %1)414 %3 = extractvalue { <4 x i32>, i32 } %2, 0415 ret <4 x i32> %3416}417 418define arm_aapcs_vfpcc <16 x i8> @test_viwdupq_m_n_u8(<16 x i8> %inactive, i32 %a, i32 %b, i16 zeroext %p) {419; CHECK-LABEL: test_viwdupq_m_n_u8:420; CHECK: @ %bb.0: @ %entry421; CHECK-NEXT: vmsr p0, r2422; CHECK-NEXT: vpst423; CHECK-NEXT: viwdupt.u8 q0, r0, r1, #8424; CHECK-NEXT: bx lr425entry:426 %0 = zext i16 %p to i32427 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)428 %2 = tail call { <16 x i8>, i32 } @llvm.arm.mve.viwdup.predicated.v16i8.v16i1(<16 x i8> %inactive, i32 %a, i32 %b, i32 8, <16 x i1> %1)429 %3 = extractvalue { <16 x i8>, i32 } %2, 0430 ret <16 x i8> %3431}432 433define arm_aapcs_vfpcc <8 x i16> @test_viwdupq_m_n_u16(<8 x i16> %inactive, i32 %a, i32 %b, i16 zeroext %p) {434; CHECK-LABEL: test_viwdupq_m_n_u16:435; CHECK: @ %bb.0: @ %entry436; CHECK-NEXT: vmsr p0, r2437; CHECK-NEXT: vpst438; CHECK-NEXT: viwdupt.u16 q0, r0, r1, #8439; CHECK-NEXT: bx lr440entry:441 %0 = zext i16 %p to i32442 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)443 %2 = tail call { <8 x i16>, i32 } @llvm.arm.mve.viwdup.predicated.v8i16.v8i1(<8 x i16> %inactive, i32 %a, i32 %b, i32 8, <8 x i1> %1)444 %3 = extractvalue { <8 x i16>, i32 } %2, 0445 ret <8 x i16> %3446}447 448define arm_aapcs_vfpcc <4 x i32> @test_viwdupq_m_n_u32(<4 x i32> %inactive, i32 %a, i32 %b, i16 zeroext %p) {449; CHECK-LABEL: test_viwdupq_m_n_u32:450; CHECK: @ %bb.0: @ %entry451; CHECK-NEXT: vmsr p0, r2452; CHECK-NEXT: vpst453; CHECK-NEXT: viwdupt.u32 q0, r0, r1, #4454; CHECK-NEXT: bx lr455entry:456 %0 = zext i16 %p to i32457 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)458 %2 = tail call { <4 x i32>, i32 } @llvm.arm.mve.viwdup.predicated.v4i32.v4i1(<4 x i32> %inactive, i32 %a, i32 %b, i32 4, <4 x i1> %1)459 %3 = extractvalue { <4 x i32>, i32 } %2, 0460 ret <4 x i32> %3461}462 463define arm_aapcs_vfpcc <16 x i8> @test_vdwdupq_m_n_u8(<16 x i8> %inactive, i32 %a, i32 %b, i16 zeroext %p) {464; CHECK-LABEL: test_vdwdupq_m_n_u8:465; CHECK: @ %bb.0: @ %entry466; CHECK-NEXT: vmsr p0, r2467; CHECK-NEXT: vpst468; CHECK-NEXT: vdwdupt.u8 q0, r0, r1, #1469; CHECK-NEXT: bx lr470entry:471 %0 = zext i16 %p to i32472 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)473 %2 = tail call { <16 x i8>, i32 } @llvm.arm.mve.vdwdup.predicated.v16i8.v16i1(<16 x i8> %inactive, i32 %a, i32 %b, i32 1, <16 x i1> %1)474 %3 = extractvalue { <16 x i8>, i32 } %2, 0475 ret <16 x i8> %3476}477 478define arm_aapcs_vfpcc <8 x i16> @test_vdwdupq_m_n_u16(<8 x i16> %inactive, i32 %a, i32 %b, i16 zeroext %p) {479; CHECK-LABEL: test_vdwdupq_m_n_u16:480; CHECK: @ %bb.0: @ %entry481; CHECK-NEXT: vmsr p0, r2482; CHECK-NEXT: vpst483; CHECK-NEXT: vdwdupt.u16 q0, r0, r1, #2484; CHECK-NEXT: bx lr485entry:486 %0 = zext i16 %p to i32487 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)488 %2 = tail call { <8 x i16>, i32 } @llvm.arm.mve.vdwdup.predicated.v8i16.v8i1(<8 x i16> %inactive, i32 %a, i32 %b, i32 2, <8 x i1> %1)489 %3 = extractvalue { <8 x i16>, i32 } %2, 0490 ret <8 x i16> %3491}492 493define arm_aapcs_vfpcc <4 x i32> @test_vdwdupq_m_n_u32(<4 x i32> %inactive, i32 %a, i32 %b, i16 zeroext %p) {494; CHECK-LABEL: test_vdwdupq_m_n_u32:495; CHECK: @ %bb.0: @ %entry496; CHECK-NEXT: vmsr p0, r2497; CHECK-NEXT: vpst498; CHECK-NEXT: vdwdupt.u32 q0, r0, r1, #4499; CHECK-NEXT: bx lr500entry:501 %0 = zext i16 %p to i32502 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)503 %2 = tail call { <4 x i32>, i32 } @llvm.arm.mve.vdwdup.predicated.v4i32.v4i1(<4 x i32> %inactive, i32 %a, i32 %b, i32 4, <4 x i1> %1)504 %3 = extractvalue { <4 x i32>, i32 } %2, 0505 ret <4 x i32> %3506}507 508define arm_aapcs_vfpcc <16 x i8> @test_vidupq_m_wb_u8(<16 x i8> %inactive, ptr nocapture %a, i16 zeroext %p) {509; CHECK-LABEL: test_vidupq_m_wb_u8:510; CHECK: @ %bb.0: @ %entry511; CHECK-NEXT: ldr r2, [r0]512; CHECK-NEXT: vmsr p0, r1513; CHECK-NEXT: vpst514; CHECK-NEXT: vidupt.u8 q0, r2, #8515; CHECK-NEXT: str r2, [r0]516; CHECK-NEXT: bx lr517entry:518 %0 = load i32, ptr %a, align 4519 %1 = zext i16 %p to i32520 %2 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)521 %3 = tail call { <16 x i8>, i32 } @llvm.arm.mve.vidup.predicated.v16i8.v16i1(<16 x i8> %inactive, i32 %0, i32 8, <16 x i1> %2)522 %4 = extractvalue { <16 x i8>, i32 } %3, 1523 store i32 %4, ptr %a, align 4524 %5 = extractvalue { <16 x i8>, i32 } %3, 0525 ret <16 x i8> %5526}527 528define arm_aapcs_vfpcc <8 x i16> @test_vidupq_m_wb_u16(<8 x i16> %inactive, ptr nocapture %a, i16 zeroext %p) {529; CHECK-LABEL: test_vidupq_m_wb_u16:530; CHECK: @ %bb.0: @ %entry531; CHECK-NEXT: ldr r2, [r0]532; CHECK-NEXT: vmsr p0, r1533; CHECK-NEXT: vpst534; CHECK-NEXT: vidupt.u16 q0, r2, #2535; CHECK-NEXT: str r2, [r0]536; CHECK-NEXT: bx lr537entry:538 %0 = load i32, ptr %a, align 4539 %1 = zext i16 %p to i32540 %2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)541 %3 = tail call { <8 x i16>, i32 } @llvm.arm.mve.vidup.predicated.v8i16.v8i1(<8 x i16> %inactive, i32 %0, i32 2, <8 x i1> %2)542 %4 = extractvalue { <8 x i16>, i32 } %3, 1543 store i32 %4, ptr %a, align 4544 %5 = extractvalue { <8 x i16>, i32 } %3, 0545 ret <8 x i16> %5546}547 548define arm_aapcs_vfpcc <4 x i32> @test_vidupq_m_wb_u32(<4 x i32> %inactive, ptr nocapture %a, i16 zeroext %p) {549; CHECK-LABEL: test_vidupq_m_wb_u32:550; CHECK: @ %bb.0: @ %entry551; CHECK-NEXT: ldr r2, [r0]552; CHECK-NEXT: vmsr p0, r1553; CHECK-NEXT: vpst554; CHECK-NEXT: vidupt.u32 q0, r2, #8555; CHECK-NEXT: str r2, [r0]556; CHECK-NEXT: bx lr557entry:558 %0 = load i32, ptr %a, align 4559 %1 = zext i16 %p to i32560 %2 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)561 %3 = tail call { <4 x i32>, i32 } @llvm.arm.mve.vidup.predicated.v4i32.v4i1(<4 x i32> %inactive, i32 %0, i32 8, <4 x i1> %2)562 %4 = extractvalue { <4 x i32>, i32 } %3, 1563 store i32 %4, ptr %a, align 4564 %5 = extractvalue { <4 x i32>, i32 } %3, 0565 ret <4 x i32> %5566}567 568define arm_aapcs_vfpcc <16 x i8> @test_vddupq_m_wb_u8(<16 x i8> %inactive, ptr nocapture %a, i16 zeroext %p) {569; CHECK-LABEL: test_vddupq_m_wb_u8:570; CHECK: @ %bb.0: @ %entry571; CHECK-NEXT: ldr r2, [r0]572; CHECK-NEXT: vmsr p0, r1573; CHECK-NEXT: vpst574; CHECK-NEXT: vddupt.u8 q0, r2, #1575; CHECK-NEXT: str r2, [r0]576; CHECK-NEXT: bx lr577entry:578 %0 = load i32, ptr %a, align 4579 %1 = zext i16 %p to i32580 %2 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)581 %3 = tail call { <16 x i8>, i32 } @llvm.arm.mve.vddup.predicated.v16i8.v16i1(<16 x i8> %inactive, i32 %0, i32 1, <16 x i1> %2)582 %4 = extractvalue { <16 x i8>, i32 } %3, 1583 store i32 %4, ptr %a, align 4584 %5 = extractvalue { <16 x i8>, i32 } %3, 0585 ret <16 x i8> %5586}587 588define arm_aapcs_vfpcc <8 x i16> @test_vddupq_m_wb_u16(<8 x i16> %inactive, ptr nocapture %a, i16 zeroext %p) {589; CHECK-LABEL: test_vddupq_m_wb_u16:590; CHECK: @ %bb.0: @ %entry591; CHECK-NEXT: ldr r2, [r0]592; CHECK-NEXT: vmsr p0, r1593; CHECK-NEXT: vpst594; CHECK-NEXT: vddupt.u16 q0, r2, #1595; CHECK-NEXT: str r2, [r0]596; CHECK-NEXT: bx lr597entry:598 %0 = load i32, ptr %a, align 4599 %1 = zext i16 %p to i32600 %2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)601 %3 = tail call { <8 x i16>, i32 } @llvm.arm.mve.vddup.predicated.v8i16.v8i1(<8 x i16> %inactive, i32 %0, i32 1, <8 x i1> %2)602 %4 = extractvalue { <8 x i16>, i32 } %3, 1603 store i32 %4, ptr %a, align 4604 %5 = extractvalue { <8 x i16>, i32 } %3, 0605 ret <8 x i16> %5606}607 608define arm_aapcs_vfpcc <4 x i32> @test_vddupq_m_wb_u32(<4 x i32> %inactive, ptr nocapture %a, i16 zeroext %p) {609; CHECK-LABEL: test_vddupq_m_wb_u32:610; CHECK: @ %bb.0: @ %entry611; CHECK-NEXT: ldr r2, [r0]612; CHECK-NEXT: vmsr p0, r1613; CHECK-NEXT: vpst614; CHECK-NEXT: vddupt.u32 q0, r2, #4615; CHECK-NEXT: str r2, [r0]616; CHECK-NEXT: bx lr617entry:618 %0 = load i32, ptr %a, align 4619 %1 = zext i16 %p to i32620 %2 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)621 %3 = tail call { <4 x i32>, i32 } @llvm.arm.mve.vddup.predicated.v4i32.v4i1(<4 x i32> %inactive, i32 %0, i32 4, <4 x i1> %2)622 %4 = extractvalue { <4 x i32>, i32 } %3, 1623 store i32 %4, ptr %a, align 4624 %5 = extractvalue { <4 x i32>, i32 } %3, 0625 ret <4 x i32> %5626}627 628define arm_aapcs_vfpcc <16 x i8> @test_viwdupq_m_wb_u8(<16 x i8> %inactive, ptr nocapture %a, i32 %b, i16 zeroext %p) {629; CHECK-LABEL: test_viwdupq_m_wb_u8:630; CHECK: @ %bb.0: @ %entry631; CHECK-NEXT: ldr.w r12, [r0]632; CHECK-NEXT: vmsr p0, r2633; CHECK-NEXT: vpst634; CHECK-NEXT: viwdupt.u8 q0, r12, r1, #8635; CHECK-NEXT: str.w r12, [r0]636; CHECK-NEXT: bx lr637entry:638 %0 = load i32, ptr %a, align 4639 %1 = zext i16 %p to i32640 %2 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)641 %3 = tail call { <16 x i8>, i32 } @llvm.arm.mve.viwdup.predicated.v16i8.v16i1(<16 x i8> %inactive, i32 %0, i32 %b, i32 8, <16 x i1> %2)642 %4 = extractvalue { <16 x i8>, i32 } %3, 1643 store i32 %4, ptr %a, align 4644 %5 = extractvalue { <16 x i8>, i32 } %3, 0645 ret <16 x i8> %5646}647 648define arm_aapcs_vfpcc <8 x i16> @test_viwdupq_m_wb_u16(<8 x i16> %inactive, ptr nocapture %a, i32 %b, i16 zeroext %p) {649; CHECK-LABEL: test_viwdupq_m_wb_u16:650; CHECK: @ %bb.0: @ %entry651; CHECK-NEXT: ldr.w r12, [r0]652; CHECK-NEXT: vmsr p0, r2653; CHECK-NEXT: vpst654; CHECK-NEXT: viwdupt.u16 q0, r12, r1, #8655; CHECK-NEXT: str.w r12, [r0]656; CHECK-NEXT: bx lr657entry:658 %0 = load i32, ptr %a, align 4659 %1 = zext i16 %p to i32660 %2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)661 %3 = tail call { <8 x i16>, i32 } @llvm.arm.mve.viwdup.predicated.v8i16.v8i1(<8 x i16> %inactive, i32 %0, i32 %b, i32 8, <8 x i1> %2)662 %4 = extractvalue { <8 x i16>, i32 } %3, 1663 store i32 %4, ptr %a, align 4664 %5 = extractvalue { <8 x i16>, i32 } %3, 0665 ret <8 x i16> %5666}667 668define arm_aapcs_vfpcc <4 x i32> @test_viwdupq_m_wb_u32(<4 x i32> %inactive, ptr nocapture %a, i32 %b, i16 zeroext %p) {669; CHECK-LABEL: test_viwdupq_m_wb_u32:670; CHECK: @ %bb.0: @ %entry671; CHECK-NEXT: ldr.w r12, [r0]672; CHECK-NEXT: vmsr p0, r2673; CHECK-NEXT: vpst674; CHECK-NEXT: viwdupt.u32 q0, r12, r1, #4675; CHECK-NEXT: str.w r12, [r0]676; CHECK-NEXT: bx lr677entry:678 %0 = load i32, ptr %a, align 4679 %1 = zext i16 %p to i32680 %2 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)681 %3 = tail call { <4 x i32>, i32 } @llvm.arm.mve.viwdup.predicated.v4i32.v4i1(<4 x i32> %inactive, i32 %0, i32 %b, i32 4, <4 x i1> %2)682 %4 = extractvalue { <4 x i32>, i32 } %3, 1683 store i32 %4, ptr %a, align 4684 %5 = extractvalue { <4 x i32>, i32 } %3, 0685 ret <4 x i32> %5686}687 688define arm_aapcs_vfpcc <16 x i8> @test_vdwdupq_m_wb_u8(<16 x i8> %inactive, ptr nocapture %a, i32 %b, i16 zeroext %p) {689; CHECK-LABEL: test_vdwdupq_m_wb_u8:690; CHECK: @ %bb.0: @ %entry691; CHECK-NEXT: ldr.w r12, [r0]692; CHECK-NEXT: vmsr p0, r2693; CHECK-NEXT: vpst694; CHECK-NEXT: vdwdupt.u8 q0, r12, r1, #1695; CHECK-NEXT: str.w r12, [r0]696; CHECK-NEXT: bx lr697entry:698 %0 = load i32, ptr %a, align 4699 %1 = zext i16 %p to i32700 %2 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)701 %3 = tail call { <16 x i8>, i32 } @llvm.arm.mve.vdwdup.predicated.v16i8.v16i1(<16 x i8> %inactive, i32 %0, i32 %b, i32 1, <16 x i1> %2)702 %4 = extractvalue { <16 x i8>, i32 } %3, 1703 store i32 %4, ptr %a, align 4704 %5 = extractvalue { <16 x i8>, i32 } %3, 0705 ret <16 x i8> %5706}707 708define arm_aapcs_vfpcc <8 x i16> @test_vdwdupq_m_wb_u16(<8 x i16> %inactive, ptr nocapture %a, i32 %b, i16 zeroext %p) {709; CHECK-LABEL: test_vdwdupq_m_wb_u16:710; CHECK: @ %bb.0: @ %entry711; CHECK-NEXT: ldr.w r12, [r0]712; CHECK-NEXT: vmsr p0, r2713; CHECK-NEXT: vpst714; CHECK-NEXT: vdwdupt.u16 q0, r12, r1, #4715; CHECK-NEXT: str.w r12, [r0]716; CHECK-NEXT: bx lr717entry:718 %0 = load i32, ptr %a, align 4719 %1 = zext i16 %p to i32720 %2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)721 %3 = tail call { <8 x i16>, i32 } @llvm.arm.mve.vdwdup.predicated.v8i16.v8i1(<8 x i16> %inactive, i32 %0, i32 %b, i32 4, <8 x i1> %2)722 %4 = extractvalue { <8 x i16>, i32 } %3, 1723 store i32 %4, ptr %a, align 4724 %5 = extractvalue { <8 x i16>, i32 } %3, 0725 ret <8 x i16> %5726}727 728define arm_aapcs_vfpcc <4 x i32> @test_vdwdupq_m_wb_u32(<4 x i32> %inactive, ptr nocapture %a, i32 %b, i16 zeroext %p) {729; CHECK-LABEL: test_vdwdupq_m_wb_u32:730; CHECK: @ %bb.0: @ %entry731; CHECK-NEXT: ldr.w r12, [r0]732; CHECK-NEXT: vmsr p0, r2733; CHECK-NEXT: vpst734; CHECK-NEXT: vdwdupt.u32 q0, r12, r1, #4735; CHECK-NEXT: str.w r12, [r0]736; CHECK-NEXT: bx lr737entry:738 %0 = load i32, ptr %a, align 4739 %1 = zext i16 %p to i32740 %2 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)741 %3 = tail call { <4 x i32>, i32 } @llvm.arm.mve.vdwdup.predicated.v4i32.v4i1(<4 x i32> %inactive, i32 %0, i32 %b, i32 4, <4 x i1> %2)742 %4 = extractvalue { <4 x i32>, i32 } %3, 1743 store i32 %4, ptr %a, align 4744 %5 = extractvalue { <4 x i32>, i32 } %3, 0745 ret <4 x i32> %5746}747 748declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)749declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)750declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)751 752declare { <16 x i8>, i32 } @llvm.arm.mve.vidup.v16i8(i32, i32)753declare { <8 x i16>, i32 } @llvm.arm.mve.vidup.v8i16(i32, i32)754declare { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32, i32)755declare { <16 x i8>, i32 } @llvm.arm.mve.vddup.v16i8(i32, i32)756declare { <8 x i16>, i32 } @llvm.arm.mve.vddup.v8i16(i32, i32)757declare { <4 x i32>, i32 } @llvm.arm.mve.vddup.v4i32(i32, i32)758declare { <16 x i8>, i32 } @llvm.arm.mve.viwdup.v16i8(i32, i32, i32)759declare { <8 x i16>, i32 } @llvm.arm.mve.viwdup.v8i16(i32, i32, i32)760declare { <4 x i32>, i32 } @llvm.arm.mve.viwdup.v4i32(i32, i32, i32)761declare { <16 x i8>, i32 } @llvm.arm.mve.vdwdup.v16i8(i32, i32, i32)762declare { <8 x i16>, i32 } @llvm.arm.mve.vdwdup.v8i16(i32, i32, i32)763declare { <4 x i32>, i32 } @llvm.arm.mve.vdwdup.v4i32(i32, i32, i32)764declare { <16 x i8>, i32 } @llvm.arm.mve.vidup.predicated.v16i8.v16i1(<16 x i8>, i32, i32, <16 x i1>)765declare { <8 x i16>, i32 } @llvm.arm.mve.vidup.predicated.v8i16.v8i1(<8 x i16>, i32, i32, <8 x i1>)766declare { <4 x i32>, i32 } @llvm.arm.mve.vidup.predicated.v4i32.v4i1(<4 x i32>, i32, i32, <4 x i1>)767declare { <16 x i8>, i32 } @llvm.arm.mve.vddup.predicated.v16i8.v16i1(<16 x i8>, i32, i32, <16 x i1>)768declare { <8 x i16>, i32 } @llvm.arm.mve.vddup.predicated.v8i16.v8i1(<8 x i16>, i32, i32, <8 x i1>)769declare { <4 x i32>, i32 } @llvm.arm.mve.vddup.predicated.v4i32.v4i1(<4 x i32>, i32, i32, <4 x i1>)770declare { <16 x i8>, i32 } @llvm.arm.mve.viwdup.predicated.v16i8.v16i1(<16 x i8>, i32, i32, i32, <16 x i1>)771declare { <8 x i16>, i32 } @llvm.arm.mve.viwdup.predicated.v8i16.v8i1(<8 x i16>, i32, i32, i32, <8 x i1>)772declare { <4 x i32>, i32 } @llvm.arm.mve.viwdup.predicated.v4i32.v4i1(<4 x i32>, i32, i32, i32, <4 x i1>)773declare { <16 x i8>, i32 } @llvm.arm.mve.vdwdup.predicated.v16i8.v16i1(<16 x i8>, i32, i32, i32, <16 x i1>)774declare { <8 x i16>, i32 } @llvm.arm.mve.vdwdup.predicated.v8i16.v8i1(<8 x i16>, i32, i32, i32, <8 x i1>)775declare { <4 x i32>, i32 } @llvm.arm.mve.vdwdup.predicated.v4i32.v4i1(<4 x i32>, i32, i32, i32, <4 x i1>)776