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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s3 4define arm_aapcs_vfpcc <8 x half> @test_vld1q_f16(ptr %base) {5; CHECK-LABEL: test_vld1q_f16:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vldrh.u16 q0, [r0]8; CHECK-NEXT: bx lr9entry:10 %0 = load <8 x half>, ptr %base, align 211 ret <8 x half> %012}13 14define arm_aapcs_vfpcc <4 x float> @test_vld1q_f32(ptr %base) {15; CHECK-LABEL: test_vld1q_f32:16; CHECK: @ %bb.0: @ %entry17; CHECK-NEXT: vldrw.u32 q0, [r0]18; CHECK-NEXT: bx lr19entry:20 %0 = load <4 x float>, ptr %base, align 421 ret <4 x float> %022}23 24define arm_aapcs_vfpcc <16 x i8> @test_vld1q_s8(ptr %base) {25; CHECK-LABEL: test_vld1q_s8:26; CHECK: @ %bb.0: @ %entry27; CHECK-NEXT: vldrb.u8 q0, [r0]28; CHECK-NEXT: bx lr29entry:30 %0 = load <16 x i8>, ptr %base, align 131 ret <16 x i8> %032}33 34define arm_aapcs_vfpcc <8 x i16> @test_vld1q_s16(ptr %base) {35; CHECK-LABEL: test_vld1q_s16:36; CHECK: @ %bb.0: @ %entry37; CHECK-NEXT: vldrh.u16 q0, [r0]38; CHECK-NEXT: bx lr39entry:40 %0 = load <8 x i16>, ptr %base, align 241 ret <8 x i16> %042}43 44define arm_aapcs_vfpcc <4 x i32> @test_vld1q_s32(ptr %base) {45; CHECK-LABEL: test_vld1q_s32:46; CHECK: @ %bb.0: @ %entry47; CHECK-NEXT: vldrw.u32 q0, [r0]48; CHECK-NEXT: bx lr49entry:50 %0 = load <4 x i32>, ptr %base, align 451 ret <4 x i32> %052}53 54define arm_aapcs_vfpcc <16 x i8> @test_vld1q_u8(ptr %base) {55; CHECK-LABEL: test_vld1q_u8:56; CHECK: @ %bb.0: @ %entry57; CHECK-NEXT: vldrb.u8 q0, [r0]58; CHECK-NEXT: bx lr59entry:60 %0 = load <16 x i8>, ptr %base, align 161 ret <16 x i8> %062}63 64define arm_aapcs_vfpcc <8 x i16> @test_vld1q_u16(ptr %base) {65; CHECK-LABEL: test_vld1q_u16:66; CHECK: @ %bb.0: @ %entry67; CHECK-NEXT: vldrh.u16 q0, [r0]68; CHECK-NEXT: bx lr69entry:70 %0 = load <8 x i16>, ptr %base, align 271 ret <8 x i16> %072}73 74define arm_aapcs_vfpcc <4 x i32> @test_vld1q_u32(ptr %base) {75; CHECK-LABEL: test_vld1q_u32:76; CHECK: @ %bb.0: @ %entry77; CHECK-NEXT: vldrw.u32 q0, [r0]78; CHECK-NEXT: bx lr79entry:80 %0 = load <4 x i32>, ptr %base, align 481 ret <4 x i32> %082}83 84define arm_aapcs_vfpcc <8 x half> @test_vld1q_z_f16(ptr %base, i16 zeroext %p) {85; CHECK-LABEL: test_vld1q_z_f16:86; CHECK: @ %bb.0: @ %entry87; CHECK-NEXT: vmsr p0, r188; CHECK-NEXT: vpst89; CHECK-NEXT: vldrht.u16 q0, [r0]90; CHECK-NEXT: bx lr91entry:92 %0 = zext i16 %p to i3293 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)94 %2 = call <8 x half> @llvm.masked.load.v8f16.p0(ptr %base, i32 2, <8 x i1> %1, <8 x half> zeroinitializer)95 ret <8 x half> %296}97 98declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)99 100declare <8 x half> @llvm.masked.load.v8f16.p0(ptr, i32 immarg, <8 x i1>, <8 x half>)101 102define arm_aapcs_vfpcc <4 x float> @test_vld1q_z_f32(ptr %base, i16 zeroext %p) {103; CHECK-LABEL: test_vld1q_z_f32:104; CHECK: @ %bb.0: @ %entry105; CHECK-NEXT: vmsr p0, r1106; CHECK-NEXT: vpst107; CHECK-NEXT: vldrwt.u32 q0, [r0]108; CHECK-NEXT: bx lr109entry:110 %0 = zext i16 %p to i32111 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)112 %2 = call <4 x float> @llvm.masked.load.v4f32.p0(ptr %base, i32 4, <4 x i1> %1, <4 x float> zeroinitializer)113 ret <4 x float> %2114}115 116declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)117 118declare <4 x float> @llvm.masked.load.v4f32.p0(ptr, i32 immarg, <4 x i1>, <4 x float>)119 120define arm_aapcs_vfpcc <16 x i8> @test_vld1q_z_s8(ptr %base, i16 zeroext %p) {121; CHECK-LABEL: test_vld1q_z_s8:122; CHECK: @ %bb.0: @ %entry123; CHECK-NEXT: vmsr p0, r1124; CHECK-NEXT: vpst125; CHECK-NEXT: vldrbt.u8 q0, [r0]126; CHECK-NEXT: bx lr127entry:128 %0 = zext i16 %p to i32129 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)130 %2 = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %base, i32 1, <16 x i1> %1, <16 x i8> zeroinitializer)131 ret <16 x i8> %2132}133 134declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)135 136declare <16 x i8> @llvm.masked.load.v16i8.p0(ptr, i32 immarg, <16 x i1>, <16 x i8>)137 138define arm_aapcs_vfpcc <8 x i16> @test_vld1q_z_s16(ptr %base, i16 zeroext %p) {139; CHECK-LABEL: test_vld1q_z_s16:140; CHECK: @ %bb.0: @ %entry141; CHECK-NEXT: vmsr p0, r1142; CHECK-NEXT: vpst143; CHECK-NEXT: vldrht.u16 q0, [r0]144; CHECK-NEXT: bx lr145entry:146 %0 = zext i16 %p to i32147 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)148 %2 = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %base, i32 2, <8 x i1> %1, <8 x i16> zeroinitializer)149 ret <8 x i16> %2150}151 152declare <8 x i16> @llvm.masked.load.v8i16.p0(ptr, i32 immarg, <8 x i1>, <8 x i16>)153 154define arm_aapcs_vfpcc <4 x i32> @test_vld1q_z_s32(ptr %base, i16 zeroext %p) {155; CHECK-LABEL: test_vld1q_z_s32:156; CHECK: @ %bb.0: @ %entry157; CHECK-NEXT: vmsr p0, r1158; CHECK-NEXT: vpst159; CHECK-NEXT: vldrwt.u32 q0, [r0]160; CHECK-NEXT: bx lr161entry:162 %0 = zext i16 %p to i32163 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)164 %2 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %base, i32 4, <4 x i1> %1, <4 x i32> zeroinitializer)165 ret <4 x i32> %2166}167 168declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>)169 170define arm_aapcs_vfpcc <16 x i8> @test_vld1q_z_u8(ptr %base, i16 zeroext %p) {171; CHECK-LABEL: test_vld1q_z_u8:172; CHECK: @ %bb.0: @ %entry173; CHECK-NEXT: vmsr p0, r1174; CHECK-NEXT: vpst175; CHECK-NEXT: vldrbt.u8 q0, [r0]176; CHECK-NEXT: bx lr177entry:178 %0 = zext i16 %p to i32179 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)180 %2 = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %base, i32 1, <16 x i1> %1, <16 x i8> zeroinitializer)181 ret <16 x i8> %2182}183 184define arm_aapcs_vfpcc <8 x i16> @test_vld1q_z_u16(ptr %base, i16 zeroext %p) {185; CHECK-LABEL: test_vld1q_z_u16:186; CHECK: @ %bb.0: @ %entry187; CHECK-NEXT: vmsr p0, r1188; CHECK-NEXT: vpst189; CHECK-NEXT: vldrht.u16 q0, [r0]190; CHECK-NEXT: bx lr191entry:192 %0 = zext i16 %p to i32193 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)194 %2 = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %base, i32 2, <8 x i1> %1, <8 x i16> zeroinitializer)195 ret <8 x i16> %2196}197 198define arm_aapcs_vfpcc <4 x i32> @test_vld1q_z_u32(ptr %base, i16 zeroext %p) {199; CHECK-LABEL: test_vld1q_z_u32:200; CHECK: @ %bb.0: @ %entry201; CHECK-NEXT: vmsr p0, r1202; CHECK-NEXT: vpst203; CHECK-NEXT: vldrwt.u32 q0, [r0]204; CHECK-NEXT: bx lr205entry:206 %0 = zext i16 %p to i32207 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)208 %2 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %base, i32 4, <4 x i1> %1, <4 x i32> zeroinitializer)209 ret <4 x i32> %2210}211 212define arm_aapcs_vfpcc <16 x i8> @test_vldrbq_s8(ptr %base) {213; CHECK-LABEL: test_vldrbq_s8:214; CHECK: @ %bb.0: @ %entry215; CHECK-NEXT: vldrb.u8 q0, [r0]216; CHECK-NEXT: bx lr217entry:218 %0 = load <16 x i8>, ptr %base, align 1219 ret <16 x i8> %0220}221 222define arm_aapcs_vfpcc <8 x i16> @test_vldrbq_s16(ptr %base) {223; CHECK-LABEL: test_vldrbq_s16:224; CHECK: @ %bb.0: @ %entry225; CHECK-NEXT: vldrb.s16 q0, [r0]226; CHECK-NEXT: bx lr227entry:228 %0 = load <8 x i8>, ptr %base, align 1229 %1 = sext <8 x i8> %0 to <8 x i16>230 ret <8 x i16> %1231}232 233define arm_aapcs_vfpcc <4 x i32> @test_vldrbq_s32(ptr %base) {234; CHECK-LABEL: test_vldrbq_s32:235; CHECK: @ %bb.0: @ %entry236; CHECK-NEXT: vldrb.s32 q0, [r0]237; CHECK-NEXT: bx lr238entry:239 %0 = load <4 x i8>, ptr %base, align 1240 %1 = sext <4 x i8> %0 to <4 x i32>241 ret <4 x i32> %1242}243 244define arm_aapcs_vfpcc <16 x i8> @test_vldrbq_u8(ptr %base) {245; CHECK-LABEL: test_vldrbq_u8:246; CHECK: @ %bb.0: @ %entry247; CHECK-NEXT: vldrb.u8 q0, [r0]248; CHECK-NEXT: bx lr249entry:250 %0 = load <16 x i8>, ptr %base, align 1251 ret <16 x i8> %0252}253 254define arm_aapcs_vfpcc <8 x i16> @test_vldrbq_u16(ptr %base) {255; CHECK-LABEL: test_vldrbq_u16:256; CHECK: @ %bb.0: @ %entry257; CHECK-NEXT: vldrb.u16 q0, [r0]258; CHECK-NEXT: bx lr259entry:260 %0 = load <8 x i8>, ptr %base, align 1261 %1 = zext <8 x i8> %0 to <8 x i16>262 ret <8 x i16> %1263}264 265define arm_aapcs_vfpcc <4 x i32> @test_vldrbq_u32(ptr %base) {266; CHECK-LABEL: test_vldrbq_u32:267; CHECK: @ %bb.0: @ %entry268; CHECK-NEXT: vldrb.u32 q0, [r0]269; CHECK-NEXT: bx lr270entry:271 %0 = load <4 x i8>, ptr %base, align 1272 %1 = zext <4 x i8> %0 to <4 x i32>273 ret <4 x i32> %1274}275 276define arm_aapcs_vfpcc <16 x i8> @test_vldrbq_z_s8(ptr %base, i16 zeroext %p) {277; CHECK-LABEL: test_vldrbq_z_s8:278; CHECK: @ %bb.0: @ %entry279; CHECK-NEXT: vmsr p0, r1280; CHECK-NEXT: vpst281; CHECK-NEXT: vldrbt.u8 q0, [r0]282; CHECK-NEXT: bx lr283entry:284 %0 = zext i16 %p to i32285 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)286 %2 = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %base, i32 1, <16 x i1> %1, <16 x i8> zeroinitializer)287 ret <16 x i8> %2288}289 290define arm_aapcs_vfpcc <8 x i16> @test_vldrbq_z_s16(ptr %base, i16 zeroext %p) {291; CHECK-LABEL: test_vldrbq_z_s16:292; CHECK: @ %bb.0: @ %entry293; CHECK-NEXT: vmsr p0, r1294; CHECK-NEXT: vpst295; CHECK-NEXT: vldrbt.s16 q0, [r0]296; CHECK-NEXT: bx lr297entry:298 %0 = zext i16 %p to i32299 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)300 %2 = call <8 x i8> @llvm.masked.load.v8i8.p0(ptr %base, i32 1, <8 x i1> %1, <8 x i8> zeroinitializer)301 %3 = sext <8 x i8> %2 to <8 x i16>302 ret <8 x i16> %3303}304 305declare <8 x i8> @llvm.masked.load.v8i8.p0(ptr, i32 immarg, <8 x i1>, <8 x i8>)306 307define arm_aapcs_vfpcc <4 x i32> @test_vldrbq_z_s32(ptr %base, i16 zeroext %p) {308; CHECK-LABEL: test_vldrbq_z_s32:309; CHECK: @ %bb.0: @ %entry310; CHECK-NEXT: vmsr p0, r1311; CHECK-NEXT: vpst312; CHECK-NEXT: vldrbt.s32 q0, [r0]313; CHECK-NEXT: bx lr314entry:315 %0 = zext i16 %p to i32316 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)317 %2 = call <4 x i8> @llvm.masked.load.v4i8.p0(ptr %base, i32 1, <4 x i1> %1, <4 x i8> zeroinitializer)318 %3 = sext <4 x i8> %2 to <4 x i32>319 ret <4 x i32> %3320}321 322declare <4 x i8> @llvm.masked.load.v4i8.p0(ptr, i32 immarg, <4 x i1>, <4 x i8>)323 324define arm_aapcs_vfpcc <16 x i8> @test_vldrbq_z_u8(ptr %base, i16 zeroext %p) {325; CHECK-LABEL: test_vldrbq_z_u8:326; CHECK: @ %bb.0: @ %entry327; CHECK-NEXT: vmsr p0, r1328; CHECK-NEXT: vpst329; CHECK-NEXT: vldrbt.u8 q0, [r0]330; CHECK-NEXT: bx lr331entry:332 %0 = zext i16 %p to i32333 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)334 %2 = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %base, i32 1, <16 x i1> %1, <16 x i8> zeroinitializer)335 ret <16 x i8> %2336}337 338define arm_aapcs_vfpcc <8 x i16> @test_vldrbq_z_u16(ptr %base, i16 zeroext %p) {339; CHECK-LABEL: test_vldrbq_z_u16:340; CHECK: @ %bb.0: @ %entry341; CHECK-NEXT: vmsr p0, r1342; CHECK-NEXT: vpst343; CHECK-NEXT: vldrbt.u16 q0, [r0]344; CHECK-NEXT: bx lr345entry:346 %0 = zext i16 %p to i32347 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)348 %2 = call <8 x i8> @llvm.masked.load.v8i8.p0(ptr %base, i32 1, <8 x i1> %1, <8 x i8> zeroinitializer)349 %3 = zext <8 x i8> %2 to <8 x i16>350 ret <8 x i16> %3351}352 353define arm_aapcs_vfpcc <4 x i32> @test_vldrbq_z_u32(ptr %base, i16 zeroext %p) {354; CHECK-LABEL: test_vldrbq_z_u32:355; CHECK: @ %bb.0: @ %entry356; CHECK-NEXT: vmsr p0, r1357; CHECK-NEXT: vpst358; CHECK-NEXT: vldrbt.u32 q0, [r0]359; CHECK-NEXT: bx lr360entry:361 %0 = zext i16 %p to i32362 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)363 %2 = call <4 x i8> @llvm.masked.load.v4i8.p0(ptr %base, i32 1, <4 x i1> %1, <4 x i8> zeroinitializer)364 %3 = zext <4 x i8> %2 to <4 x i32>365 ret <4 x i32> %3366}367 368define arm_aapcs_vfpcc <8 x half> @test_vldrhq_f16(ptr %base) {369; CHECK-LABEL: test_vldrhq_f16:370; CHECK: @ %bb.0: @ %entry371; CHECK-NEXT: vldrh.u16 q0, [r0]372; CHECK-NEXT: bx lr373entry:374 %0 = load <8 x half>, ptr %base, align 2375 ret <8 x half> %0376}377 378define arm_aapcs_vfpcc <8 x i16> @test_vldrhq_s16(ptr %base) {379; CHECK-LABEL: test_vldrhq_s16:380; CHECK: @ %bb.0: @ %entry381; CHECK-NEXT: vldrh.u16 q0, [r0]382; CHECK-NEXT: bx lr383entry:384 %0 = load <8 x i16>, ptr %base, align 2385 ret <8 x i16> %0386}387 388define arm_aapcs_vfpcc <4 x i32> @test_vldrhq_s32(ptr %base) {389; CHECK-LABEL: test_vldrhq_s32:390; CHECK: @ %bb.0: @ %entry391; CHECK-NEXT: vldrh.s32 q0, [r0]392; CHECK-NEXT: bx lr393entry:394 %0 = load <4 x i16>, ptr %base, align 2395 %1 = sext <4 x i16> %0 to <4 x i32>396 ret <4 x i32> %1397}398 399define arm_aapcs_vfpcc <8 x i16> @test_vldrhq_u16(ptr %base) {400; CHECK-LABEL: test_vldrhq_u16:401; CHECK: @ %bb.0: @ %entry402; CHECK-NEXT: vldrh.u16 q0, [r0]403; CHECK-NEXT: bx lr404entry:405 %0 = load <8 x i16>, ptr %base, align 2406 ret <8 x i16> %0407}408 409define arm_aapcs_vfpcc <4 x i32> @test_vldrhq_u32(ptr %base) {410; CHECK-LABEL: test_vldrhq_u32:411; CHECK: @ %bb.0: @ %entry412; CHECK-NEXT: vldrh.u32 q0, [r0]413; CHECK-NEXT: bx lr414entry:415 %0 = load <4 x i16>, ptr %base, align 2416 %1 = zext <4 x i16> %0 to <4 x i32>417 ret <4 x i32> %1418}419 420define arm_aapcs_vfpcc <8 x half> @test_vldrhq_z_f16(ptr %base, i16 zeroext %p) {421; CHECK-LABEL: test_vldrhq_z_f16:422; CHECK: @ %bb.0: @ %entry423; CHECK-NEXT: vmsr p0, r1424; CHECK-NEXT: vpst425; CHECK-NEXT: vldrht.u16 q0, [r0]426; CHECK-NEXT: bx lr427entry:428 %0 = zext i16 %p to i32429 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)430 %2 = call <8 x half> @llvm.masked.load.v8f16.p0(ptr %base, i32 2, <8 x i1> %1, <8 x half> zeroinitializer)431 ret <8 x half> %2432}433 434define arm_aapcs_vfpcc <8 x i16> @test_vldrhq_z_s16(ptr %base, i16 zeroext %p) {435; CHECK-LABEL: test_vldrhq_z_s16:436; CHECK: @ %bb.0: @ %entry437; CHECK-NEXT: vmsr p0, r1438; CHECK-NEXT: vpst439; CHECK-NEXT: vldrht.u16 q0, [r0]440; CHECK-NEXT: bx lr441entry:442 %0 = zext i16 %p to i32443 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)444 %2 = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %base, i32 2, <8 x i1> %1, <8 x i16> zeroinitializer)445 ret <8 x i16> %2446}447 448define arm_aapcs_vfpcc <4 x i32> @test_vldrhq_z_s32(ptr %base, i16 zeroext %p) {449; CHECK-LABEL: test_vldrhq_z_s32:450; CHECK: @ %bb.0: @ %entry451; CHECK-NEXT: vmsr p0, r1452; CHECK-NEXT: vpst453; CHECK-NEXT: vldrht.s32 q0, [r0]454; CHECK-NEXT: bx lr455entry:456 %0 = zext i16 %p to i32457 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)458 %2 = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %base, i32 2, <4 x i1> %1, <4 x i16> zeroinitializer)459 %3 = sext <4 x i16> %2 to <4 x i32>460 ret <4 x i32> %3461}462 463declare <4 x i16> @llvm.masked.load.v4i16.p0(ptr, i32 immarg, <4 x i1>, <4 x i16>)464 465define arm_aapcs_vfpcc <8 x i16> @test_vldrhq_z_u16(ptr %base, i16 zeroext %p) {466; CHECK-LABEL: test_vldrhq_z_u16:467; CHECK: @ %bb.0: @ %entry468; CHECK-NEXT: vmsr p0, r1469; CHECK-NEXT: vpst470; CHECK-NEXT: vldrht.u16 q0, [r0]471; CHECK-NEXT: bx lr472entry:473 %0 = zext i16 %p to i32474 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)475 %2 = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %base, i32 2, <8 x i1> %1, <8 x i16> zeroinitializer)476 ret <8 x i16> %2477}478 479define arm_aapcs_vfpcc <4 x i32> @test_vldrhq_z_u32(ptr %base, i16 zeroext %p) {480; CHECK-LABEL: test_vldrhq_z_u32:481; CHECK: @ %bb.0: @ %entry482; CHECK-NEXT: vmsr p0, r1483; CHECK-NEXT: vpst484; CHECK-NEXT: vldrht.u32 q0, [r0]485; CHECK-NEXT: bx lr486entry:487 %0 = zext i16 %p to i32488 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)489 %2 = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %base, i32 2, <4 x i1> %1, <4 x i16> zeroinitializer)490 %3 = zext <4 x i16> %2 to <4 x i32>491 ret <4 x i32> %3492}493 494define arm_aapcs_vfpcc <4 x float> @test_vldrwq_f32(ptr %base) {495; CHECK-LABEL: test_vldrwq_f32:496; CHECK: @ %bb.0: @ %entry497; CHECK-NEXT: vldrw.u32 q0, [r0]498; CHECK-NEXT: bx lr499entry:500 %0 = load <4 x float>, ptr %base, align 4501 ret <4 x float> %0502}503 504define arm_aapcs_vfpcc <4 x i32> @test_vldrwq_s32(ptr %base) {505; CHECK-LABEL: test_vldrwq_s32:506; CHECK: @ %bb.0: @ %entry507; CHECK-NEXT: vldrw.u32 q0, [r0]508; CHECK-NEXT: bx lr509entry:510 %0 = load <4 x i32>, ptr %base, align 4511 ret <4 x i32> %0512}513 514define arm_aapcs_vfpcc <4 x i32> @test_vldrwq_u32(ptr %base) {515; CHECK-LABEL: test_vldrwq_u32:516; CHECK: @ %bb.0: @ %entry517; CHECK-NEXT: vldrw.u32 q0, [r0]518; CHECK-NEXT: bx lr519entry:520 %0 = load <4 x i32>, ptr %base, align 4521 ret <4 x i32> %0522}523 524define arm_aapcs_vfpcc <4 x float> @test_vldrwq_z_f32(ptr %base, i16 zeroext %p) {525; CHECK-LABEL: test_vldrwq_z_f32:526; CHECK: @ %bb.0: @ %entry527; CHECK-NEXT: vmsr p0, r1528; CHECK-NEXT: vpst529; CHECK-NEXT: vldrwt.u32 q0, [r0]530; CHECK-NEXT: bx lr531entry:532 %0 = zext i16 %p to i32533 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)534 %2 = call <4 x float> @llvm.masked.load.v4f32.p0(ptr %base, i32 4, <4 x i1> %1, <4 x float> zeroinitializer)535 ret <4 x float> %2536}537 538define arm_aapcs_vfpcc <4 x i32> @test_vldrwq_z_s32(ptr %base, i16 zeroext %p) {539; CHECK-LABEL: test_vldrwq_z_s32:540; CHECK: @ %bb.0: @ %entry541; CHECK-NEXT: vmsr p0, r1542; CHECK-NEXT: vpst543; CHECK-NEXT: vldrwt.u32 q0, [r0]544; CHECK-NEXT: bx lr545entry:546 %0 = zext i16 %p to i32547 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)548 %2 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %base, i32 4, <4 x i1> %1, <4 x i32> zeroinitializer)549 ret <4 x i32> %2550}551 552define arm_aapcs_vfpcc <4 x i32> @test_vldrwq_z_u32(ptr %base, i16 zeroext %p) {553; CHECK-LABEL: test_vldrwq_z_u32:554; CHECK: @ %bb.0: @ %entry555; CHECK-NEXT: vmsr p0, r1556; CHECK-NEXT: vpst557; CHECK-NEXT: vldrwt.u32 q0, [r0]558; CHECK-NEXT: bx lr559entry:560 %0 = zext i16 %p to i32561 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)562 %2 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %base, i32 4, <4 x i1> %1, <4 x i32> zeroinitializer)563 ret <4 x i32> %2564}565 566define arm_aapcs_vfpcc void @test_vst1q_f16(ptr %base, <8 x half> %value) {567; CHECK-LABEL: test_vst1q_f16:568; CHECK: @ %bb.0: @ %entry569; CHECK-NEXT: vstrh.16 q0, [r0]570; CHECK-NEXT: bx lr571entry:572 store <8 x half> %value, ptr %base, align 2573 ret void574}575 576define arm_aapcs_vfpcc void @test_vst1q_f32(ptr %base, <4 x float> %value) {577; CHECK-LABEL: test_vst1q_f32:578; CHECK: @ %bb.0: @ %entry579; CHECK-NEXT: vstrw.32 q0, [r0]580; CHECK-NEXT: bx lr581entry:582 store <4 x float> %value, ptr %base, align 4583 ret void584}585 586define arm_aapcs_vfpcc void @test_vst1q_s8(ptr %base, <16 x i8> %value) {587; CHECK-LABEL: test_vst1q_s8:588; CHECK: @ %bb.0: @ %entry589; CHECK-NEXT: vstrb.8 q0, [r0]590; CHECK-NEXT: bx lr591entry:592 store <16 x i8> %value, ptr %base, align 1593 ret void594}595 596define arm_aapcs_vfpcc void @test_vst1q_s16(ptr %base, <8 x i16> %value) {597; CHECK-LABEL: test_vst1q_s16:598; CHECK: @ %bb.0: @ %entry599; CHECK-NEXT: vstrh.16 q0, [r0]600; CHECK-NEXT: bx lr601entry:602 store <8 x i16> %value, ptr %base, align 2603 ret void604}605 606define arm_aapcs_vfpcc void @test_vst1q_s32(ptr %base, <4 x i32> %value) {607; CHECK-LABEL: test_vst1q_s32:608; CHECK: @ %bb.0: @ %entry609; CHECK-NEXT: vstrw.32 q0, [r0]610; CHECK-NEXT: bx lr611entry:612 store <4 x i32> %value, ptr %base, align 4613 ret void614}615 616define arm_aapcs_vfpcc void @test_vst1q_u8(ptr %base, <16 x i8> %value) {617; CHECK-LABEL: test_vst1q_u8:618; CHECK: @ %bb.0: @ %entry619; CHECK-NEXT: vstrb.8 q0, [r0]620; CHECK-NEXT: bx lr621entry:622 store <16 x i8> %value, ptr %base, align 1623 ret void624}625 626define arm_aapcs_vfpcc void @test_vst1q_u16(ptr %base, <8 x i16> %value) {627; CHECK-LABEL: test_vst1q_u16:628; CHECK: @ %bb.0: @ %entry629; CHECK-NEXT: vstrh.16 q0, [r0]630; CHECK-NEXT: bx lr631entry:632 store <8 x i16> %value, ptr %base, align 2633 ret void634}635 636define arm_aapcs_vfpcc void @test_vst1q_u32(ptr %base, <4 x i32> %value) {637; CHECK-LABEL: test_vst1q_u32:638; CHECK: @ %bb.0: @ %entry639; CHECK-NEXT: vstrw.32 q0, [r0]640; CHECK-NEXT: bx lr641entry:642 store <4 x i32> %value, ptr %base, align 4643 ret void644}645 646define arm_aapcs_vfpcc void @test_vst1q_p_f16(ptr %base, <8 x half> %value, i16 zeroext %p) {647; CHECK-LABEL: test_vst1q_p_f16:648; CHECK: @ %bb.0: @ %entry649; CHECK-NEXT: vmsr p0, r1650; CHECK-NEXT: vpst651; CHECK-NEXT: vstrht.16 q0, [r0]652; CHECK-NEXT: bx lr653entry:654 %0 = zext i16 %p to i32655 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)656 call void @llvm.masked.store.v8f16.p0(<8 x half> %value, ptr %base, i32 2, <8 x i1> %1)657 ret void658}659 660declare void @llvm.masked.store.v8f16.p0(<8 x half>, ptr, i32 immarg, <8 x i1>)661 662define arm_aapcs_vfpcc void @test_vst1q_p_f32(ptr %base, <4 x float> %value, i16 zeroext %p) {663; CHECK-LABEL: test_vst1q_p_f32:664; CHECK: @ %bb.0: @ %entry665; CHECK-NEXT: vmsr p0, r1666; CHECK-NEXT: vpst667; CHECK-NEXT: vstrwt.32 q0, [r0]668; CHECK-NEXT: bx lr669entry:670 %0 = zext i16 %p to i32671 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)672 call void @llvm.masked.store.v4f32.p0(<4 x float> %value, ptr %base, i32 4, <4 x i1> %1)673 ret void674}675 676declare void @llvm.masked.store.v4f32.p0(<4 x float>, ptr, i32 immarg, <4 x i1>)677 678define arm_aapcs_vfpcc void @test_vst1q_p_s8(ptr %base, <16 x i8> %value, i16 zeroext %p) {679; CHECK-LABEL: test_vst1q_p_s8:680; CHECK: @ %bb.0: @ %entry681; CHECK-NEXT: vmsr p0, r1682; CHECK-NEXT: vpst683; CHECK-NEXT: vstrbt.8 q0, [r0]684; CHECK-NEXT: bx lr685entry:686 %0 = zext i16 %p to i32687 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)688 call void @llvm.masked.store.v16i8.p0(<16 x i8> %value, ptr %base, i32 1, <16 x i1> %1)689 ret void690}691 692declare void @llvm.masked.store.v16i8.p0(<16 x i8>, ptr, i32 immarg, <16 x i1>)693 694define arm_aapcs_vfpcc void @test_vst1q_p_s16(ptr %base, <8 x i16> %value, i16 zeroext %p) {695; CHECK-LABEL: test_vst1q_p_s16:696; CHECK: @ %bb.0: @ %entry697; CHECK-NEXT: vmsr p0, r1698; CHECK-NEXT: vpst699; CHECK-NEXT: vstrht.16 q0, [r0]700; CHECK-NEXT: bx lr701entry:702 %0 = zext i16 %p to i32703 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)704 call void @llvm.masked.store.v8i16.p0(<8 x i16> %value, ptr %base, i32 2, <8 x i1> %1)705 ret void706}707 708declare void @llvm.masked.store.v8i16.p0(<8 x i16>, ptr, i32 immarg, <8 x i1>)709 710define arm_aapcs_vfpcc void @test_vst1q_p_s32(ptr %base, <4 x i32> %value, i16 zeroext %p) {711; CHECK-LABEL: test_vst1q_p_s32:712; CHECK: @ %bb.0: @ %entry713; CHECK-NEXT: vmsr p0, r1714; CHECK-NEXT: vpst715; CHECK-NEXT: vstrwt.32 q0, [r0]716; CHECK-NEXT: bx lr717entry:718 %0 = zext i16 %p to i32719 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)720 call void @llvm.masked.store.v4i32.p0(<4 x i32> %value, ptr %base, i32 4, <4 x i1> %1)721 ret void722}723 724declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr, i32 immarg, <4 x i1>)725 726define arm_aapcs_vfpcc void @test_vst1q_p_u8(ptr %base, <16 x i8> %value, i16 zeroext %p) {727; CHECK-LABEL: test_vst1q_p_u8:728; CHECK: @ %bb.0: @ %entry729; CHECK-NEXT: vmsr p0, r1730; CHECK-NEXT: vpst731; CHECK-NEXT: vstrbt.8 q0, [r0]732; CHECK-NEXT: bx lr733entry:734 %0 = zext i16 %p to i32735 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)736 call void @llvm.masked.store.v16i8.p0(<16 x i8> %value, ptr %base, i32 1, <16 x i1> %1)737 ret void738}739 740define arm_aapcs_vfpcc void @test_vst1q_p_u16(ptr %base, <8 x i16> %value, i16 zeroext %p) {741; CHECK-LABEL: test_vst1q_p_u16:742; CHECK: @ %bb.0: @ %entry743; CHECK-NEXT: vmsr p0, r1744; CHECK-NEXT: vpst745; CHECK-NEXT: vstrht.16 q0, [r0]746; CHECK-NEXT: bx lr747entry:748 %0 = zext i16 %p to i32749 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)750 call void @llvm.masked.store.v8i16.p0(<8 x i16> %value, ptr %base, i32 2, <8 x i1> %1)751 ret void752}753 754define arm_aapcs_vfpcc void @test_vst1q_p_u32(ptr %base, <4 x i32> %value, i16 zeroext %p) {755; CHECK-LABEL: test_vst1q_p_u32:756; CHECK: @ %bb.0: @ %entry757; CHECK-NEXT: vmsr p0, r1758; CHECK-NEXT: vpst759; CHECK-NEXT: vstrwt.32 q0, [r0]760; CHECK-NEXT: bx lr761entry:762 %0 = zext i16 %p to i32763 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)764 call void @llvm.masked.store.v4i32.p0(<4 x i32> %value, ptr %base, i32 4, <4 x i1> %1)765 ret void766}767 768define arm_aapcs_vfpcc void @test_vstrbq_s8(ptr %base, <16 x i8> %value) {769; CHECK-LABEL: test_vstrbq_s8:770; CHECK: @ %bb.0: @ %entry771; CHECK-NEXT: vstrb.8 q0, [r0]772; CHECK-NEXT: bx lr773entry:774 store <16 x i8> %value, ptr %base, align 1775 ret void776}777 778define arm_aapcs_vfpcc void @test_vstrbq_s16(ptr %base, <8 x i16> %value) {779; CHECK-LABEL: test_vstrbq_s16:780; CHECK: @ %bb.0: @ %entry781; CHECK-NEXT: vstrb.16 q0, [r0]782; CHECK-NEXT: bx lr783entry:784 %0 = trunc <8 x i16> %value to <8 x i8>785 store <8 x i8> %0, ptr %base, align 1786 ret void787}788 789define arm_aapcs_vfpcc void @test_vstrbq_s32(ptr %base, <4 x i32> %value) {790; CHECK-LABEL: test_vstrbq_s32:791; CHECK: @ %bb.0: @ %entry792; CHECK-NEXT: vstrb.32 q0, [r0]793; CHECK-NEXT: bx lr794entry:795 %0 = trunc <4 x i32> %value to <4 x i8>796 store <4 x i8> %0, ptr %base, align 1797 ret void798}799 800define arm_aapcs_vfpcc void @test_vstrbq_u8(ptr %base, <16 x i8> %value) {801; CHECK-LABEL: test_vstrbq_u8:802; CHECK: @ %bb.0: @ %entry803; CHECK-NEXT: vstrb.8 q0, [r0]804; CHECK-NEXT: bx lr805entry:806 store <16 x i8> %value, ptr %base, align 1807 ret void808}809 810define arm_aapcs_vfpcc void @test_vstrbq_u16(ptr %base, <8 x i16> %value) {811; CHECK-LABEL: test_vstrbq_u16:812; CHECK: @ %bb.0: @ %entry813; CHECK-NEXT: vstrb.16 q0, [r0]814; CHECK-NEXT: bx lr815entry:816 %0 = trunc <8 x i16> %value to <8 x i8>817 store <8 x i8> %0, ptr %base, align 1818 ret void819}820 821define arm_aapcs_vfpcc void @test_vstrbq_u32(ptr %base, <4 x i32> %value) {822; CHECK-LABEL: test_vstrbq_u32:823; CHECK: @ %bb.0: @ %entry824; CHECK-NEXT: vstrb.32 q0, [r0]825; CHECK-NEXT: bx lr826entry:827 %0 = trunc <4 x i32> %value to <4 x i8>828 store <4 x i8> %0, ptr %base, align 1829 ret void830}831 832define arm_aapcs_vfpcc void @test_vstrbq_p_s8(ptr %base, <16 x i8> %value, i16 zeroext %p) {833; CHECK-LABEL: test_vstrbq_p_s8:834; CHECK: @ %bb.0: @ %entry835; CHECK-NEXT: vmsr p0, r1836; CHECK-NEXT: vpst837; CHECK-NEXT: vstrbt.8 q0, [r0]838; CHECK-NEXT: bx lr839entry:840 %0 = zext i16 %p to i32841 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)842 call void @llvm.masked.store.v16i8.p0(<16 x i8> %value, ptr %base, i32 1, <16 x i1> %1)843 ret void844}845 846define arm_aapcs_vfpcc void @test_vstrbq_p_s16(ptr %base, <8 x i16> %value, i16 zeroext %p) {847; CHECK-LABEL: test_vstrbq_p_s16:848; CHECK: @ %bb.0: @ %entry849; CHECK-NEXT: vmsr p0, r1850; CHECK-NEXT: vpst851; CHECK-NEXT: vstrbt.16 q0, [r0]852; CHECK-NEXT: bx lr853entry:854 %0 = trunc <8 x i16> %value to <8 x i8>855 %1 = zext i16 %p to i32856 %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)857 call void @llvm.masked.store.v8i8.p0(<8 x i8> %0, ptr %base, i32 1, <8 x i1> %2)858 ret void859}860 861declare void @llvm.masked.store.v8i8.p0(<8 x i8>, ptr, i32 immarg, <8 x i1>)862 863define arm_aapcs_vfpcc void @test_vstrbq_p_s32(ptr %base, <4 x i32> %value, i16 zeroext %p) {864; CHECK-LABEL: test_vstrbq_p_s32:865; CHECK: @ %bb.0: @ %entry866; CHECK-NEXT: vmsr p0, r1867; CHECK-NEXT: vpst868; CHECK-NEXT: vstrbt.32 q0, [r0]869; CHECK-NEXT: bx lr870entry:871 %0 = trunc <4 x i32> %value to <4 x i8>872 %1 = zext i16 %p to i32873 %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)874 call void @llvm.masked.store.v4i8.p0(<4 x i8> %0, ptr %base, i32 1, <4 x i1> %2)875 ret void876}877 878declare void @llvm.masked.store.v4i8.p0(<4 x i8>, ptr, i32 immarg, <4 x i1>)879 880define arm_aapcs_vfpcc void @test_vstrbq_p_u8(ptr %base, <16 x i8> %value, i16 zeroext %p) {881; CHECK-LABEL: test_vstrbq_p_u8:882; CHECK: @ %bb.0: @ %entry883; CHECK-NEXT: vmsr p0, r1884; CHECK-NEXT: vpst885; CHECK-NEXT: vstrbt.8 q0, [r0]886; CHECK-NEXT: bx lr887entry:888 %0 = zext i16 %p to i32889 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)890 call void @llvm.masked.store.v16i8.p0(<16 x i8> %value, ptr %base, i32 1, <16 x i1> %1)891 ret void892}893 894define arm_aapcs_vfpcc void @test_vstrbq_p_u16(ptr %base, <8 x i16> %value, i16 zeroext %p) {895; CHECK-LABEL: test_vstrbq_p_u16:896; CHECK: @ %bb.0: @ %entry897; CHECK-NEXT: vmsr p0, r1898; CHECK-NEXT: vpst899; CHECK-NEXT: vstrbt.16 q0, [r0]900; CHECK-NEXT: bx lr901entry:902 %0 = trunc <8 x i16> %value to <8 x i8>903 %1 = zext i16 %p to i32904 %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)905 call void @llvm.masked.store.v8i8.p0(<8 x i8> %0, ptr %base, i32 1, <8 x i1> %2)906 ret void907}908 909define arm_aapcs_vfpcc void @test_vstrbq_p_u32(ptr %base, <4 x i32> %value, i16 zeroext %p) {910; CHECK-LABEL: test_vstrbq_p_u32:911; CHECK: @ %bb.0: @ %entry912; CHECK-NEXT: vmsr p0, r1913; CHECK-NEXT: vpst914; CHECK-NEXT: vstrbt.32 q0, [r0]915; CHECK-NEXT: bx lr916entry:917 %0 = trunc <4 x i32> %value to <4 x i8>918 %1 = zext i16 %p to i32919 %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)920 call void @llvm.masked.store.v4i8.p0(<4 x i8> %0, ptr %base, i32 1, <4 x i1> %2)921 ret void922}923 924define arm_aapcs_vfpcc void @test_vstrhq_f16(ptr %base, <8 x half> %value) {925; CHECK-LABEL: test_vstrhq_f16:926; CHECK: @ %bb.0: @ %entry927; CHECK-NEXT: vstrh.16 q0, [r0]928; CHECK-NEXT: bx lr929entry:930 store <8 x half> %value, ptr %base, align 2931 ret void932}933 934define arm_aapcs_vfpcc void @test_vstrhq_s16(ptr %base, <8 x i16> %value) {935; CHECK-LABEL: test_vstrhq_s16:936; CHECK: @ %bb.0: @ %entry937; CHECK-NEXT: vstrh.16 q0, [r0]938; CHECK-NEXT: bx lr939entry:940 store <8 x i16> %value, ptr %base, align 2941 ret void942}943 944define arm_aapcs_vfpcc void @test_vstrhq_s32(ptr %base, <4 x i32> %value) {945; CHECK-LABEL: test_vstrhq_s32:946; CHECK: @ %bb.0: @ %entry947; CHECK-NEXT: vstrh.32 q0, [r0]948; CHECK-NEXT: bx lr949entry:950 %0 = trunc <4 x i32> %value to <4 x i16>951 store <4 x i16> %0, ptr %base, align 2952 ret void953}954 955define arm_aapcs_vfpcc void @test_vstrhq_u16(ptr %base, <8 x i16> %value) {956; CHECK-LABEL: test_vstrhq_u16:957; CHECK: @ %bb.0: @ %entry958; CHECK-NEXT: vstrh.16 q0, [r0]959; CHECK-NEXT: bx lr960entry:961 store <8 x i16> %value, ptr %base, align 2962 ret void963}964 965define arm_aapcs_vfpcc void @test_vstrhq_u32(ptr %base, <4 x i32> %value) {966; CHECK-LABEL: test_vstrhq_u32:967; CHECK: @ %bb.0: @ %entry968; CHECK-NEXT: vstrh.32 q0, [r0]969; CHECK-NEXT: bx lr970entry:971 %0 = trunc <4 x i32> %value to <4 x i16>972 store <4 x i16> %0, ptr %base, align 2973 ret void974}975 976define arm_aapcs_vfpcc void @test_vstrhq_p_f16(ptr %base, <8 x half> %value, i16 zeroext %p) {977; CHECK-LABEL: test_vstrhq_p_f16:978; CHECK: @ %bb.0: @ %entry979; CHECK-NEXT: vmsr p0, r1980; CHECK-NEXT: vpst981; CHECK-NEXT: vstrht.16 q0, [r0]982; CHECK-NEXT: bx lr983entry:984 %0 = zext i16 %p to i32985 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)986 call void @llvm.masked.store.v8f16.p0(<8 x half> %value, ptr %base, i32 2, <8 x i1> %1)987 ret void988}989 990define arm_aapcs_vfpcc void @test_vstrhq_p_s16(ptr %base, <8 x i16> %value, i16 zeroext %p) {991; CHECK-LABEL: test_vstrhq_p_s16:992; CHECK: @ %bb.0: @ %entry993; CHECK-NEXT: vmsr p0, r1994; CHECK-NEXT: vpst995; CHECK-NEXT: vstrht.16 q0, [r0]996; CHECK-NEXT: bx lr997entry:998 %0 = zext i16 %p to i32999 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)1000 call void @llvm.masked.store.v8i16.p0(<8 x i16> %value, ptr %base, i32 2, <8 x i1> %1)1001 ret void1002}1003 1004define arm_aapcs_vfpcc void @test_vstrhq_p_s32(ptr %base, <4 x i32> %value, i16 zeroext %p) {1005; CHECK-LABEL: test_vstrhq_p_s32:1006; CHECK: @ %bb.0: @ %entry1007; CHECK-NEXT: vmsr p0, r11008; CHECK-NEXT: vpst1009; CHECK-NEXT: vstrht.32 q0, [r0]1010; CHECK-NEXT: bx lr1011entry:1012 %0 = trunc <4 x i32> %value to <4 x i16>1013 %1 = zext i16 %p to i321014 %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)1015 call void @llvm.masked.store.v4i16.p0(<4 x i16> %0, ptr %base, i32 2, <4 x i1> %2)1016 ret void1017}1018 1019declare void @llvm.masked.store.v4i16.p0(<4 x i16>, ptr, i32 immarg, <4 x i1>)1020 1021define arm_aapcs_vfpcc void @test_vstrhq_p_u16(ptr %base, <8 x i16> %value, i16 zeroext %p) {1022; CHECK-LABEL: test_vstrhq_p_u16:1023; CHECK: @ %bb.0: @ %entry1024; CHECK-NEXT: vmsr p0, r11025; CHECK-NEXT: vpst1026; CHECK-NEXT: vstrht.16 q0, [r0]1027; CHECK-NEXT: bx lr1028entry:1029 %0 = zext i16 %p to i321030 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)1031 call void @llvm.masked.store.v8i16.p0(<8 x i16> %value, ptr %base, i32 2, <8 x i1> %1)1032 ret void1033}1034 1035define arm_aapcs_vfpcc void @test_vstrhq_p_u32(ptr %base, <4 x i32> %value, i16 zeroext %p) {1036; CHECK-LABEL: test_vstrhq_p_u32:1037; CHECK: @ %bb.0: @ %entry1038; CHECK-NEXT: vmsr p0, r11039; CHECK-NEXT: vpst1040; CHECK-NEXT: vstrht.32 q0, [r0]1041; CHECK-NEXT: bx lr1042entry:1043 %0 = trunc <4 x i32> %value to <4 x i16>1044 %1 = zext i16 %p to i321045 %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)1046 call void @llvm.masked.store.v4i16.p0(<4 x i16> %0, ptr %base, i32 2, <4 x i1> %2)1047 ret void1048}1049 1050define arm_aapcs_vfpcc void @test_vstrwq_f32(ptr %base, <4 x float> %value) {1051; CHECK-LABEL: test_vstrwq_f32:1052; CHECK: @ %bb.0: @ %entry1053; CHECK-NEXT: vstrw.32 q0, [r0]1054; CHECK-NEXT: bx lr1055entry:1056 store <4 x float> %value, ptr %base, align 41057 ret void1058}1059 1060define arm_aapcs_vfpcc void @test_vstrwq_s32(ptr %base, <4 x i32> %value) {1061; CHECK-LABEL: test_vstrwq_s32:1062; CHECK: @ %bb.0: @ %entry1063; CHECK-NEXT: vstrw.32 q0, [r0]1064; CHECK-NEXT: bx lr1065entry:1066 store <4 x i32> %value, ptr %base, align 41067 ret void1068}1069 1070define arm_aapcs_vfpcc void @test_vstrwq_u32(ptr %base, <4 x i32> %value) {1071; CHECK-LABEL: test_vstrwq_u32:1072; CHECK: @ %bb.0: @ %entry1073; CHECK-NEXT: vstrw.32 q0, [r0]1074; CHECK-NEXT: bx lr1075entry:1076 store <4 x i32> %value, ptr %base, align 41077 ret void1078}1079 1080define arm_aapcs_vfpcc void @test_vstrwq_p_f32(ptr %base, <4 x float> %value, i16 zeroext %p) {1081; CHECK-LABEL: test_vstrwq_p_f32:1082; CHECK: @ %bb.0: @ %entry1083; CHECK-NEXT: vmsr p0, r11084; CHECK-NEXT: vpst1085; CHECK-NEXT: vstrwt.32 q0, [r0]1086; CHECK-NEXT: bx lr1087entry:1088 %0 = zext i16 %p to i321089 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1090 call void @llvm.masked.store.v4f32.p0(<4 x float> %value, ptr %base, i32 4, <4 x i1> %1)1091 ret void1092}1093 1094define arm_aapcs_vfpcc void @test_vstrwq_p_s32(ptr %base, <4 x i32> %value, i16 zeroext %p) {1095; CHECK-LABEL: test_vstrwq_p_s32:1096; CHECK: @ %bb.0: @ %entry1097; CHECK-NEXT: vmsr p0, r11098; CHECK-NEXT: vpst1099; CHECK-NEXT: vstrwt.32 q0, [r0]1100; CHECK-NEXT: bx lr1101entry:1102 %0 = zext i16 %p to i321103 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1104 call void @llvm.masked.store.v4i32.p0(<4 x i32> %value, ptr %base, i32 4, <4 x i1> %1)1105 ret void1106}1107 1108define arm_aapcs_vfpcc void @test_vstrwq_p_u32(ptr %base, <4 x i32> %value, i16 zeroext %p) {1109; CHECK-LABEL: test_vstrwq_p_u32:1110; CHECK: @ %bb.0: @ %entry1111; CHECK-NEXT: vmsr p0, r11112; CHECK-NEXT: vpst1113; CHECK-NEXT: vstrwt.32 q0, [r0]1114; CHECK-NEXT: bx lr1115entry:1116 %0 = zext i16 %p to i321117 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1118 call void @llvm.masked.store.v4i32.p0(<4 x i32> %value, ptr %base, i32 4, <4 x i1> %1)1119 ret void1120}1121