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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s3 4define arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_s16(ptr %base, <8 x i16> %offset) {5; CHECK-LABEL: test_vldrbq_gather_offset_s16:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vldrb.s16 q1, [r0, q0]8; CHECK-NEXT: vmov q0, q19; CHECK-NEXT: bx lr10entry:11 %0 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.v8i16.p0.v8i16(ptr %base, <8 x i16> %offset, i32 8, i32 0, i32 0)12 ret <8 x i16> %013}14 15declare <8 x i16> @llvm.arm.mve.vldr.gather.offset.v8i16.p0.v8i16(ptr, <8 x i16>, i32, i32, i32)16 17define arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_s32(ptr %base, <4 x i32> %offset) {18; CHECK-LABEL: test_vldrbq_gather_offset_s32:19; CHECK: @ %bb.0: @ %entry20; CHECK-NEXT: vldrb.s32 q1, [r0, q0]21; CHECK-NEXT: vmov q0, q122; CHECK-NEXT: bx lr23entry:24 %0 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr %base, <4 x i32> %offset, i32 8, i32 0, i32 0)25 ret <4 x i32> %026}27 28declare <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr, <4 x i32>, i32, i32, i32)29 30define arm_aapcs_vfpcc <16 x i8> @test_vldrbq_gather_offset_s8(ptr %base, <16 x i8> %offset) {31; CHECK-LABEL: test_vldrbq_gather_offset_s8:32; CHECK: @ %bb.0: @ %entry33; CHECK-NEXT: vldrb.u8 q1, [r0, q0]34; CHECK-NEXT: vmov q0, q135; CHECK-NEXT: bx lr36entry:37 %0 = call <16 x i8> @llvm.arm.mve.vldr.gather.offset.v16i8.p0.v16i8(ptr %base, <16 x i8> %offset, i32 8, i32 0, i32 0)38 ret <16 x i8> %039}40 41declare <16 x i8> @llvm.arm.mve.vldr.gather.offset.v16i8.p0.v16i8(ptr, <16 x i8>, i32, i32, i32)42 43define arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_u16(ptr %base, <8 x i16> %offset) {44; CHECK-LABEL: test_vldrbq_gather_offset_u16:45; CHECK: @ %bb.0: @ %entry46; CHECK-NEXT: vldrb.u16 q1, [r0, q0]47; CHECK-NEXT: vmov q0, q148; CHECK-NEXT: bx lr49entry:50 %0 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.v8i16.p0.v8i16(ptr %base, <8 x i16> %offset, i32 8, i32 0, i32 1)51 ret <8 x i16> %052}53 54define arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_u32(ptr %base, <4 x i32> %offset) {55; CHECK-LABEL: test_vldrbq_gather_offset_u32:56; CHECK: @ %bb.0: @ %entry57; CHECK-NEXT: vldrb.u32 q1, [r0, q0]58; CHECK-NEXT: vmov q0, q159; CHECK-NEXT: bx lr60entry:61 %0 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr %base, <4 x i32> %offset, i32 8, i32 0, i32 1)62 ret <4 x i32> %063}64 65define arm_aapcs_vfpcc <16 x i8> @test_vldrbq_gather_offset_u8(ptr %base, <16 x i8> %offset) {66; CHECK-LABEL: test_vldrbq_gather_offset_u8:67; CHECK: @ %bb.0: @ %entry68; CHECK-NEXT: vldrb.u8 q1, [r0, q0]69; CHECK-NEXT: vmov q0, q170; CHECK-NEXT: bx lr71entry:72 %0 = call <16 x i8> @llvm.arm.mve.vldr.gather.offset.v16i8.p0.v16i8(ptr %base, <16 x i8> %offset, i32 8, i32 0, i32 1)73 ret <16 x i8> %074}75 76define arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_z_s16(ptr %base, <8 x i16> %offset, i16 zeroext %p) {77; CHECK-LABEL: test_vldrbq_gather_offset_z_s16:78; CHECK: @ %bb.0: @ %entry79; CHECK-NEXT: vmsr p0, r180; CHECK-NEXT: vpst81; CHECK-NEXT: vldrbt.s16 q1, [r0, q0]82; CHECK-NEXT: vmov q0, q183; CHECK-NEXT: bx lr84entry:85 %0 = zext i16 %p to i3286 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)87 %2 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.predicated.v8i16.p0.v8i16.v8i1(ptr %base, <8 x i16> %offset, i32 8, i32 0, i32 0, <8 x i1> %1)88 ret <8 x i16> %289}90 91declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)92 93declare <8 x i16> @llvm.arm.mve.vldr.gather.offset.predicated.v8i16.p0.v8i16.v8i1(ptr, <8 x i16>, i32, i32, i32, <8 x i1>)94 95define arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_z_s32(ptr %base, <4 x i32> %offset, i16 zeroext %p) {96; CHECK-LABEL: test_vldrbq_gather_offset_z_s32:97; CHECK: @ %bb.0: @ %entry98; CHECK-NEXT: vmsr p0, r199; CHECK-NEXT: vpst100; CHECK-NEXT: vldrbt.s32 q1, [r0, q0]101; CHECK-NEXT: vmov q0, q1102; CHECK-NEXT: bx lr103entry:104 %0 = zext i16 %p to i32105 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)106 %2 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0.v4i32.v4i1(ptr %base, <4 x i32> %offset, i32 8, i32 0, i32 0, <4 x i1> %1)107 ret <4 x i32> %2108}109 110declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)111 112declare <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0.v4i32.v4i1(ptr, <4 x i32>, i32, i32, i32, <4 x i1>)113 114define arm_aapcs_vfpcc <16 x i8> @test_vldrbq_gather_offset_z_s8(ptr %base, <16 x i8> %offset, i16 zeroext %p) {115; CHECK-LABEL: test_vldrbq_gather_offset_z_s8:116; CHECK: @ %bb.0: @ %entry117; CHECK-NEXT: vmsr p0, r1118; CHECK-NEXT: vpst119; CHECK-NEXT: vldrbt.u8 q1, [r0, q0]120; CHECK-NEXT: vmov q0, q1121; CHECK-NEXT: bx lr122entry:123 %0 = zext i16 %p to i32124 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)125 %2 = call <16 x i8> @llvm.arm.mve.vldr.gather.offset.predicated.v16i8.p0.v16i8.v16i1(ptr %base, <16 x i8> %offset, i32 8, i32 0, i32 0, <16 x i1> %1)126 ret <16 x i8> %2127}128 129declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)130 131declare <16 x i8> @llvm.arm.mve.vldr.gather.offset.predicated.v16i8.p0.v16i8.v16i1(ptr, <16 x i8>, i32, i32, i32, <16 x i1>)132 133define arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_z_u16(ptr %base, <8 x i16> %offset, i16 zeroext %p) {134; CHECK-LABEL: test_vldrbq_gather_offset_z_u16:135; CHECK: @ %bb.0: @ %entry136; CHECK-NEXT: vmsr p0, r1137; CHECK-NEXT: vpst138; CHECK-NEXT: vldrbt.u16 q1, [r0, q0]139; CHECK-NEXT: vmov q0, q1140; CHECK-NEXT: bx lr141entry:142 %0 = zext i16 %p to i32143 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)144 %2 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.predicated.v8i16.p0.v8i16.v8i1(ptr %base, <8 x i16> %offset, i32 8, i32 0, i32 1, <8 x i1> %1)145 ret <8 x i16> %2146}147 148define arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_z_u32(ptr %base, <4 x i32> %offset, i16 zeroext %p) {149; CHECK-LABEL: test_vldrbq_gather_offset_z_u32:150; CHECK: @ %bb.0: @ %entry151; CHECK-NEXT: vmsr p0, r1152; CHECK-NEXT: vpst153; CHECK-NEXT: vldrbt.u32 q1, [r0, q0]154; CHECK-NEXT: vmov q0, q1155; CHECK-NEXT: bx lr156entry:157 %0 = zext i16 %p to i32158 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)159 %2 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0.v4i32.v4i1(ptr %base, <4 x i32> %offset, i32 8, i32 0, i32 1, <4 x i1> %1)160 ret <4 x i32> %2161}162 163define arm_aapcs_vfpcc <16 x i8> @test_vldrbq_gather_offset_z_u8(ptr %base, <16 x i8> %offset, i16 zeroext %p) {164; CHECK-LABEL: test_vldrbq_gather_offset_z_u8:165; CHECK: @ %bb.0: @ %entry166; CHECK-NEXT: vmsr p0, r1167; CHECK-NEXT: vpst168; CHECK-NEXT: vldrbt.u8 q1, [r0, q0]169; CHECK-NEXT: vmov q0, q1170; CHECK-NEXT: bx lr171entry:172 %0 = zext i16 %p to i32173 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)174 %2 = call <16 x i8> @llvm.arm.mve.vldr.gather.offset.predicated.v16i8.p0.v16i8.v16i1(ptr %base, <16 x i8> %offset, i32 8, i32 0, i32 1, <16 x i1> %1)175 ret <16 x i8> %2176}177 178define arm_aapcs_vfpcc <2 x i64> @test_vldrdq_gather_base_s64(<2 x i64> %addr) {179; CHECK-LABEL: test_vldrdq_gather_base_s64:180; CHECK: @ %bb.0: @ %entry181; CHECK-NEXT: vldrd.u64 q1, [q0, #616]182; CHECK-NEXT: vmov q0, q1183; CHECK-NEXT: bx lr184entry:185 %0 = call <2 x i64> @llvm.arm.mve.vldr.gather.base.v2i64.v2i64(<2 x i64> %addr, i32 616)186 ret <2 x i64> %0187}188 189declare <2 x i64> @llvm.arm.mve.vldr.gather.base.v2i64.v2i64(<2 x i64>, i32)190 191define arm_aapcs_vfpcc <2 x i64> @test_vldrdq_gather_base_u64(<2 x i64> %addr) {192; CHECK-LABEL: test_vldrdq_gather_base_u64:193; CHECK: @ %bb.0: @ %entry194; CHECK-NEXT: vldrd.u64 q1, [q0, #-336]195; CHECK-NEXT: vmov q0, q1196; CHECK-NEXT: bx lr197entry:198 %0 = call <2 x i64> @llvm.arm.mve.vldr.gather.base.v2i64.v2i64(<2 x i64> %addr, i32 -336)199 ret <2 x i64> %0200}201 202define arm_aapcs_vfpcc <2 x i64> @test_vldrdq_gather_base_wb_s64(ptr %addr) {203; CHECK-LABEL: test_vldrdq_gather_base_wb_s64:204; CHECK: @ %bb.0: @ %entry205; CHECK-NEXT: vldrw.u32 q1, [r0]206; CHECK-NEXT: vldrd.u64 q0, [q1, #576]!207; CHECK-NEXT: vstrw.32 q1, [r0]208; CHECK-NEXT: bx lr209entry:210 %0 = load <2 x i64>, ptr %addr, align 8211 %1 = call { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.v2i64.v2i64(<2 x i64> %0, i32 576)212 %2 = extractvalue { <2 x i64>, <2 x i64> } %1, 1213 store <2 x i64> %2, ptr %addr, align 8214 %3 = extractvalue { <2 x i64>, <2 x i64> } %1, 0215 ret <2 x i64> %3216}217 218declare { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.v2i64.v2i64(<2 x i64>, i32)219 220define arm_aapcs_vfpcc <2 x i64> @test_vldrdq_gather_base_wb_u64(ptr %addr) {221; CHECK-LABEL: test_vldrdq_gather_base_wb_u64:222; CHECK: @ %bb.0: @ %entry223; CHECK-NEXT: vldrw.u32 q1, [r0]224; CHECK-NEXT: vldrd.u64 q0, [q1, #-328]!225; CHECK-NEXT: vstrw.32 q1, [r0]226; CHECK-NEXT: bx lr227entry:228 %0 = load <2 x i64>, ptr %addr, align 8229 %1 = call { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.v2i64.v2i64(<2 x i64> %0, i32 -328)230 %2 = extractvalue { <2 x i64>, <2 x i64> } %1, 1231 store <2 x i64> %2, ptr %addr, align 8232 %3 = extractvalue { <2 x i64>, <2 x i64> } %1, 0233 ret <2 x i64> %3234}235 236define arm_aapcs_vfpcc <2 x i64> @test_vldrdq_gather_base_wb_z_s64(ptr %addr, i16 zeroext %p) {237; CHECK-LABEL: test_vldrdq_gather_base_wb_z_s64:238; CHECK: @ %bb.0: @ %entry239; CHECK-NEXT: vmsr p0, r1240; CHECK-NEXT: vldrw.u32 q1, [r0]241; CHECK-NEXT: vpst242; CHECK-NEXT: vldrdt.u64 q0, [q1, #664]!243; CHECK-NEXT: vstrw.32 q1, [r0]244; CHECK-NEXT: bx lr245entry:246 %0 = load <2 x i64>, ptr %addr, align 8247 %1 = zext i16 %p to i32248 %2 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %1)249 %3 = call { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v2i64.v2i64.v2i1(<2 x i64> %0, i32 664, <2 x i1> %2)250 %4 = extractvalue { <2 x i64>, <2 x i64> } %3, 1251 store <2 x i64> %4, ptr %addr, align 8252 %5 = extractvalue { <2 x i64>, <2 x i64> } %3, 0253 ret <2 x i64> %5254}255 256declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32)257declare { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v2i64.v2i64.v2i1(<2 x i64>, i32, <2 x i1>)258 259define arm_aapcs_vfpcc <2 x i64> @test_vldrdq_gather_base_wb_z_u64(ptr %addr, i16 zeroext %p) {260; CHECK-LABEL: test_vldrdq_gather_base_wb_z_u64:261; CHECK: @ %bb.0: @ %entry262; CHECK-NEXT: vmsr p0, r1263; CHECK-NEXT: vldrw.u32 q1, [r0]264; CHECK-NEXT: vpst265; CHECK-NEXT: vldrdt.u64 q0, [q1, #656]!266; CHECK-NEXT: vstrw.32 q1, [r0]267; CHECK-NEXT: bx lr268entry:269 %0 = load <2 x i64>, ptr %addr, align 8270 %1 = zext i16 %p to i32271 %2 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %1)272 %3 = call { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v2i64.v2i64.v2i1(<2 x i64> %0, i32 656, <2 x i1> %2)273 %4 = extractvalue { <2 x i64>, <2 x i64> } %3, 1274 store <2 x i64> %4, ptr %addr, align 8275 %5 = extractvalue { <2 x i64>, <2 x i64> } %3, 0276 ret <2 x i64> %5277}278 279define arm_aapcs_vfpcc <2 x i64> @test_vldrdq_gather_base_z_s64(<2 x i64> %addr, i16 zeroext %p) {280; CHECK-LABEL: test_vldrdq_gather_base_z_s64:281; CHECK: @ %bb.0: @ %entry282; CHECK-NEXT: vmsr p0, r0283; CHECK-NEXT: vpst284; CHECK-NEXT: vldrdt.u64 q1, [q0, #888]285; CHECK-NEXT: vmov q0, q1286; CHECK-NEXT: bx lr287entry:288 %0 = zext i16 %p to i32289 %1 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %0)290 %2 = call <2 x i64> @llvm.arm.mve.vldr.gather.base.predicated.v2i64.v2i64.v2i1(<2 x i64> %addr, i32 888, <2 x i1> %1)291 ret <2 x i64> %2292}293 294declare <2 x i64> @llvm.arm.mve.vldr.gather.base.predicated.v2i64.v2i64.v2i1(<2 x i64>, i32, <2 x i1>)295 296define arm_aapcs_vfpcc <2 x i64> @test_vldrdq_gather_base_z_u64(<2 x i64> %addr, i16 zeroext %p) {297; CHECK-LABEL: test_vldrdq_gather_base_z_u64:298; CHECK: @ %bb.0: @ %entry299; CHECK-NEXT: vmsr p0, r0300; CHECK-NEXT: vpst301; CHECK-NEXT: vldrdt.u64 q1, [q0, #-1000]302; CHECK-NEXT: vmov q0, q1303; CHECK-NEXT: bx lr304entry:305 %0 = zext i16 %p to i32306 %1 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %0)307 %2 = call <2 x i64> @llvm.arm.mve.vldr.gather.base.predicated.v2i64.v2i64.v2i1(<2 x i64> %addr, i32 -1000, <2 x i1> %1)308 ret <2 x i64> %2309}310 311define arm_aapcs_vfpcc <2 x i64> @test_vldrdq_gather_offset_s64(ptr %base, <2 x i64> %offset) {312; CHECK-LABEL: test_vldrdq_gather_offset_s64:313; CHECK: @ %bb.0: @ %entry314; CHECK-NEXT: vldrd.u64 q1, [r0, q0]315; CHECK-NEXT: vmov q0, q1316; CHECK-NEXT: bx lr317entry:318 %0 = call <2 x i64> @llvm.arm.mve.vldr.gather.offset.v2i64.p0.v2i64(ptr %base, <2 x i64> %offset, i32 64, i32 0, i32 0)319 ret <2 x i64> %0320}321 322declare <2 x i64> @llvm.arm.mve.vldr.gather.offset.v2i64.p0.v2i64(ptr, <2 x i64>, i32, i32, i32)323 324define arm_aapcs_vfpcc <2 x i64> @test_vldrdq_gather_offset_u64(ptr %base, <2 x i64> %offset) {325; CHECK-LABEL: test_vldrdq_gather_offset_u64:326; CHECK: @ %bb.0: @ %entry327; CHECK-NEXT: vldrd.u64 q1, [r0, q0]328; CHECK-NEXT: vmov q0, q1329; CHECK-NEXT: bx lr330entry:331 %0 = call <2 x i64> @llvm.arm.mve.vldr.gather.offset.v2i64.p0.v2i64(ptr %base, <2 x i64> %offset, i32 64, i32 0, i32 1)332 ret <2 x i64> %0333}334 335define arm_aapcs_vfpcc <2 x i64> @test_vldrdq_gather_offset_z_s64(ptr %base, <2 x i64> %offset, i16 zeroext %p) {336; CHECK-LABEL: test_vldrdq_gather_offset_z_s64:337; CHECK: @ %bb.0: @ %entry338; CHECK-NEXT: vmsr p0, r1339; CHECK-NEXT: vpst340; CHECK-NEXT: vldrdt.u64 q1, [r0, q0]341; CHECK-NEXT: vmov q0, q1342; CHECK-NEXT: bx lr343entry:344 %0 = zext i16 %p to i32345 %1 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %0)346 %2 = call <2 x i64> @llvm.arm.mve.vldr.gather.offset.predicated.v2i64.p0.v2i64.v2i1(ptr %base, <2 x i64> %offset, i32 64, i32 0, i32 0, <2 x i1> %1)347 ret <2 x i64> %2348}349 350declare <2 x i64> @llvm.arm.mve.vldr.gather.offset.predicated.v2i64.p0.v2i64.v2i1(ptr, <2 x i64>, i32, i32, i32, <2 x i1>)351 352define arm_aapcs_vfpcc <2 x i64> @test_vldrdq_gather_offset_z_u64(ptr %base, <2 x i64> %offset, i16 zeroext %p) {353; CHECK-LABEL: test_vldrdq_gather_offset_z_u64:354; CHECK: @ %bb.0: @ %entry355; CHECK-NEXT: vmsr p0, r1356; CHECK-NEXT: vpst357; CHECK-NEXT: vldrdt.u64 q1, [r0, q0]358; CHECK-NEXT: vmov q0, q1359; CHECK-NEXT: bx lr360entry:361 %0 = zext i16 %p to i32362 %1 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %0)363 %2 = call <2 x i64> @llvm.arm.mve.vldr.gather.offset.predicated.v2i64.p0.v2i64.v2i1(ptr %base, <2 x i64> %offset, i32 64, i32 0, i32 1, <2 x i1> %1)364 ret <2 x i64> %2365}366 367define arm_aapcs_vfpcc <2 x i64> @test_vldrdq_gather_shifted_offset_s64(ptr %base, <2 x i64> %offset) {368; CHECK-LABEL: test_vldrdq_gather_shifted_offset_s64:369; CHECK: @ %bb.0: @ %entry370; CHECK-NEXT: vldrd.u64 q1, [r0, q0, uxtw #3]371; CHECK-NEXT: vmov q0, q1372; CHECK-NEXT: bx lr373entry:374 %0 = call <2 x i64> @llvm.arm.mve.vldr.gather.offset.v2i64.p0.v2i64(ptr %base, <2 x i64> %offset, i32 64, i32 3, i32 0)375 ret <2 x i64> %0376}377 378define arm_aapcs_vfpcc <2 x i64> @test_vldrdq_gather_shifted_offset_u64(ptr %base, <2 x i64> %offset) {379; CHECK-LABEL: test_vldrdq_gather_shifted_offset_u64:380; CHECK: @ %bb.0: @ %entry381; CHECK-NEXT: vldrd.u64 q1, [r0, q0, uxtw #3]382; CHECK-NEXT: vmov q0, q1383; CHECK-NEXT: bx lr384entry:385 %0 = call <2 x i64> @llvm.arm.mve.vldr.gather.offset.v2i64.p0.v2i64(ptr %base, <2 x i64> %offset, i32 64, i32 3, i32 1)386 ret <2 x i64> %0387}388 389define arm_aapcs_vfpcc <2 x i64> @test_vldrdq_gather_shifted_offset_z_s64(ptr %base, <2 x i64> %offset, i16 zeroext %p) {390; CHECK-LABEL: test_vldrdq_gather_shifted_offset_z_s64:391; CHECK: @ %bb.0: @ %entry392; CHECK-NEXT: vmsr p0, r1393; CHECK-NEXT: vpst394; CHECK-NEXT: vldrdt.u64 q1, [r0, q0, uxtw #3]395; CHECK-NEXT: vmov q0, q1396; CHECK-NEXT: bx lr397entry:398 %0 = zext i16 %p to i32399 %1 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %0)400 %2 = call <2 x i64> @llvm.arm.mve.vldr.gather.offset.predicated.v2i64.p0.v2i64.v2i1(ptr %base, <2 x i64> %offset, i32 64, i32 3, i32 0, <2 x i1> %1)401 ret <2 x i64> %2402}403 404define arm_aapcs_vfpcc <2 x i64> @test_vldrdq_gather_shifted_offset_z_u64(ptr %base, <2 x i64> %offset, i16 zeroext %p) {405; CHECK-LABEL: test_vldrdq_gather_shifted_offset_z_u64:406; CHECK: @ %bb.0: @ %entry407; CHECK-NEXT: vmsr p0, r1408; CHECK-NEXT: vpst409; CHECK-NEXT: vldrdt.u64 q1, [r0, q0, uxtw #3]410; CHECK-NEXT: vmov q0, q1411; CHECK-NEXT: bx lr412entry:413 %0 = zext i16 %p to i32414 %1 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %0)415 %2 = call <2 x i64> @llvm.arm.mve.vldr.gather.offset.predicated.v2i64.p0.v2i64.v2i1(ptr %base, <2 x i64> %offset, i32 64, i32 3, i32 1, <2 x i1> %1)416 ret <2 x i64> %2417}418 419define arm_aapcs_vfpcc <8 x half> @test_vldrhq_gather_offset_f16(ptr %base, <8 x i16> %offset) {420; CHECK-LABEL: test_vldrhq_gather_offset_f16:421; CHECK: @ %bb.0: @ %entry422; CHECK-NEXT: vldrh.u16 q1, [r0, q0]423; CHECK-NEXT: vmov q0, q1424; CHECK-NEXT: bx lr425entry:426 %0 = call <8 x half> @llvm.arm.mve.vldr.gather.offset.v8f16.p0.v8i16(ptr %base, <8 x i16> %offset, i32 16, i32 0, i32 0)427 ret <8 x half> %0428}429 430declare <8 x half> @llvm.arm.mve.vldr.gather.offset.v8f16.p0.v8i16(ptr, <8 x i16>, i32, i32, i32)431 432define arm_aapcs_vfpcc <8 x i16> @test_vldrhq_gather_offset_s16(ptr %base, <8 x i16> %offset) {433; CHECK-LABEL: test_vldrhq_gather_offset_s16:434; CHECK: @ %bb.0: @ %entry435; CHECK-NEXT: vldrh.u16 q1, [r0, q0]436; CHECK-NEXT: vmov q0, q1437; CHECK-NEXT: bx lr438entry:439 %0 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.v8i16.p0.v8i16(ptr %base, <8 x i16> %offset, i32 16, i32 0, i32 0)440 ret <8 x i16> %0441}442 443 444define arm_aapcs_vfpcc <4 x i32> @test_vldrhq_gather_offset_s32(ptr %base, <4 x i32> %offset) {445; CHECK-LABEL: test_vldrhq_gather_offset_s32:446; CHECK: @ %bb.0: @ %entry447; CHECK-NEXT: vldrh.s32 q1, [r0, q0]448; CHECK-NEXT: vmov q0, q1449; CHECK-NEXT: bx lr450entry:451 %0 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr %base, <4 x i32> %offset, i32 16, i32 0, i32 0)452 ret <4 x i32> %0453}454 455 456define arm_aapcs_vfpcc <8 x i16> @test_vldrhq_gather_offset_u16(ptr %base, <8 x i16> %offset) {457; CHECK-LABEL: test_vldrhq_gather_offset_u16:458; CHECK: @ %bb.0: @ %entry459; CHECK-NEXT: vldrh.u16 q1, [r0, q0]460; CHECK-NEXT: vmov q0, q1461; CHECK-NEXT: bx lr462entry:463 %0 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.v8i16.p0.v8i16(ptr %base, <8 x i16> %offset, i32 16, i32 0, i32 1)464 ret <8 x i16> %0465}466 467define arm_aapcs_vfpcc <4 x i32> @test_vldrhq_gather_offset_u32(ptr %base, <4 x i32> %offset) {468; CHECK-LABEL: test_vldrhq_gather_offset_u32:469; CHECK: @ %bb.0: @ %entry470; CHECK-NEXT: vldrh.u32 q1, [r0, q0]471; CHECK-NEXT: vmov q0, q1472; CHECK-NEXT: bx lr473entry:474 %0 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr %base, <4 x i32> %offset, i32 16, i32 0, i32 1)475 ret <4 x i32> %0476}477 478define arm_aapcs_vfpcc <8 x half> @test_vldrhq_gather_offset_z_f16(ptr %base, <8 x i16> %offset, i16 zeroext %p) {479; CHECK-LABEL: test_vldrhq_gather_offset_z_f16:480; CHECK: @ %bb.0: @ %entry481; CHECK-NEXT: vmsr p0, r1482; CHECK-NEXT: vpst483; CHECK-NEXT: vldrht.u16 q1, [r0, q0]484; CHECK-NEXT: vmov q0, q1485; CHECK-NEXT: bx lr486entry:487 %0 = zext i16 %p to i32488 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)489 %2 = call <8 x half> @llvm.arm.mve.vldr.gather.offset.predicated.v8f16.p0.v8i16.v8i1(ptr %base, <8 x i16> %offset, i32 16, i32 0, i32 0, <8 x i1> %1)490 ret <8 x half> %2491}492 493declare <8 x half> @llvm.arm.mve.vldr.gather.offset.predicated.v8f16.p0.v8i16.v8i1(ptr, <8 x i16>, i32, i32, i32, <8 x i1>)494 495define arm_aapcs_vfpcc <8 x i16> @test_vldrhq_gather_offset_z_s16(ptr %base, <8 x i16> %offset, i16 zeroext %p) {496; CHECK-LABEL: test_vldrhq_gather_offset_z_s16:497; CHECK: @ %bb.0: @ %entry498; CHECK-NEXT: vmsr p0, r1499; CHECK-NEXT: vpst500; CHECK-NEXT: vldrht.u16 q1, [r0, q0]501; CHECK-NEXT: vmov q0, q1502; CHECK-NEXT: bx lr503entry:504 %0 = zext i16 %p to i32505 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)506 %2 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.predicated.v8i16.p0.v8i16.v8i1(ptr %base, <8 x i16> %offset, i32 16, i32 0, i32 0, <8 x i1> %1)507 ret <8 x i16> %2508}509 510 511define arm_aapcs_vfpcc <4 x i32> @test_vldrhq_gather_offset_z_s32(ptr %base, <4 x i32> %offset, i16 zeroext %p) {512; CHECK-LABEL: test_vldrhq_gather_offset_z_s32:513; CHECK: @ %bb.0: @ %entry514; CHECK-NEXT: vmsr p0, r1515; CHECK-NEXT: vpst516; CHECK-NEXT: vldrht.s32 q1, [r0, q0]517; CHECK-NEXT: vmov q0, q1518; CHECK-NEXT: bx lr519entry:520 %0 = zext i16 %p to i32521 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)522 %2 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0.v4i32.v4i1(ptr %base, <4 x i32> %offset, i32 16, i32 0, i32 0, <4 x i1> %1)523 ret <4 x i32> %2524}525 526 527define arm_aapcs_vfpcc <8 x i16> @test_vldrhq_gather_offset_z_u16(ptr %base, <8 x i16> %offset, i16 zeroext %p) {528; CHECK-LABEL: test_vldrhq_gather_offset_z_u16:529; CHECK: @ %bb.0: @ %entry530; CHECK-NEXT: vmsr p0, r1531; CHECK-NEXT: vpst532; CHECK-NEXT: vldrht.u16 q1, [r0, q0]533; CHECK-NEXT: vmov q0, q1534; CHECK-NEXT: bx lr535entry:536 %0 = zext i16 %p to i32537 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)538 %2 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.predicated.v8i16.p0.v8i16.v8i1(ptr %base, <8 x i16> %offset, i32 16, i32 0, i32 1, <8 x i1> %1)539 ret <8 x i16> %2540}541 542define arm_aapcs_vfpcc <4 x i32> @test_vldrhq_gather_offset_z_u32(ptr %base, <4 x i32> %offset, i16 zeroext %p) {543; CHECK-LABEL: test_vldrhq_gather_offset_z_u32:544; CHECK: @ %bb.0: @ %entry545; CHECK-NEXT: vmsr p0, r1546; CHECK-NEXT: vpst547; CHECK-NEXT: vldrht.u32 q1, [r0, q0]548; CHECK-NEXT: vmov q0, q1549; CHECK-NEXT: bx lr550entry:551 %0 = zext i16 %p to i32552 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)553 %2 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0.v4i32.v4i1(ptr %base, <4 x i32> %offset, i32 16, i32 0, i32 1, <4 x i1> %1)554 ret <4 x i32> %2555}556 557define arm_aapcs_vfpcc <8 x half> @test_vldrhq_gather_shifted_offset_f16(ptr %base, <8 x i16> %offset) {558; CHECK-LABEL: test_vldrhq_gather_shifted_offset_f16:559; CHECK: @ %bb.0: @ %entry560; CHECK-NEXT: vldrh.u16 q1, [r0, q0, uxtw #1]561; CHECK-NEXT: vmov q0, q1562; CHECK-NEXT: bx lr563entry:564 %0 = call <8 x half> @llvm.arm.mve.vldr.gather.offset.v8f16.p0.v8i16(ptr %base, <8 x i16> %offset, i32 16, i32 1, i32 0)565 ret <8 x half> %0566}567 568define arm_aapcs_vfpcc <8 x i16> @test_vldrhq_gather_shifted_offset_s16(ptr %base, <8 x i16> %offset) {569; CHECK-LABEL: test_vldrhq_gather_shifted_offset_s16:570; CHECK: @ %bb.0: @ %entry571; CHECK-NEXT: vldrh.u16 q1, [r0, q0, uxtw #1]572; CHECK-NEXT: vmov q0, q1573; CHECK-NEXT: bx lr574entry:575 %0 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.v8i16.p0.v8i16(ptr %base, <8 x i16> %offset, i32 16, i32 1, i32 0)576 ret <8 x i16> %0577}578 579define arm_aapcs_vfpcc <4 x i32> @test_vldrhq_gather_shifted_offset_s32(ptr %base, <4 x i32> %offset) {580; CHECK-LABEL: test_vldrhq_gather_shifted_offset_s32:581; CHECK: @ %bb.0: @ %entry582; CHECK-NEXT: vldrh.s32 q1, [r0, q0, uxtw #1]583; CHECK-NEXT: vmov q0, q1584; CHECK-NEXT: bx lr585entry:586 %0 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr %base, <4 x i32> %offset, i32 16, i32 1, i32 0)587 ret <4 x i32> %0588}589 590define arm_aapcs_vfpcc <8 x i16> @test_vldrhq_gather_shifted_offset_u16(ptr %base, <8 x i16> %offset) {591; CHECK-LABEL: test_vldrhq_gather_shifted_offset_u16:592; CHECK: @ %bb.0: @ %entry593; CHECK-NEXT: vldrh.u16 q1, [r0, q0, uxtw #1]594; CHECK-NEXT: vmov q0, q1595; CHECK-NEXT: bx lr596entry:597 %0 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.v8i16.p0.v8i16(ptr %base, <8 x i16> %offset, i32 16, i32 1, i32 1)598 ret <8 x i16> %0599}600 601define arm_aapcs_vfpcc <4 x i32> @test_vldrhq_gather_shifted_offset_u32(ptr %base, <4 x i32> %offset) {602; CHECK-LABEL: test_vldrhq_gather_shifted_offset_u32:603; CHECK: @ %bb.0: @ %entry604; CHECK-NEXT: vldrh.u32 q1, [r0, q0, uxtw #1]605; CHECK-NEXT: vmov q0, q1606; CHECK-NEXT: bx lr607entry:608 %0 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr %base, <4 x i32> %offset, i32 16, i32 1, i32 1)609 ret <4 x i32> %0610}611 612define arm_aapcs_vfpcc <8 x half> @test_vldrhq_gather_shifted_offset_z_f16(ptr %base, <8 x i16> %offset, i16 zeroext %p) {613; CHECK-LABEL: test_vldrhq_gather_shifted_offset_z_f16:614; CHECK: @ %bb.0: @ %entry615; CHECK-NEXT: vmsr p0, r1616; CHECK-NEXT: vpst617; CHECK-NEXT: vldrht.u16 q1, [r0, q0, uxtw #1]618; CHECK-NEXT: vmov q0, q1619; CHECK-NEXT: bx lr620entry:621 %0 = zext i16 %p to i32622 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)623 %2 = call <8 x half> @llvm.arm.mve.vldr.gather.offset.predicated.v8f16.p0.v8i16.v8i1(ptr %base, <8 x i16> %offset, i32 16, i32 1, i32 0, <8 x i1> %1)624 ret <8 x half> %2625}626 627define arm_aapcs_vfpcc <8 x i16> @test_vldrhq_gather_shifted_offset_z_s16(ptr %base, <8 x i16> %offset, i16 zeroext %p) {628; CHECK-LABEL: test_vldrhq_gather_shifted_offset_z_s16:629; CHECK: @ %bb.0: @ %entry630; CHECK-NEXT: vmsr p0, r1631; CHECK-NEXT: vpst632; CHECK-NEXT: vldrht.u16 q1, [r0, q0, uxtw #1]633; CHECK-NEXT: vmov q0, q1634; CHECK-NEXT: bx lr635entry:636 %0 = zext i16 %p to i32637 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)638 %2 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.predicated.v8i16.p0.v8i16.v8i1(ptr %base, <8 x i16> %offset, i32 16, i32 1, i32 0, <8 x i1> %1)639 ret <8 x i16> %2640}641 642define arm_aapcs_vfpcc <4 x i32> @test_vldrhq_gather_shifted_offset_z_s32(ptr %base, <4 x i32> %offset, i16 zeroext %p) {643; CHECK-LABEL: test_vldrhq_gather_shifted_offset_z_s32:644; CHECK: @ %bb.0: @ %entry645; CHECK-NEXT: vmsr p0, r1646; CHECK-NEXT: vpst647; CHECK-NEXT: vldrht.s32 q1, [r0, q0, uxtw #1]648; CHECK-NEXT: vmov q0, q1649; CHECK-NEXT: bx lr650entry:651 %0 = zext i16 %p to i32652 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)653 %2 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0.v4i32.v4i1(ptr %base, <4 x i32> %offset, i32 16, i32 1, i32 0, <4 x i1> %1)654 ret <4 x i32> %2655}656 657define arm_aapcs_vfpcc <8 x i16> @test_vldrhq_gather_shifted_offset_z_u16(ptr %base, <8 x i16> %offset, i16 zeroext %p) {658; CHECK-LABEL: test_vldrhq_gather_shifted_offset_z_u16:659; CHECK: @ %bb.0: @ %entry660; CHECK-NEXT: vmsr p0, r1661; CHECK-NEXT: vpst662; CHECK-NEXT: vldrht.u16 q1, [r0, q0, uxtw #1]663; CHECK-NEXT: vmov q0, q1664; CHECK-NEXT: bx lr665entry:666 %0 = zext i16 %p to i32667 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)668 %2 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.predicated.v8i16.p0.v8i16.v8i1(ptr %base, <8 x i16> %offset, i32 16, i32 1, i32 1, <8 x i1> %1)669 ret <8 x i16> %2670}671 672define arm_aapcs_vfpcc <4 x i32> @test_vldrhq_gather_shifted_offset_z_u32(ptr %base, <4 x i32> %offset, i16 zeroext %p) {673; CHECK-LABEL: test_vldrhq_gather_shifted_offset_z_u32:674; CHECK: @ %bb.0: @ %entry675; CHECK-NEXT: vmsr p0, r1676; CHECK-NEXT: vpst677; CHECK-NEXT: vldrht.u32 q1, [r0, q0, uxtw #1]678; CHECK-NEXT: vmov q0, q1679; CHECK-NEXT: bx lr680entry:681 %0 = zext i16 %p to i32682 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)683 %2 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0.v4i32.v4i1(ptr %base, <4 x i32> %offset, i32 16, i32 1, i32 1, <4 x i1> %1)684 ret <4 x i32> %2685}686 687define arm_aapcs_vfpcc <4 x float> @test_vldrwq_gather_base_f32(<4 x i32> %addr) {688; CHECK-LABEL: test_vldrwq_gather_base_f32:689; CHECK: @ %bb.0: @ %entry690; CHECK-NEXT: vldrw.u32 q1, [q0, #12]691; CHECK-NEXT: vmov q0, q1692; CHECK-NEXT: bx lr693entry:694 %0 = call <4 x float> @llvm.arm.mve.vldr.gather.base.v4f32.v4i32(<4 x i32> %addr, i32 12)695 ret <4 x float> %0696}697 698declare <4 x float> @llvm.arm.mve.vldr.gather.base.v4f32.v4i32(<4 x i32>, i32)699 700define arm_aapcs_vfpcc <4 x i32> @test_vldrwq_gather_base_s32(<4 x i32> %addr) {701; CHECK-LABEL: test_vldrwq_gather_base_s32:702; CHECK: @ %bb.0: @ %entry703; CHECK-NEXT: vldrw.u32 q1, [q0, #400]704; CHECK-NEXT: vmov q0, q1705; CHECK-NEXT: bx lr706entry:707 %0 = call <4 x i32> @llvm.arm.mve.vldr.gather.base.v4i32.v4i32(<4 x i32> %addr, i32 400)708 ret <4 x i32> %0709}710 711declare <4 x i32> @llvm.arm.mve.vldr.gather.base.v4i32.v4i32(<4 x i32>, i32)712 713define arm_aapcs_vfpcc <4 x i32> @test_vldrwq_gather_base_u32(<4 x i32> %addr) {714; CHECK-LABEL: test_vldrwq_gather_base_u32:715; CHECK: @ %bb.0: @ %entry716; CHECK-NEXT: vldrw.u32 q1, [q0, #284]717; CHECK-NEXT: vmov q0, q1718; CHECK-NEXT: bx lr719entry:720 %0 = call <4 x i32> @llvm.arm.mve.vldr.gather.base.v4i32.v4i32(<4 x i32> %addr, i32 284)721 ret <4 x i32> %0722}723 724define arm_aapcs_vfpcc <4 x float> @test_vldrwq_gather_base_wb_f32(ptr %addr) {725; CHECK-LABEL: test_vldrwq_gather_base_wb_f32:726; CHECK: @ %bb.0: @ %entry727; CHECK-NEXT: vldrw.u32 q1, [r0]728; CHECK-NEXT: vldrw.u32 q0, [q1, #-64]!729; CHECK-NEXT: vstrw.32 q1, [r0]730; CHECK-NEXT: bx lr731entry:732 %0 = load <4 x i32>, ptr %addr, align 8733 %1 = call { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4f32.v4i32(<4 x i32> %0, i32 -64)734 %2 = extractvalue { <4 x float>, <4 x i32> } %1, 1735 store <4 x i32> %2, ptr %addr, align 8736 %3 = extractvalue { <4 x float>, <4 x i32> } %1, 0737 ret <4 x float> %3738}739 740declare { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4f32.v4i32(<4 x i32>, i32)741 742define arm_aapcs_vfpcc <4 x i32> @test_vldrwq_gather_base_wb_s32(ptr %addr) {743; CHECK-LABEL: test_vldrwq_gather_base_wb_s32:744; CHECK: @ %bb.0: @ %entry745; CHECK-NEXT: vldrw.u32 q1, [r0]746; CHECK-NEXT: vldrw.u32 q0, [q1, #80]!747; CHECK-NEXT: vstrw.32 q1, [r0]748; CHECK-NEXT: bx lr749entry:750 %0 = load <4 x i32>, ptr %addr, align 8751 %1 = call { <4 x i32>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4i32.v4i32(<4 x i32> %0, i32 80)752 %2 = extractvalue { <4 x i32>, <4 x i32> } %1, 1753 store <4 x i32> %2, ptr %addr, align 8754 %3 = extractvalue { <4 x i32>, <4 x i32> } %1, 0755 ret <4 x i32> %3756}757 758declare { <4 x i32>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4i32.v4i32(<4 x i32>, i32)759 760define arm_aapcs_vfpcc <4 x i32> @test_vldrwq_gather_base_wb_u32(ptr %addr) {761; CHECK-LABEL: test_vldrwq_gather_base_wb_u32:762; CHECK: @ %bb.0: @ %entry763; CHECK-NEXT: vldrw.u32 q1, [r0]764; CHECK-NEXT: vldrw.u32 q0, [q1, #480]!765; CHECK-NEXT: vstrw.32 q1, [r0]766; CHECK-NEXT: bx lr767entry:768 %0 = load <4 x i32>, ptr %addr, align 8769 %1 = call { <4 x i32>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4i32.v4i32(<4 x i32> %0, i32 480)770 %2 = extractvalue { <4 x i32>, <4 x i32> } %1, 1771 store <4 x i32> %2, ptr %addr, align 8772 %3 = extractvalue { <4 x i32>, <4 x i32> } %1, 0773 ret <4 x i32> %3774}775 776define arm_aapcs_vfpcc <4 x float> @test_vldrwq_gather_base_wb_z_f32(ptr %addr, i16 zeroext %p) {777; CHECK-LABEL: test_vldrwq_gather_base_wb_z_f32:778; CHECK: @ %bb.0: @ %entry779; CHECK-NEXT: vmsr p0, r1780; CHECK-NEXT: vldrw.u32 q1, [r0]781; CHECK-NEXT: vpst782; CHECK-NEXT: vldrwt.u32 q0, [q1, #-352]!783; CHECK-NEXT: vstrw.32 q1, [r0]784; CHECK-NEXT: bx lr785entry:786 %0 = load <4 x i32>, ptr %addr, align 8787 %1 = zext i16 %p to i32788 %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)789 %3 = call { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v4f32.v4i32.v4i1(<4 x i32> %0, i32 -352, <4 x i1> %2)790 %4 = extractvalue { <4 x float>, <4 x i32> } %3, 1791 store <4 x i32> %4, ptr %addr, align 8792 %5 = extractvalue { <4 x float>, <4 x i32> } %3, 0793 ret <4 x float> %5794}795 796declare { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v4f32.v4i32.v4i1(<4 x i32>, i32, <4 x i1>)797 798define arm_aapcs_vfpcc <4 x i32> @test_vldrwq_gather_base_wb_z_s32(ptr %addr, i16 zeroext %p) {799; CHECK-LABEL: test_vldrwq_gather_base_wb_z_s32:800; CHECK: @ %bb.0: @ %entry801; CHECK-NEXT: vmsr p0, r1802; CHECK-NEXT: vldrw.u32 q1, [r0]803; CHECK-NEXT: vpst804; CHECK-NEXT: vldrwt.u32 q0, [q1, #276]!805; CHECK-NEXT: vstrw.32 q1, [r0]806; CHECK-NEXT: bx lr807entry:808 %0 = load <4 x i32>, ptr %addr, align 8809 %1 = zext i16 %p to i32810 %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)811 %3 = call { <4 x i32>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v4i32.v4i32.v4i1(<4 x i32> %0, i32 276, <4 x i1> %2)812 %4 = extractvalue { <4 x i32>, <4 x i32> } %3, 1813 store <4 x i32> %4, ptr %addr, align 8814 %5 = extractvalue { <4 x i32>, <4 x i32> } %3, 0815 ret <4 x i32> %5816}817 818declare { <4 x i32>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v4i32.v4i32.v4i1(<4 x i32>, i32, <4 x i1>)819 820define arm_aapcs_vfpcc <4 x i32> @test_vldrwq_gather_base_wb_z_u32(ptr %addr, i16 zeroext %p) {821; CHECK-LABEL: test_vldrwq_gather_base_wb_z_u32:822; CHECK: @ %bb.0: @ %entry823; CHECK-NEXT: vmsr p0, r1824; CHECK-NEXT: vldrw.u32 q1, [r0]825; CHECK-NEXT: vpst826; CHECK-NEXT: vldrwt.u32 q0, [q1, #88]!827; CHECK-NEXT: vstrw.32 q1, [r0]828; CHECK-NEXT: bx lr829entry:830 %0 = load <4 x i32>, ptr %addr, align 8831 %1 = zext i16 %p to i32832 %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)833 %3 = call { <4 x i32>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v4i32.v4i32.v4i1(<4 x i32> %0, i32 88, <4 x i1> %2)834 %4 = extractvalue { <4 x i32>, <4 x i32> } %3, 1835 store <4 x i32> %4, ptr %addr, align 8836 %5 = extractvalue { <4 x i32>, <4 x i32> } %3, 0837 ret <4 x i32> %5838}839 840define arm_aapcs_vfpcc <4 x float> @test_vldrwq_gather_base_z_f32(<4 x i32> %addr, i16 zeroext %p) {841; CHECK-LABEL: test_vldrwq_gather_base_z_f32:842; CHECK: @ %bb.0: @ %entry843; CHECK-NEXT: vmsr p0, r0844; CHECK-NEXT: vpst845; CHECK-NEXT: vldrwt.u32 q1, [q0, #-300]846; CHECK-NEXT: vmov q0, q1847; CHECK-NEXT: bx lr848entry:849 %0 = zext i16 %p to i32850 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)851 %2 = call <4 x float> @llvm.arm.mve.vldr.gather.base.predicated.v4f32.v4i32.v4i1(<4 x i32> %addr, i32 -300, <4 x i1> %1)852 ret <4 x float> %2853}854 855declare <4 x float> @llvm.arm.mve.vldr.gather.base.predicated.v4f32.v4i32.v4i1(<4 x i32>, i32, <4 x i1>)856 857define arm_aapcs_vfpcc <4 x i32> @test_vldrwq_gather_base_z_s32(<4 x i32> %addr, i16 zeroext %p) {858; CHECK-LABEL: test_vldrwq_gather_base_z_s32:859; CHECK: @ %bb.0: @ %entry860; CHECK-NEXT: vmsr p0, r0861; CHECK-NEXT: vpst862; CHECK-NEXT: vldrwt.u32 q1, [q0, #440]863; CHECK-NEXT: vmov q0, q1864; CHECK-NEXT: bx lr865entry:866 %0 = zext i16 %p to i32867 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)868 %2 = call <4 x i32> @llvm.arm.mve.vldr.gather.base.predicated.v4i32.v4i32.v4i1(<4 x i32> %addr, i32 440, <4 x i1> %1)869 ret <4 x i32> %2870}871 872declare <4 x i32> @llvm.arm.mve.vldr.gather.base.predicated.v4i32.v4i32.v4i1(<4 x i32>, i32, <4 x i1>)873 874define arm_aapcs_vfpcc <4 x i32> @test_vldrwq_gather_base_z_u32(<4 x i32> %addr, i16 zeroext %p) {875; CHECK-LABEL: test_vldrwq_gather_base_z_u32:876; CHECK: @ %bb.0: @ %entry877; CHECK-NEXT: vmsr p0, r0878; CHECK-NEXT: vpst879; CHECK-NEXT: vldrwt.u32 q1, [q0, #300]880; CHECK-NEXT: vmov q0, q1881; CHECK-NEXT: bx lr882entry:883 %0 = zext i16 %p to i32884 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)885 %2 = call <4 x i32> @llvm.arm.mve.vldr.gather.base.predicated.v4i32.v4i32.v4i1(<4 x i32> %addr, i32 300, <4 x i1> %1)886 ret <4 x i32> %2887}888 889define arm_aapcs_vfpcc <4 x float> @test_vldrwq_gather_offset_f32(ptr %base, <4 x i32> %offset) {890; CHECK-LABEL: test_vldrwq_gather_offset_f32:891; CHECK: @ %bb.0: @ %entry892; CHECK-NEXT: vldrw.u32 q1, [r0, q0]893; CHECK-NEXT: vmov q0, q1894; CHECK-NEXT: bx lr895entry:896 %0 = call <4 x float> @llvm.arm.mve.vldr.gather.offset.v4f32.p0.v4i32(ptr %base, <4 x i32> %offset, i32 32, i32 0, i32 0)897 ret <4 x float> %0898}899 900declare <4 x float> @llvm.arm.mve.vldr.gather.offset.v4f32.p0.v4i32(ptr, <4 x i32>, i32, i32, i32)901 902define arm_aapcs_vfpcc <4 x i32> @test_vldrwq_gather_offset_s32(ptr %base, <4 x i32> %offset) {903; CHECK-LABEL: test_vldrwq_gather_offset_s32:904; CHECK: @ %bb.0: @ %entry905; CHECK-NEXT: vldrw.u32 q1, [r0, q0]906; CHECK-NEXT: vmov q0, q1907; CHECK-NEXT: bx lr908entry:909 %0 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr %base, <4 x i32> %offset, i32 32, i32 0, i32 0)910 ret <4 x i32> %0911}912 913 914define arm_aapcs_vfpcc <4 x i32> @test_vldrwq_gather_offset_u32(ptr %base, <4 x i32> %offset) {915; CHECK-LABEL: test_vldrwq_gather_offset_u32:916; CHECK: @ %bb.0: @ %entry917; CHECK-NEXT: vldrw.u32 q1, [r0, q0]918; CHECK-NEXT: vmov q0, q1919; CHECK-NEXT: bx lr920entry:921 %0 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr %base, <4 x i32> %offset, i32 32, i32 0, i32 1)922 ret <4 x i32> %0923}924 925define arm_aapcs_vfpcc <4 x float> @test_vldrwq_gather_offset_z_f32(ptr %base, <4 x i32> %offset, i16 zeroext %p) {926; CHECK-LABEL: test_vldrwq_gather_offset_z_f32:927; CHECK: @ %bb.0: @ %entry928; CHECK-NEXT: vmsr p0, r1929; CHECK-NEXT: vpst930; CHECK-NEXT: vldrwt.u32 q1, [r0, q0]931; CHECK-NEXT: vmov q0, q1932; CHECK-NEXT: bx lr933entry:934 %0 = zext i16 %p to i32935 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)936 %2 = call <4 x float> @llvm.arm.mve.vldr.gather.offset.predicated.v4f32.p0.v4i32.v4i1(ptr %base, <4 x i32> %offset, i32 32, i32 0, i32 0, <4 x i1> %1)937 ret <4 x float> %2938}939 940declare <4 x float> @llvm.arm.mve.vldr.gather.offset.predicated.v4f32.p0.v4i32.v4i1(ptr, <4 x i32>, i32, i32, i32, <4 x i1>)941 942define arm_aapcs_vfpcc <4 x i32> @test_vldrwq_gather_offset_z_s32(ptr %base, <4 x i32> %offset, i16 zeroext %p) {943; CHECK-LABEL: test_vldrwq_gather_offset_z_s32:944; CHECK: @ %bb.0: @ %entry945; CHECK-NEXT: vmsr p0, r1946; CHECK-NEXT: vpst947; CHECK-NEXT: vldrwt.u32 q1, [r0, q0]948; CHECK-NEXT: vmov q0, q1949; CHECK-NEXT: bx lr950entry:951 %0 = zext i16 %p to i32952 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)953 %2 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0.v4i32.v4i1(ptr %base, <4 x i32> %offset, i32 32, i32 0, i32 0, <4 x i1> %1)954 ret <4 x i32> %2955}956 957 958define arm_aapcs_vfpcc <4 x i32> @test_vldrwq_gather_offset_z_u32(ptr %base, <4 x i32> %offset, i16 zeroext %p) {959; CHECK-LABEL: test_vldrwq_gather_offset_z_u32:960; CHECK: @ %bb.0: @ %entry961; CHECK-NEXT: vmsr p0, r1962; CHECK-NEXT: vpst963; CHECK-NEXT: vldrwt.u32 q1, [r0, q0]964; CHECK-NEXT: vmov q0, q1965; CHECK-NEXT: bx lr966entry:967 %0 = zext i16 %p to i32968 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)969 %2 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0.v4i32.v4i1(ptr %base, <4 x i32> %offset, i32 32, i32 0, i32 1, <4 x i1> %1)970 ret <4 x i32> %2971}972 973define arm_aapcs_vfpcc <4 x float> @test_vldrwq_gather_shifted_offset_f32(ptr %base, <4 x i32> %offset) {974; CHECK-LABEL: test_vldrwq_gather_shifted_offset_f32:975; CHECK: @ %bb.0: @ %entry976; CHECK-NEXT: vldrw.u32 q1, [r0, q0, uxtw #2]977; CHECK-NEXT: vmov q0, q1978; CHECK-NEXT: bx lr979entry:980 %0 = call <4 x float> @llvm.arm.mve.vldr.gather.offset.v4f32.p0.v4i32(ptr %base, <4 x i32> %offset, i32 32, i32 2, i32 0)981 ret <4 x float> %0982}983 984define arm_aapcs_vfpcc <4 x i32> @test_vldrwq_gather_shifted_offset_s32(ptr %base, <4 x i32> %offset) {985; CHECK-LABEL: test_vldrwq_gather_shifted_offset_s32:986; CHECK: @ %bb.0: @ %entry987; CHECK-NEXT: vldrw.u32 q1, [r0, q0, uxtw #2]988; CHECK-NEXT: vmov q0, q1989; CHECK-NEXT: bx lr990entry:991 %0 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr %base, <4 x i32> %offset, i32 32, i32 2, i32 0)992 ret <4 x i32> %0993}994 995define arm_aapcs_vfpcc <4 x i32> @test_vldrwq_gather_shifted_offset_u32(ptr %base, <4 x i32> %offset) {996; CHECK-LABEL: test_vldrwq_gather_shifted_offset_u32:997; CHECK: @ %bb.0: @ %entry998; CHECK-NEXT: vldrw.u32 q1, [r0, q0, uxtw #2]999; CHECK-NEXT: vmov q0, q11000; CHECK-NEXT: bx lr1001entry:1002 %0 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr %base, <4 x i32> %offset, i32 32, i32 2, i32 1)1003 ret <4 x i32> %01004}1005 1006define arm_aapcs_vfpcc <4 x float> @test_vldrwq_gather_shifted_offset_z_f32(ptr %base, <4 x i32> %offset, i16 zeroext %p) {1007; CHECK-LABEL: test_vldrwq_gather_shifted_offset_z_f32:1008; CHECK: @ %bb.0: @ %entry1009; CHECK-NEXT: vmsr p0, r11010; CHECK-NEXT: vpst1011; CHECK-NEXT: vldrwt.u32 q1, [r0, q0, uxtw #2]1012; CHECK-NEXT: vmov q0, q11013; CHECK-NEXT: bx lr1014entry:1015 %0 = zext i16 %p to i321016 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1017 %2 = call <4 x float> @llvm.arm.mve.vldr.gather.offset.predicated.v4f32.p0.v4i32.v4i1(ptr %base, <4 x i32> %offset, i32 32, i32 2, i32 0, <4 x i1> %1)1018 ret <4 x float> %21019}1020 1021define arm_aapcs_vfpcc <4 x i32> @test_vldrwq_gather_shifted_offset_z_s32(ptr %base, <4 x i32> %offset, i16 zeroext %p) {1022; CHECK-LABEL: test_vldrwq_gather_shifted_offset_z_s32:1023; CHECK: @ %bb.0: @ %entry1024; CHECK-NEXT: vmsr p0, r11025; CHECK-NEXT: vpst1026; CHECK-NEXT: vldrwt.u32 q1, [r0, q0, uxtw #2]1027; CHECK-NEXT: vmov q0, q11028; CHECK-NEXT: bx lr1029entry:1030 %0 = zext i16 %p to i321031 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1032 %2 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0.v4i32.v4i1(ptr %base, <4 x i32> %offset, i32 32, i32 2, i32 0, <4 x i1> %1)1033 ret <4 x i32> %21034}1035 1036define arm_aapcs_vfpcc <4 x i32> @test_vldrwq_gather_shifted_offset_z_u32(ptr %base, <4 x i32> %offset, i16 zeroext %p) {1037; CHECK-LABEL: test_vldrwq_gather_shifted_offset_z_u32:1038; CHECK: @ %bb.0: @ %entry1039; CHECK-NEXT: vmsr p0, r11040; CHECK-NEXT: vpst1041; CHECK-NEXT: vldrwt.u32 q1, [r0, q0, uxtw #2]1042; CHECK-NEXT: vmov q0, q11043; CHECK-NEXT: bx lr1044entry:1045 %0 = zext i16 %p to i321046 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1047 %2 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0.v4i32.v4i1(ptr %base, <4 x i32> %offset, i32 32, i32 2, i32 1, <4 x i1> %1)1048 ret <4 x i32> %21049}1050 1051define arm_aapcs_vfpcc void @test_vstrbq_scatter_offset_p_s16(ptr %base, <8 x i16> %offset, <8 x i16> %value, i16 zeroext %p) {1052; CHECK-LABEL: test_vstrbq_scatter_offset_p_s16:1053; CHECK: @ %bb.0: @ %entry1054; CHECK-NEXT: vmsr p0, r11055; CHECK-NEXT: vpst1056; CHECK-NEXT: vstrbt.16 q1, [r0, q0]1057; CHECK-NEXT: bx lr1058entry:1059 %0 = zext i16 %p to i321060 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)1061 call void @llvm.arm.mve.vstr.scatter.offset.predicated.p0.v8i16.v8i16.v8i1(ptr %base, <8 x i16> %offset, <8 x i16> %value, i32 8, i32 0, <8 x i1> %1)1062 ret void1063}1064 1065declare void @llvm.arm.mve.vstr.scatter.offset.predicated.p0.v8i16.v8i16.v8i1(ptr, <8 x i16>, <8 x i16>, i32, i32, <8 x i1>)1066 1067define arm_aapcs_vfpcc void @test_vstrbq_scatter_offset_p_s32(ptr %base, <4 x i32> %offset, <4 x i32> %value, i16 zeroext %p) {1068; CHECK-LABEL: test_vstrbq_scatter_offset_p_s32:1069; CHECK: @ %bb.0: @ %entry1070; CHECK-NEXT: vmsr p0, r11071; CHECK-NEXT: vpst1072; CHECK-NEXT: vstrbt.32 q1, [r0, q0]1073; CHECK-NEXT: bx lr1074entry:1075 %0 = zext i16 %p to i321076 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1077 call void @llvm.arm.mve.vstr.scatter.offset.predicated.p0.v4i32.v4i32.v4i1(ptr %base, <4 x i32> %offset, <4 x i32> %value, i32 8, i32 0, <4 x i1> %1)1078 ret void1079}1080 1081declare void @llvm.arm.mve.vstr.scatter.offset.predicated.p0.v4i32.v4i32.v4i1(ptr, <4 x i32>, <4 x i32>, i32, i32, <4 x i1>)1082 1083define arm_aapcs_vfpcc void @test_vstrbq_scatter_offset_p_s8(ptr %base, <16 x i8> %offset, <16 x i8> %value, i16 zeroext %p) {1084; CHECK-LABEL: test_vstrbq_scatter_offset_p_s8:1085; CHECK: @ %bb.0: @ %entry1086; CHECK-NEXT: vmsr p0, r11087; CHECK-NEXT: vpst1088; CHECK-NEXT: vstrbt.8 q1, [r0, q0]1089; CHECK-NEXT: bx lr1090entry:1091 %0 = zext i16 %p to i321092 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)1093 call void @llvm.arm.mve.vstr.scatter.offset.predicated.p0.v16i8.v16i8.v16i1(ptr %base, <16 x i8> %offset, <16 x i8> %value, i32 8, i32 0, <16 x i1> %1)1094 ret void1095}1096 1097declare void @llvm.arm.mve.vstr.scatter.offset.predicated.p0.v16i8.v16i8.v16i1(ptr, <16 x i8>, <16 x i8>, i32, i32, <16 x i1>)1098 1099define arm_aapcs_vfpcc void @test_vstrbq_scatter_offset_p_u16(ptr %base, <8 x i16> %offset, <8 x i16> %value, i16 zeroext %p) {1100; CHECK-LABEL: test_vstrbq_scatter_offset_p_u16:1101; CHECK: @ %bb.0: @ %entry1102; CHECK-NEXT: vmsr p0, r11103; CHECK-NEXT: vpst1104; CHECK-NEXT: vstrbt.16 q1, [r0, q0]1105; CHECK-NEXT: bx lr1106entry:1107 %0 = zext i16 %p to i321108 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)1109 call void @llvm.arm.mve.vstr.scatter.offset.predicated.p0.v8i16.v8i16.v8i1(ptr %base, <8 x i16> %offset, <8 x i16> %value, i32 8, i32 0, <8 x i1> %1)1110 ret void1111}1112 1113define arm_aapcs_vfpcc void @test_vstrbq_scatter_offset_p_u32(ptr %base, <4 x i32> %offset, <4 x i32> %value, i16 zeroext %p) {1114; CHECK-LABEL: test_vstrbq_scatter_offset_p_u32:1115; CHECK: @ %bb.0: @ %entry1116; CHECK-NEXT: vmsr p0, r11117; CHECK-NEXT: vpst1118; CHECK-NEXT: vstrbt.32 q1, [r0, q0]1119; CHECK-NEXT: bx lr1120entry:1121 %0 = zext i16 %p to i321122 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1123 call void @llvm.arm.mve.vstr.scatter.offset.predicated.p0.v4i32.v4i32.v4i1(ptr %base, <4 x i32> %offset, <4 x i32> %value, i32 8, i32 0, <4 x i1> %1)1124 ret void1125}1126 1127define arm_aapcs_vfpcc void @test_vstrbq_scatter_offset_p_u8(ptr %base, <16 x i8> %offset, <16 x i8> %value, i16 zeroext %p) {1128; CHECK-LABEL: test_vstrbq_scatter_offset_p_u8:1129; CHECK: @ %bb.0: @ %entry1130; CHECK-NEXT: vmsr p0, r11131; CHECK-NEXT: vpst1132; CHECK-NEXT: vstrbt.8 q1, [r0, q0]1133; CHECK-NEXT: bx lr1134entry:1135 %0 = zext i16 %p to i321136 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)1137 call void @llvm.arm.mve.vstr.scatter.offset.predicated.p0.v16i8.v16i8.v16i1(ptr %base, <16 x i8> %offset, <16 x i8> %value, i32 8, i32 0, <16 x i1> %1)1138 ret void1139}1140 1141define arm_aapcs_vfpcc void @test_vstrbq_scatter_offset_s16(ptr %base, <8 x i16> %offset, <8 x i16> %value) {1142; CHECK-LABEL: test_vstrbq_scatter_offset_s16:1143; CHECK: @ %bb.0: @ %entry1144; CHECK-NEXT: vstrb.16 q1, [r0, q0]1145; CHECK-NEXT: bx lr1146entry:1147 call void @llvm.arm.mve.vstr.scatter.offset.p0.v8i16.v8i16(ptr %base, <8 x i16> %offset, <8 x i16> %value, i32 8, i32 0)1148 ret void1149}1150 1151declare void @llvm.arm.mve.vstr.scatter.offset.p0.v8i16.v8i16(ptr, <8 x i16>, <8 x i16>, i32, i32)1152 1153define arm_aapcs_vfpcc void @test_vstrbq_scatter_offset_s32(ptr %base, <4 x i32> %offset, <4 x i32> %value) {1154; CHECK-LABEL: test_vstrbq_scatter_offset_s32:1155; CHECK: @ %bb.0: @ %entry1156; CHECK-NEXT: vstrb.32 q1, [r0, q0]1157; CHECK-NEXT: bx lr1158entry:1159 call void @llvm.arm.mve.vstr.scatter.offset.p0.v4i32.v4i32(ptr %base, <4 x i32> %offset, <4 x i32> %value, i32 8, i32 0)1160 ret void1161}1162 1163declare void @llvm.arm.mve.vstr.scatter.offset.p0.v4i32.v4i32(ptr, <4 x i32>, <4 x i32>, i32, i32)1164 1165define arm_aapcs_vfpcc void @test_vstrbq_scatter_offset_s8(ptr %base, <16 x i8> %offset, <16 x i8> %value) {1166; CHECK-LABEL: test_vstrbq_scatter_offset_s8:1167; CHECK: @ %bb.0: @ %entry1168; CHECK-NEXT: vstrb.8 q1, [r0, q0]1169; CHECK-NEXT: bx lr1170entry:1171 call void @llvm.arm.mve.vstr.scatter.offset.p0.v16i8.v16i8(ptr %base, <16 x i8> %offset, <16 x i8> %value, i32 8, i32 0)1172 ret void1173}1174 1175declare void @llvm.arm.mve.vstr.scatter.offset.p0.v16i8.v16i8(ptr, <16 x i8>, <16 x i8>, i32, i32)1176 1177define arm_aapcs_vfpcc void @test_vstrbq_scatter_offset_u16(ptr %base, <8 x i16> %offset, <8 x i16> %value) {1178; CHECK-LABEL: test_vstrbq_scatter_offset_u16:1179; CHECK: @ %bb.0: @ %entry1180; CHECK-NEXT: vstrb.16 q1, [r0, q0]1181; CHECK-NEXT: bx lr1182entry:1183 call void @llvm.arm.mve.vstr.scatter.offset.p0.v8i16.v8i16(ptr %base, <8 x i16> %offset, <8 x i16> %value, i32 8, i32 0)1184 ret void1185}1186 1187define arm_aapcs_vfpcc void @test_vstrbq_scatter_offset_u32(ptr %base, <4 x i32> %offset, <4 x i32> %value) {1188; CHECK-LABEL: test_vstrbq_scatter_offset_u32:1189; CHECK: @ %bb.0: @ %entry1190; CHECK-NEXT: vstrb.32 q1, [r0, q0]1191; CHECK-NEXT: bx lr1192entry:1193 call void @llvm.arm.mve.vstr.scatter.offset.p0.v4i32.v4i32(ptr %base, <4 x i32> %offset, <4 x i32> %value, i32 8, i32 0)1194 ret void1195}1196 1197define arm_aapcs_vfpcc void @test_vstrbq_scatter_offset_u8(ptr %base, <16 x i8> %offset, <16 x i8> %value) {1198; CHECK-LABEL: test_vstrbq_scatter_offset_u8:1199; CHECK: @ %bb.0: @ %entry1200; CHECK-NEXT: vstrb.8 q1, [r0, q0]1201; CHECK-NEXT: bx lr1202entry:1203 call void @llvm.arm.mve.vstr.scatter.offset.p0.v16i8.v16i8(ptr %base, <16 x i8> %offset, <16 x i8> %value, i32 8, i32 0)1204 ret void1205}1206 1207define arm_aapcs_vfpcc void @test_vstrdq_scatter_base_p_s64(<2 x i64> %addr, <2 x i64> %value, i16 zeroext %p) {1208; CHECK-LABEL: test_vstrdq_scatter_base_p_s64:1209; CHECK: @ %bb.0: @ %entry1210; CHECK-NEXT: vmsr p0, r01211; CHECK-NEXT: vpst1212; CHECK-NEXT: vstrdt.64 q1, [q0, #888]1213; CHECK-NEXT: bx lr1214entry:1215 %0 = zext i16 %p to i321216 %1 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %0)1217 call void @llvm.arm.mve.vstr.scatter.base.predicated.v2i64.v2i64.v2i1(<2 x i64> %addr, i32 888, <2 x i64> %value, <2 x i1> %1)1218 ret void1219}1220 1221declare void @llvm.arm.mve.vstr.scatter.base.predicated.v2i64.v2i64.v2i1(<2 x i64>, i32, <2 x i64>, <2 x i1>)1222 1223define arm_aapcs_vfpcc void @test_vstrdq_scatter_base_p_u64(<2 x i64> %addr, <2 x i64> %value, i16 zeroext %p) {1224; CHECK-LABEL: test_vstrdq_scatter_base_p_u64:1225; CHECK: @ %bb.0: @ %entry1226; CHECK-NEXT: vmsr p0, r01227; CHECK-NEXT: vpst1228; CHECK-NEXT: vstrdt.64 q1, [q0, #264]1229; CHECK-NEXT: bx lr1230entry:1231 %0 = zext i16 %p to i321232 %1 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %0)1233 call void @llvm.arm.mve.vstr.scatter.base.predicated.v2i64.v2i64.v2i1(<2 x i64> %addr, i32 264, <2 x i64> %value, <2 x i1> %1)1234 ret void1235}1236 1237define arm_aapcs_vfpcc void @test_vstrdq_scatter_base_s64(<2 x i64> %addr, <2 x i64> %value) {1238; CHECK-LABEL: test_vstrdq_scatter_base_s64:1239; CHECK: @ %bb.0: @ %entry1240; CHECK-NEXT: vstrd.64 q1, [q0, #408]1241; CHECK-NEXT: bx lr1242entry:1243 call void @llvm.arm.mve.vstr.scatter.base.v2i64.v2i64(<2 x i64> %addr, i32 408, <2 x i64> %value)1244 ret void1245}1246 1247declare void @llvm.arm.mve.vstr.scatter.base.v2i64.v2i64(<2 x i64>, i32, <2 x i64>)1248 1249define arm_aapcs_vfpcc void @test_vstrdq_scatter_base_u64(<2 x i64> %addr, <2 x i64> %value) {1250; CHECK-LABEL: test_vstrdq_scatter_base_u64:1251; CHECK: @ %bb.0: @ %entry1252; CHECK-NEXT: vstrd.64 q1, [q0, #-472]1253; CHECK-NEXT: bx lr1254entry:1255 call void @llvm.arm.mve.vstr.scatter.base.v2i64.v2i64(<2 x i64> %addr, i32 -472, <2 x i64> %value)1256 ret void1257}1258 1259define arm_aapcs_vfpcc void @test_vstrdq_scatter_base_wb_p_s64(ptr %addr, <2 x i64> %value, i16 zeroext %p) {1260; CHECK-LABEL: test_vstrdq_scatter_base_wb_p_s64:1261; CHECK: @ %bb.0: @ %entry1262; CHECK-NEXT: vldrw.u32 q1, [r0]1263; CHECK-NEXT: vmsr p0, r11264; CHECK-NEXT: vpst1265; CHECK-NEXT: vstrdt.64 q0, [q1, #248]!1266; CHECK-NEXT: vstrw.32 q1, [r0]1267; CHECK-NEXT: bx lr1268entry:1269 %0 = load <2 x i64>, ptr %addr, align 81270 %1 = zext i16 %p to i321271 %2 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %1)1272 %3 = call <2 x i64> @llvm.arm.mve.vstr.scatter.base.wb.predicated.v2i64.v2i64.v2i1(<2 x i64> %0, i32 248, <2 x i64> %value, <2 x i1> %2)1273 store <2 x i64> %3, ptr %addr, align 81274 ret void1275}1276 1277declare <2 x i64> @llvm.arm.mve.vstr.scatter.base.wb.predicated.v2i64.v2i64.v2i1(<2 x i64>, i32, <2 x i64>, <2 x i1>)1278 1279define arm_aapcs_vfpcc void @test_vstrdq_scatter_base_wb_p_u64(ptr %addr, <2 x i64> %value, i16 zeroext %p) {1280; CHECK-LABEL: test_vstrdq_scatter_base_wb_p_u64:1281; CHECK: @ %bb.0: @ %entry1282; CHECK-NEXT: vldrw.u32 q1, [r0]1283; CHECK-NEXT: vmsr p0, r11284; CHECK-NEXT: vpst1285; CHECK-NEXT: vstrdt.64 q0, [q1, #136]!1286; CHECK-NEXT: vstrw.32 q1, [r0]1287; CHECK-NEXT: bx lr1288entry:1289 %0 = load <2 x i64>, ptr %addr, align 81290 %1 = zext i16 %p to i321291 %2 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %1)1292 %3 = call <2 x i64> @llvm.arm.mve.vstr.scatter.base.wb.predicated.v2i64.v2i64.v2i1(<2 x i64> %0, i32 136, <2 x i64> %value, <2 x i1> %2)1293 store <2 x i64> %3, ptr %addr, align 81294 ret void1295}1296 1297define arm_aapcs_vfpcc void @test_vstrdq_scatter_base_wb_s64(ptr %addr, <2 x i64> %value) {1298; CHECK-LABEL: test_vstrdq_scatter_base_wb_s64:1299; CHECK: @ %bb.0: @ %entry1300; CHECK-NEXT: vldrw.u32 q1, [r0]1301; CHECK-NEXT: vstrd.64 q0, [q1, #208]!1302; CHECK-NEXT: vstrw.32 q1, [r0]1303; CHECK-NEXT: bx lr1304entry:1305 %0 = load <2 x i64>, ptr %addr, align 81306 %1 = call <2 x i64> @llvm.arm.mve.vstr.scatter.base.wb.v2i64.v2i64(<2 x i64> %0, i32 208, <2 x i64> %value)1307 store <2 x i64> %1, ptr %addr, align 81308 ret void1309}1310 1311declare <2 x i64> @llvm.arm.mve.vstr.scatter.base.wb.v2i64.v2i64(<2 x i64>, i32, <2 x i64>)1312 1313define arm_aapcs_vfpcc void @test_vstrdq_scatter_base_wb_u64(ptr %addr, <2 x i64> %value) {1314; CHECK-LABEL: test_vstrdq_scatter_base_wb_u64:1315; CHECK: @ %bb.0: @ %entry1316; CHECK-NEXT: vldrw.u32 q1, [r0]1317; CHECK-NEXT: vstrd.64 q0, [q1, #-168]!1318; CHECK-NEXT: vstrw.32 q1, [r0]1319; CHECK-NEXT: bx lr1320entry:1321 %0 = load <2 x i64>, ptr %addr, align 81322 %1 = call <2 x i64> @llvm.arm.mve.vstr.scatter.base.wb.v2i64.v2i64(<2 x i64> %0, i32 -168, <2 x i64> %value)1323 store <2 x i64> %1, ptr %addr, align 81324 ret void1325}1326 1327define arm_aapcs_vfpcc void @test_vstrdq_scatter_offset_p_s64(ptr %base, <2 x i64> %offset, <2 x i64> %value, i16 zeroext %p) {1328; CHECK-LABEL: test_vstrdq_scatter_offset_p_s64:1329; CHECK: @ %bb.0: @ %entry1330; CHECK-NEXT: vmsr p0, r11331; CHECK-NEXT: vpst1332; CHECK-NEXT: vstrdt.64 q1, [r0, q0]1333; CHECK-NEXT: bx lr1334entry:1335 %0 = zext i16 %p to i321336 %1 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %0)1337 call void @llvm.arm.mve.vstr.scatter.offset.predicated.p0.v2i64.v2i64.v2i1(ptr %base, <2 x i64> %offset, <2 x i64> %value, i32 64, i32 0, <2 x i1> %1)1338 ret void1339}1340 1341declare void @llvm.arm.mve.vstr.scatter.offset.predicated.p0.v2i64.v2i64.v2i1(ptr, <2 x i64>, <2 x i64>, i32, i32, <2 x i1>)1342 1343define arm_aapcs_vfpcc void @test_vstrdq_scatter_offset_p_u64(ptr %base, <2 x i64> %offset, <2 x i64> %value, i16 zeroext %p) {1344; CHECK-LABEL: test_vstrdq_scatter_offset_p_u64:1345; CHECK: @ %bb.0: @ %entry1346; CHECK-NEXT: vmsr p0, r11347; CHECK-NEXT: vpst1348; CHECK-NEXT: vstrdt.64 q1, [r0, q0]1349; CHECK-NEXT: bx lr1350entry:1351 %0 = zext i16 %p to i321352 %1 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %0)1353 call void @llvm.arm.mve.vstr.scatter.offset.predicated.p0.v2i64.v2i64.v2i1(ptr %base, <2 x i64> %offset, <2 x i64> %value, i32 64, i32 0, <2 x i1> %1)1354 ret void1355}1356 1357define arm_aapcs_vfpcc void @test_vstrdq_scatter_offset_s64(ptr %base, <2 x i64> %offset, <2 x i64> %value) {1358; CHECK-LABEL: test_vstrdq_scatter_offset_s64:1359; CHECK: @ %bb.0: @ %entry1360; CHECK-NEXT: vstrd.64 q1, [r0, q0]1361; CHECK-NEXT: bx lr1362entry:1363 call void @llvm.arm.mve.vstr.scatter.offset.p0.v2i64.v2i64(ptr %base, <2 x i64> %offset, <2 x i64> %value, i32 64, i32 0)1364 ret void1365}1366 1367declare void @llvm.arm.mve.vstr.scatter.offset.p0.v2i64.v2i64(ptr, <2 x i64>, <2 x i64>, i32, i32)1368 1369define arm_aapcs_vfpcc void @test_vstrdq_scatter_offset_u64(ptr %base, <2 x i64> %offset, <2 x i64> %value) {1370; CHECK-LABEL: test_vstrdq_scatter_offset_u64:1371; CHECK: @ %bb.0: @ %entry1372; CHECK-NEXT: vstrd.64 q1, [r0, q0]1373; CHECK-NEXT: bx lr1374entry:1375 call void @llvm.arm.mve.vstr.scatter.offset.p0.v2i64.v2i64(ptr %base, <2 x i64> %offset, <2 x i64> %value, i32 64, i32 0)1376 ret void1377}1378 1379define arm_aapcs_vfpcc void @test_vstrdq_scatter_shifted_offset_p_s64(ptr %base, <2 x i64> %offset, <2 x i64> %value, i16 zeroext %p) {1380; CHECK-LABEL: test_vstrdq_scatter_shifted_offset_p_s64:1381; CHECK: @ %bb.0: @ %entry1382; CHECK-NEXT: vmsr p0, r11383; CHECK-NEXT: vpst1384; CHECK-NEXT: vstrdt.64 q1, [r0, q0, uxtw #3]1385; CHECK-NEXT: bx lr1386entry:1387 %0 = zext i16 %p to i321388 %1 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %0)1389 call void @llvm.arm.mve.vstr.scatter.offset.predicated.p0.v2i64.v2i64.v2i1(ptr %base, <2 x i64> %offset, <2 x i64> %value, i32 64, i32 3, <2 x i1> %1)1390 ret void1391}1392 1393define arm_aapcs_vfpcc void @test_vstrdq_scatter_shifted_offset_p_u64(ptr %base, <2 x i64> %offset, <2 x i64> %value, i16 zeroext %p) {1394; CHECK-LABEL: test_vstrdq_scatter_shifted_offset_p_u64:1395; CHECK: @ %bb.0: @ %entry1396; CHECK-NEXT: vmsr p0, r11397; CHECK-NEXT: vpst1398; CHECK-NEXT: vstrdt.64 q1, [r0, q0, uxtw #3]1399; CHECK-NEXT: bx lr1400entry:1401 %0 = zext i16 %p to i321402 %1 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %0)1403 call void @llvm.arm.mve.vstr.scatter.offset.predicated.p0.v2i64.v2i64.v2i1(ptr %base, <2 x i64> %offset, <2 x i64> %value, i32 64, i32 3, <2 x i1> %1)1404 ret void1405}1406 1407define arm_aapcs_vfpcc void @test_vstrdq_scatter_shifted_offset_s64(ptr %base, <2 x i64> %offset, <2 x i64> %value) {1408; CHECK-LABEL: test_vstrdq_scatter_shifted_offset_s64:1409; CHECK: @ %bb.0: @ %entry1410; CHECK-NEXT: vstrd.64 q1, [r0, q0, uxtw #3]1411; CHECK-NEXT: bx lr1412entry:1413 call void @llvm.arm.mve.vstr.scatter.offset.p0.v2i64.v2i64(ptr %base, <2 x i64> %offset, <2 x i64> %value, i32 64, i32 3)1414 ret void1415}1416 1417define arm_aapcs_vfpcc void @test_vstrdq_scatter_shifted_offset_u64(ptr %base, <2 x i64> %offset, <2 x i64> %value) {1418; CHECK-LABEL: test_vstrdq_scatter_shifted_offset_u64:1419; CHECK: @ %bb.0: @ %entry1420; CHECK-NEXT: vstrd.64 q1, [r0, q0, uxtw #3]1421; CHECK-NEXT: bx lr1422entry:1423 call void @llvm.arm.mve.vstr.scatter.offset.p0.v2i64.v2i64(ptr %base, <2 x i64> %offset, <2 x i64> %value, i32 64, i32 3)1424 ret void1425}1426 1427define arm_aapcs_vfpcc void @test_vstrhq_scatter_offset_f16(ptr %base, <8 x i16> %offset, <8 x half> %value) {1428; CHECK-LABEL: test_vstrhq_scatter_offset_f16:1429; CHECK: @ %bb.0: @ %entry1430; CHECK-NEXT: vstrh.16 q1, [r0, q0]1431; CHECK-NEXT: bx lr1432entry:1433 call void @llvm.arm.mve.vstr.scatter.offset.p0.v8i16.v8f16(ptr %base, <8 x i16> %offset, <8 x half> %value, i32 16, i32 0)1434 ret void1435}1436 1437declare void @llvm.arm.mve.vstr.scatter.offset.p0.v8i16.v8f16(ptr, <8 x i16>, <8 x half>, i32, i32)1438 1439define arm_aapcs_vfpcc void @test_vstrhq_scatter_offset_p_f16(ptr %base, <8 x i16> %offset, <8 x half> %value, i16 zeroext %p) {1440; CHECK-LABEL: test_vstrhq_scatter_offset_p_f16:1441; CHECK: @ %bb.0: @ %entry1442; CHECK-NEXT: vmsr p0, r11443; CHECK-NEXT: vpst1444; CHECK-NEXT: vstrht.16 q1, [r0, q0]1445; CHECK-NEXT: bx lr1446entry:1447 %0 = zext i16 %p to i321448 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)1449 call void @llvm.arm.mve.vstr.scatter.offset.predicated.p0.v8i16.v8f16.v8i1(ptr %base, <8 x i16> %offset, <8 x half> %value, i32 16, i32 0, <8 x i1> %1)1450 ret void1451}1452 1453declare void @llvm.arm.mve.vstr.scatter.offset.predicated.p0.v8i16.v8f16.v8i1(ptr, <8 x i16>, <8 x half>, i32, i32, <8 x i1>)1454 1455define arm_aapcs_vfpcc void @test_vstrhq_scatter_offset_p_s16(ptr %base, <8 x i16> %offset, <8 x i16> %value, i16 zeroext %p) {1456; CHECK-LABEL: test_vstrhq_scatter_offset_p_s16:1457; CHECK: @ %bb.0: @ %entry1458; CHECK-NEXT: vmsr p0, r11459; CHECK-NEXT: vpst1460; CHECK-NEXT: vstrht.16 q1, [r0, q0]1461; CHECK-NEXT: bx lr1462entry:1463 %0 = zext i16 %p to i321464 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)1465 call void @llvm.arm.mve.vstr.scatter.offset.predicated.p0.v8i16.v8i16.v8i1(ptr %base, <8 x i16> %offset, <8 x i16> %value, i32 16, i32 0, <8 x i1> %1)1466 ret void1467}1468 1469 1470define arm_aapcs_vfpcc void @test_vstrhq_scatter_offset_p_s32(ptr %base, <4 x i32> %offset, <4 x i32> %value, i16 zeroext %p) {1471; CHECK-LABEL: test_vstrhq_scatter_offset_p_s32:1472; CHECK: @ %bb.0: @ %entry1473; CHECK-NEXT: vmsr p0, r11474; CHECK-NEXT: vpst1475; CHECK-NEXT: vstrht.32 q1, [r0, q0]1476; CHECK-NEXT: bx lr1477entry:1478 %0 = zext i16 %p to i321479 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1480 call void @llvm.arm.mve.vstr.scatter.offset.predicated.p0.v4i32.v4i32.v4i1(ptr %base, <4 x i32> %offset, <4 x i32> %value, i32 16, i32 0, <4 x i1> %1)1481 ret void1482}1483 1484 1485define arm_aapcs_vfpcc void @test_vstrhq_scatter_offset_p_u16(ptr %base, <8 x i16> %offset, <8 x i16> %value, i16 zeroext %p) {1486; CHECK-LABEL: test_vstrhq_scatter_offset_p_u16:1487; CHECK: @ %bb.0: @ %entry1488; CHECK-NEXT: vmsr p0, r11489; CHECK-NEXT: vpst1490; CHECK-NEXT: vstrht.16 q1, [r0, q0]1491; CHECK-NEXT: bx lr1492entry:1493 %0 = zext i16 %p to i321494 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)1495 call void @llvm.arm.mve.vstr.scatter.offset.predicated.p0.v8i16.v8i16.v8i1(ptr %base, <8 x i16> %offset, <8 x i16> %value, i32 16, i32 0, <8 x i1> %1)1496 ret void1497}1498 1499define arm_aapcs_vfpcc void @test_vstrhq_scatter_offset_p_u32(ptr %base, <4 x i32> %offset, <4 x i32> %value, i16 zeroext %p) {1500; CHECK-LABEL: test_vstrhq_scatter_offset_p_u32:1501; CHECK: @ %bb.0: @ %entry1502; CHECK-NEXT: vmsr p0, r11503; CHECK-NEXT: vpst1504; CHECK-NEXT: vstrht.32 q1, [r0, q0]1505; CHECK-NEXT: bx lr1506entry:1507 %0 = zext i16 %p to i321508 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1509 call void @llvm.arm.mve.vstr.scatter.offset.predicated.p0.v4i32.v4i32.v4i1(ptr %base, <4 x i32> %offset, <4 x i32> %value, i32 16, i32 0, <4 x i1> %1)1510 ret void1511}1512 1513define arm_aapcs_vfpcc void @test_vstrhq_scatter_offset_s16(ptr %base, <8 x i16> %offset, <8 x i16> %value) {1514; CHECK-LABEL: test_vstrhq_scatter_offset_s16:1515; CHECK: @ %bb.0: @ %entry1516; CHECK-NEXT: vstrh.16 q1, [r0, q0]1517; CHECK-NEXT: bx lr1518entry:1519 call void @llvm.arm.mve.vstr.scatter.offset.p0.v8i16.v8i16(ptr %base, <8 x i16> %offset, <8 x i16> %value, i32 16, i32 0)1520 ret void1521}1522 1523 1524define arm_aapcs_vfpcc void @test_vstrhq_scatter_offset_s32(ptr %base, <4 x i32> %offset, <4 x i32> %value) {1525; CHECK-LABEL: test_vstrhq_scatter_offset_s32:1526; CHECK: @ %bb.0: @ %entry1527; CHECK-NEXT: vstrh.32 q1, [r0, q0]1528; CHECK-NEXT: bx lr1529entry:1530 call void @llvm.arm.mve.vstr.scatter.offset.p0.v4i32.v4i32(ptr %base, <4 x i32> %offset, <4 x i32> %value, i32 16, i32 0)1531 ret void1532}1533 1534 1535define arm_aapcs_vfpcc void @test_vstrhq_scatter_offset_u16(ptr %base, <8 x i16> %offset, <8 x i16> %value) {1536; CHECK-LABEL: test_vstrhq_scatter_offset_u16:1537; CHECK: @ %bb.0: @ %entry1538; CHECK-NEXT: vstrh.16 q1, [r0, q0]1539; CHECK-NEXT: bx lr1540entry:1541 call void @llvm.arm.mve.vstr.scatter.offset.p0.v8i16.v8i16(ptr %base, <8 x i16> %offset, <8 x i16> %value, i32 16, i32 0)1542 ret void1543}1544 1545define arm_aapcs_vfpcc void @test_vstrhq_scatter_offset_u32(ptr %base, <4 x i32> %offset, <4 x i32> %value) {1546; CHECK-LABEL: test_vstrhq_scatter_offset_u32:1547; CHECK: @ %bb.0: @ %entry1548; CHECK-NEXT: vstrh.32 q1, [r0, q0]1549; CHECK-NEXT: bx lr1550entry:1551 call void @llvm.arm.mve.vstr.scatter.offset.p0.v4i32.v4i32(ptr %base, <4 x i32> %offset, <4 x i32> %value, i32 16, i32 0)1552 ret void1553}1554 1555define arm_aapcs_vfpcc void @test_vstrhq_scatter_shifted_offset_f16(ptr %base, <8 x i16> %offset, <8 x half> %value) {1556; CHECK-LABEL: test_vstrhq_scatter_shifted_offset_f16:1557; CHECK: @ %bb.0: @ %entry1558; CHECK-NEXT: vstrh.16 q1, [r0, q0, uxtw #1]1559; CHECK-NEXT: bx lr1560entry:1561 call void @llvm.arm.mve.vstr.scatter.offset.p0.v8i16.v8f16(ptr %base, <8 x i16> %offset, <8 x half> %value, i32 16, i32 1)1562 ret void1563}1564 1565define arm_aapcs_vfpcc void @test_vstrhq_scatter_shifted_offset_p_f16(ptr %base, <8 x i16> %offset, <8 x half> %value, i16 zeroext %p) {1566; CHECK-LABEL: test_vstrhq_scatter_shifted_offset_p_f16:1567; CHECK: @ %bb.0: @ %entry1568; CHECK-NEXT: vmsr p0, r11569; CHECK-NEXT: vpst1570; CHECK-NEXT: vstrht.16 q1, [r0, q0, uxtw #1]1571; CHECK-NEXT: bx lr1572entry:1573 %0 = zext i16 %p to i321574 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)1575 call void @llvm.arm.mve.vstr.scatter.offset.predicated.p0.v8i16.v8f16.v8i1(ptr %base, <8 x i16> %offset, <8 x half> %value, i32 16, i32 1, <8 x i1> %1)1576 ret void1577}1578 1579define arm_aapcs_vfpcc void @test_vstrhq_scatter_shifted_offset_p_s16(ptr %base, <8 x i16> %offset, <8 x i16> %value, i16 zeroext %p) {1580; CHECK-LABEL: test_vstrhq_scatter_shifted_offset_p_s16:1581; CHECK: @ %bb.0: @ %entry1582; CHECK-NEXT: vmsr p0, r11583; CHECK-NEXT: vpst1584; CHECK-NEXT: vstrht.16 q1, [r0, q0, uxtw #1]1585; CHECK-NEXT: bx lr1586entry:1587 %0 = zext i16 %p to i321588 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)1589 call void @llvm.arm.mve.vstr.scatter.offset.predicated.p0.v8i16.v8i16.v8i1(ptr %base, <8 x i16> %offset, <8 x i16> %value, i32 16, i32 1, <8 x i1> %1)1590 ret void1591}1592 1593define arm_aapcs_vfpcc void @test_vstrhq_scatter_shifted_offset_p_s32(ptr %base, <4 x i32> %offset, <4 x i32> %value, i16 zeroext %p) {1594; CHECK-LABEL: test_vstrhq_scatter_shifted_offset_p_s32:1595; CHECK: @ %bb.0: @ %entry1596; CHECK-NEXT: vmsr p0, r11597; CHECK-NEXT: vpst1598; CHECK-NEXT: vstrht.32 q1, [r0, q0, uxtw #1]1599; CHECK-NEXT: bx lr1600entry:1601 %0 = zext i16 %p to i321602 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1603 call void @llvm.arm.mve.vstr.scatter.offset.predicated.p0.v4i32.v4i32.v4i1(ptr %base, <4 x i32> %offset, <4 x i32> %value, i32 16, i32 1, <4 x i1> %1)1604 ret void1605}1606 1607define arm_aapcs_vfpcc void @test_vstrhq_scatter_shifted_offset_p_u16(ptr %base, <8 x i16> %offset, <8 x i16> %value, i16 zeroext %p) {1608; CHECK-LABEL: test_vstrhq_scatter_shifted_offset_p_u16:1609; CHECK: @ %bb.0: @ %entry1610; CHECK-NEXT: vmsr p0, r11611; CHECK-NEXT: vpst1612; CHECK-NEXT: vstrht.16 q1, [r0, q0, uxtw #1]1613; CHECK-NEXT: bx lr1614entry:1615 %0 = zext i16 %p to i321616 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)1617 call void @llvm.arm.mve.vstr.scatter.offset.predicated.p0.v8i16.v8i16.v8i1(ptr %base, <8 x i16> %offset, <8 x i16> %value, i32 16, i32 1, <8 x i1> %1)1618 ret void1619}1620 1621define arm_aapcs_vfpcc void @test_vstrhq_scatter_shifted_offset_p_u32(ptr %base, <4 x i32> %offset, <4 x i32> %value, i16 zeroext %p) {1622; CHECK-LABEL: test_vstrhq_scatter_shifted_offset_p_u32:1623; CHECK: @ %bb.0: @ %entry1624; CHECK-NEXT: vmsr p0, r11625; CHECK-NEXT: vpst1626; CHECK-NEXT: vstrht.32 q1, [r0, q0, uxtw #1]1627; CHECK-NEXT: bx lr1628entry:1629 %0 = zext i16 %p to i321630 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1631 call void @llvm.arm.mve.vstr.scatter.offset.predicated.p0.v4i32.v4i32.v4i1(ptr %base, <4 x i32> %offset, <4 x i32> %value, i32 16, i32 1, <4 x i1> %1)1632 ret void1633}1634 1635define arm_aapcs_vfpcc void @test_vstrhq_scatter_shifted_offset_s16(ptr %base, <8 x i16> %offset, <8 x i16> %value) {1636; CHECK-LABEL: test_vstrhq_scatter_shifted_offset_s16:1637; CHECK: @ %bb.0: @ %entry1638; CHECK-NEXT: vstrh.16 q1, [r0, q0, uxtw #1]1639; CHECK-NEXT: bx lr1640entry:1641 call void @llvm.arm.mve.vstr.scatter.offset.p0.v8i16.v8i16(ptr %base, <8 x i16> %offset, <8 x i16> %value, i32 16, i32 1)1642 ret void1643}1644 1645define arm_aapcs_vfpcc void @test_vstrhq_scatter_shifted_offset_s32(ptr %base, <4 x i32> %offset, <4 x i32> %value) {1646; CHECK-LABEL: test_vstrhq_scatter_shifted_offset_s32:1647; CHECK: @ %bb.0: @ %entry1648; CHECK-NEXT: vstrh.32 q1, [r0, q0, uxtw #1]1649; CHECK-NEXT: bx lr1650entry:1651 call void @llvm.arm.mve.vstr.scatter.offset.p0.v4i32.v4i32(ptr %base, <4 x i32> %offset, <4 x i32> %value, i32 16, i32 1)1652 ret void1653}1654 1655define arm_aapcs_vfpcc void @test_vstrhq_scatter_shifted_offset_u16(ptr %base, <8 x i16> %offset, <8 x i16> %value) {1656; CHECK-LABEL: test_vstrhq_scatter_shifted_offset_u16:1657; CHECK: @ %bb.0: @ %entry1658; CHECK-NEXT: vstrh.16 q1, [r0, q0, uxtw #1]1659; CHECK-NEXT: bx lr1660entry:1661 call void @llvm.arm.mve.vstr.scatter.offset.p0.v8i16.v8i16(ptr %base, <8 x i16> %offset, <8 x i16> %value, i32 16, i32 1)1662 ret void1663}1664 1665define arm_aapcs_vfpcc void @test_vstrhq_scatter_shifted_offset_u32(ptr %base, <4 x i32> %offset, <4 x i32> %value) {1666; CHECK-LABEL: test_vstrhq_scatter_shifted_offset_u32:1667; CHECK: @ %bb.0: @ %entry1668; CHECK-NEXT: vstrh.32 q1, [r0, q0, uxtw #1]1669; CHECK-NEXT: bx lr1670entry:1671 call void @llvm.arm.mve.vstr.scatter.offset.p0.v4i32.v4i32(ptr %base, <4 x i32> %offset, <4 x i32> %value, i32 16, i32 1)1672 ret void1673}1674 1675define arm_aapcs_vfpcc void @test_vstrwq_scatter_base_f32(<4 x i32> %addr, <4 x float> %value) {1676; CHECK-LABEL: test_vstrwq_scatter_base_f32:1677; CHECK: @ %bb.0: @ %entry1678; CHECK-NEXT: vstrw.32 q1, [q0, #380]1679; CHECK-NEXT: bx lr1680entry:1681 call void @llvm.arm.mve.vstr.scatter.base.v4i32.v4f32(<4 x i32> %addr, i32 380, <4 x float> %value)1682 ret void1683}1684 1685declare void @llvm.arm.mve.vstr.scatter.base.v4i32.v4f32(<4 x i32>, i32, <4 x float>)1686 1687define arm_aapcs_vfpcc void @test_vstrwq_scatter_base_p_f32(<4 x i32> %addr, <4 x float> %value, i16 zeroext %p) {1688; CHECK-LABEL: test_vstrwq_scatter_base_p_f32:1689; CHECK: @ %bb.0: @ %entry1690; CHECK-NEXT: vmsr p0, r01691; CHECK-NEXT: vpst1692; CHECK-NEXT: vstrwt.32 q1, [q0, #-400]1693; CHECK-NEXT: bx lr1694entry:1695 %0 = zext i16 %p to i321696 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1697 call void @llvm.arm.mve.vstr.scatter.base.predicated.v4i32.v4f32.v4i1(<4 x i32> %addr, i32 -400, <4 x float> %value, <4 x i1> %1)1698 ret void1699}1700 1701declare void @llvm.arm.mve.vstr.scatter.base.predicated.v4i32.v4f32.v4i1(<4 x i32>, i32, <4 x float>, <4 x i1>)1702 1703define arm_aapcs_vfpcc void @test_vstrwq_scatter_base_p_s32(<4 x i32> %addr, <4 x i32> %value, i16 zeroext %p) {1704; CHECK-LABEL: test_vstrwq_scatter_base_p_s32:1705; CHECK: @ %bb.0: @ %entry1706; CHECK-NEXT: vmsr p0, r01707; CHECK-NEXT: vpst1708; CHECK-NEXT: vstrwt.32 q1, [q0, #48]1709; CHECK-NEXT: bx lr1710entry:1711 %0 = zext i16 %p to i321712 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1713 call void @llvm.arm.mve.vstr.scatter.base.predicated.v4i32.v4i32.v4i1(<4 x i32> %addr, i32 48, <4 x i32> %value, <4 x i1> %1)1714 ret void1715}1716 1717declare void @llvm.arm.mve.vstr.scatter.base.predicated.v4i32.v4i32.v4i1(<4 x i32>, i32, <4 x i32>, <4 x i1>)1718 1719define arm_aapcs_vfpcc void @test_vstrwq_scatter_base_p_u32(<4 x i32> %addr, <4 x i32> %value, i16 zeroext %p) {1720; CHECK-LABEL: test_vstrwq_scatter_base_p_u32:1721; CHECK: @ %bb.0: @ %entry1722; CHECK-NEXT: vmsr p0, r01723; CHECK-NEXT: vpst1724; CHECK-NEXT: vstrwt.32 q1, [q0, #-376]1725; CHECK-NEXT: bx lr1726entry:1727 %0 = zext i16 %p to i321728 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1729 call void @llvm.arm.mve.vstr.scatter.base.predicated.v4i32.v4i32.v4i1(<4 x i32> %addr, i32 -376, <4 x i32> %value, <4 x i1> %1)1730 ret void1731}1732 1733define arm_aapcs_vfpcc void @test_vstrwq_scatter_base_s32(<4 x i32> %addr, <4 x i32> %value) {1734; CHECK-LABEL: test_vstrwq_scatter_base_s32:1735; CHECK: @ %bb.0: @ %entry1736; CHECK-NEXT: vstrw.32 q1, [q0, #156]1737; CHECK-NEXT: bx lr1738entry:1739 call void @llvm.arm.mve.vstr.scatter.base.v4i32.v4i32(<4 x i32> %addr, i32 156, <4 x i32> %value)1740 ret void1741}1742 1743declare void @llvm.arm.mve.vstr.scatter.base.v4i32.v4i32(<4 x i32>, i32, <4 x i32>)1744 1745define arm_aapcs_vfpcc void @test_vstrwq_scatter_base_u32(<4 x i32> %addr, <4 x i32> %value) {1746; CHECK-LABEL: test_vstrwq_scatter_base_u32:1747; CHECK: @ %bb.0: @ %entry1748; CHECK-NEXT: vstrw.32 q1, [q0, #212]1749; CHECK-NEXT: bx lr1750entry:1751 call void @llvm.arm.mve.vstr.scatter.base.v4i32.v4i32(<4 x i32> %addr, i32 212, <4 x i32> %value)1752 ret void1753}1754 1755define arm_aapcs_vfpcc void @test_vstrwq_scatter_base_wb_f32(ptr %addr, <4 x float> %value) {1756; CHECK-LABEL: test_vstrwq_scatter_base_wb_f32:1757; CHECK: @ %bb.0: @ %entry1758; CHECK-NEXT: vldrw.u32 q1, [r0]1759; CHECK-NEXT: vstrw.32 q0, [q1, #-412]!1760; CHECK-NEXT: vstrw.32 q1, [r0]1761; CHECK-NEXT: bx lr1762entry:1763 %0 = load <4 x i32>, ptr %addr, align 81764 %1 = call <4 x i32> @llvm.arm.mve.vstr.scatter.base.wb.v4i32.v4f32(<4 x i32> %0, i32 -412, <4 x float> %value)1765 store <4 x i32> %1, ptr %addr, align 81766 ret void1767}1768 1769declare <4 x i32> @llvm.arm.mve.vstr.scatter.base.wb.v4i32.v4f32(<4 x i32>, i32, <4 x float>)1770 1771define arm_aapcs_vfpcc void @test_vstrwq_scatter_base_wb_p_f32(ptr %addr, <4 x float> %value, i16 zeroext %p) {1772; CHECK-LABEL: test_vstrwq_scatter_base_wb_p_f32:1773; CHECK: @ %bb.0: @ %entry1774; CHECK-NEXT: vldrw.u32 q1, [r0]1775; CHECK-NEXT: vmsr p0, r11776; CHECK-NEXT: vpst1777; CHECK-NEXT: vstrwt.32 q0, [q1, #236]!1778; CHECK-NEXT: vstrw.32 q1, [r0]1779; CHECK-NEXT: bx lr1780entry:1781 %0 = load <4 x i32>, ptr %addr, align 81782 %1 = zext i16 %p to i321783 %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)1784 %3 = call <4 x i32> @llvm.arm.mve.vstr.scatter.base.wb.predicated.v4i32.v4f32.v4i1(<4 x i32> %0, i32 236, <4 x float> %value, <4 x i1> %2)1785 store <4 x i32> %3, ptr %addr, align 81786 ret void1787}1788 1789declare <4 x i32> @llvm.arm.mve.vstr.scatter.base.wb.predicated.v4i32.v4f32.v4i1(<4 x i32>, i32, <4 x float>, <4 x i1>)1790 1791define arm_aapcs_vfpcc void @test_vstrwq_scatter_base_wb_p_s32(ptr %addr, <4 x i32> %value, i16 zeroext %p) {1792; CHECK-LABEL: test_vstrwq_scatter_base_wb_p_s32:1793; CHECK: @ %bb.0: @ %entry1794; CHECK-NEXT: vldrw.u32 q1, [r0]1795; CHECK-NEXT: vmsr p0, r11796; CHECK-NEXT: vpst1797; CHECK-NEXT: vstrwt.32 q0, [q1, #328]!1798; CHECK-NEXT: vstrw.32 q1, [r0]1799; CHECK-NEXT: bx lr1800entry:1801 %0 = load <4 x i32>, ptr %addr, align 81802 %1 = zext i16 %p to i321803 %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)1804 %3 = call <4 x i32> @llvm.arm.mve.vstr.scatter.base.wb.predicated.v4i32.v4i32.v4i1(<4 x i32> %0, i32 328, <4 x i32> %value, <4 x i1> %2)1805 store <4 x i32> %3, ptr %addr, align 81806 ret void1807}1808 1809declare <4 x i32> @llvm.arm.mve.vstr.scatter.base.wb.predicated.v4i32.v4i32.v4i1(<4 x i32>, i32, <4 x i32>, <4 x i1>)1810 1811define arm_aapcs_vfpcc void @test_vstrwq_scatter_base_wb_p_u32(ptr %addr, <4 x i32> %value, i16 zeroext %p) {1812; CHECK-LABEL: test_vstrwq_scatter_base_wb_p_u32:1813; CHECK: @ %bb.0: @ %entry1814; CHECK-NEXT: vldrw.u32 q1, [r0]1815; CHECK-NEXT: vmsr p0, r11816; CHECK-NEXT: vpst1817; CHECK-NEXT: vstrwt.32 q0, [q1, #412]!1818; CHECK-NEXT: vstrw.32 q1, [r0]1819; CHECK-NEXT: bx lr1820entry:1821 %0 = load <4 x i32>, ptr %addr, align 81822 %1 = zext i16 %p to i321823 %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)1824 %3 = call <4 x i32> @llvm.arm.mve.vstr.scatter.base.wb.predicated.v4i32.v4i32.v4i1(<4 x i32> %0, i32 412, <4 x i32> %value, <4 x i1> %2)1825 store <4 x i32> %3, ptr %addr, align 81826 ret void1827}1828 1829define arm_aapcs_vfpcc void @test_vstrwq_scatter_base_wb_s32(ptr %addr, <4 x i32> %value) {1830; CHECK-LABEL: test_vstrwq_scatter_base_wb_s32:1831; CHECK: @ %bb.0: @ %entry1832; CHECK-NEXT: vldrw.u32 q1, [r0]1833; CHECK-NEXT: vstrw.32 q0, [q1, #-152]!1834; CHECK-NEXT: vstrw.32 q1, [r0]1835; CHECK-NEXT: bx lr1836entry:1837 %0 = load <4 x i32>, ptr %addr, align 81838 %1 = call <4 x i32> @llvm.arm.mve.vstr.scatter.base.wb.v4i32.v4i32(<4 x i32> %0, i32 -152, <4 x i32> %value)1839 store <4 x i32> %1, ptr %addr, align 81840 ret void1841}1842 1843declare <4 x i32> @llvm.arm.mve.vstr.scatter.base.wb.v4i32.v4i32(<4 x i32>, i32, <4 x i32>)1844 1845define arm_aapcs_vfpcc void @test_vstrwq_scatter_base_wb_u32(ptr %addr, <4 x i32> %value) {1846; CHECK-LABEL: test_vstrwq_scatter_base_wb_u32:1847; CHECK: @ %bb.0: @ %entry1848; CHECK-NEXT: vldrw.u32 q1, [r0]1849; CHECK-NEXT: vstrw.32 q0, [q1, #64]!1850; CHECK-NEXT: vstrw.32 q1, [r0]1851; CHECK-NEXT: bx lr1852entry:1853 %0 = load <4 x i32>, ptr %addr, align 81854 %1 = call <4 x i32> @llvm.arm.mve.vstr.scatter.base.wb.v4i32.v4i32(<4 x i32> %0, i32 64, <4 x i32> %value)1855 store <4 x i32> %1, ptr %addr, align 81856 ret void1857}1858 1859define arm_aapcs_vfpcc void @test_vstrwq_scatter_offset_f32(ptr %base, <4 x i32> %offset, <4 x float> %value) {1860; CHECK-LABEL: test_vstrwq_scatter_offset_f32:1861; CHECK: @ %bb.0: @ %entry1862; CHECK-NEXT: vstrw.32 q1, [r0, q0]1863; CHECK-NEXT: bx lr1864entry:1865 call void @llvm.arm.mve.vstr.scatter.offset.p0.v4i32.v4f32(ptr %base, <4 x i32> %offset, <4 x float> %value, i32 32, i32 0)1866 ret void1867}1868 1869declare void @llvm.arm.mve.vstr.scatter.offset.p0.v4i32.v4f32(ptr, <4 x i32>, <4 x float>, i32, i32)1870 1871define arm_aapcs_vfpcc void @test_vstrwq_scatter_offset_p_f32(ptr %base, <4 x i32> %offset, <4 x float> %value, i16 zeroext %p) {1872; CHECK-LABEL: test_vstrwq_scatter_offset_p_f32:1873; CHECK: @ %bb.0: @ %entry1874; CHECK-NEXT: vmsr p0, r11875; CHECK-NEXT: vpst1876; CHECK-NEXT: vstrwt.32 q1, [r0, q0]1877; CHECK-NEXT: bx lr1878entry:1879 %0 = zext i16 %p to i321880 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1881 call void @llvm.arm.mve.vstr.scatter.offset.predicated.p0.v4i32.v4f32.v4i1(ptr %base, <4 x i32> %offset, <4 x float> %value, i32 32, i32 0, <4 x i1> %1)1882 ret void1883}1884 1885declare void @llvm.arm.mve.vstr.scatter.offset.predicated.p0.v4i32.v4f32.v4i1(ptr, <4 x i32>, <4 x float>, i32, i32, <4 x i1>)1886 1887define arm_aapcs_vfpcc void @test_vstrwq_scatter_offset_p_s32(ptr %base, <4 x i32> %offset, <4 x i32> %value, i16 zeroext %p) {1888; CHECK-LABEL: test_vstrwq_scatter_offset_p_s32:1889; CHECK: @ %bb.0: @ %entry1890; CHECK-NEXT: vmsr p0, r11891; CHECK-NEXT: vpst1892; CHECK-NEXT: vstrwt.32 q1, [r0, q0]1893; CHECK-NEXT: bx lr1894entry:1895 %0 = zext i16 %p to i321896 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1897 call void @llvm.arm.mve.vstr.scatter.offset.predicated.p0.v4i32.v4i32.v4i1(ptr %base, <4 x i32> %offset, <4 x i32> %value, i32 32, i32 0, <4 x i1> %1)1898 ret void1899}1900 1901 1902define arm_aapcs_vfpcc void @test_vstrwq_scatter_offset_p_u32(ptr %base, <4 x i32> %offset, <4 x i32> %value, i16 zeroext %p) {1903; CHECK-LABEL: test_vstrwq_scatter_offset_p_u32:1904; CHECK: @ %bb.0: @ %entry1905; CHECK-NEXT: vmsr p0, r11906; CHECK-NEXT: vpst1907; CHECK-NEXT: vstrwt.32 q1, [r0, q0]1908; CHECK-NEXT: bx lr1909entry:1910 %0 = zext i16 %p to i321911 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1912 call void @llvm.arm.mve.vstr.scatter.offset.predicated.p0.v4i32.v4i32.v4i1(ptr %base, <4 x i32> %offset, <4 x i32> %value, i32 32, i32 0, <4 x i1> %1)1913 ret void1914}1915 1916define arm_aapcs_vfpcc void @test_vstrwq_scatter_offset_s32(ptr %base, <4 x i32> %offset, <4 x i32> %value) {1917; CHECK-LABEL: test_vstrwq_scatter_offset_s32:1918; CHECK: @ %bb.0: @ %entry1919; CHECK-NEXT: vstrw.32 q1, [r0, q0]1920; CHECK-NEXT: bx lr1921entry:1922 call void @llvm.arm.mve.vstr.scatter.offset.p0.v4i32.v4i32(ptr %base, <4 x i32> %offset, <4 x i32> %value, i32 32, i32 0)1923 ret void1924}1925 1926 1927define arm_aapcs_vfpcc void @test_vstrwq_scatter_offset_u32(ptr %base, <4 x i32> %offset, <4 x i32> %value) {1928; CHECK-LABEL: test_vstrwq_scatter_offset_u32:1929; CHECK: @ %bb.0: @ %entry1930; CHECK-NEXT: vstrw.32 q1, [r0, q0]1931; CHECK-NEXT: bx lr1932entry:1933 call void @llvm.arm.mve.vstr.scatter.offset.p0.v4i32.v4i32(ptr %base, <4 x i32> %offset, <4 x i32> %value, i32 32, i32 0)1934 ret void1935}1936 1937define arm_aapcs_vfpcc void @test_vstrwq_scatter_shifted_offset_f32(ptr %base, <4 x i32> %offset, <4 x float> %value) {1938; CHECK-LABEL: test_vstrwq_scatter_shifted_offset_f32:1939; CHECK: @ %bb.0: @ %entry1940; CHECK-NEXT: vstrw.32 q1, [r0, q0, uxtw #2]1941; CHECK-NEXT: bx lr1942entry:1943 call void @llvm.arm.mve.vstr.scatter.offset.p0.v4i32.v4f32(ptr %base, <4 x i32> %offset, <4 x float> %value, i32 32, i32 2)1944 ret void1945}1946 1947define arm_aapcs_vfpcc void @test_vstrwq_scatter_shifted_offset_p_f32(ptr %base, <4 x i32> %offset, <4 x float> %value, i16 zeroext %p) {1948; CHECK-LABEL: test_vstrwq_scatter_shifted_offset_p_f32:1949; CHECK: @ %bb.0: @ %entry1950; CHECK-NEXT: vmsr p0, r11951; CHECK-NEXT: vpst1952; CHECK-NEXT: vstrwt.32 q1, [r0, q0, uxtw #2]1953; CHECK-NEXT: bx lr1954entry:1955 %0 = zext i16 %p to i321956 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1957 call void @llvm.arm.mve.vstr.scatter.offset.predicated.p0.v4i32.v4f32.v4i1(ptr %base, <4 x i32> %offset, <4 x float> %value, i32 32, i32 2, <4 x i1> %1)1958 ret void1959}1960 1961define arm_aapcs_vfpcc void @test_vstrwq_scatter_shifted_offset_p_s32(ptr %base, <4 x i32> %offset, <4 x i32> %value, i16 zeroext %p) {1962; CHECK-LABEL: test_vstrwq_scatter_shifted_offset_p_s32:1963; CHECK: @ %bb.0: @ %entry1964; CHECK-NEXT: vmsr p0, r11965; CHECK-NEXT: vpst1966; CHECK-NEXT: vstrwt.32 q1, [r0, q0, uxtw #2]1967; CHECK-NEXT: bx lr1968entry:1969 %0 = zext i16 %p to i321970 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1971 call void @llvm.arm.mve.vstr.scatter.offset.predicated.p0.v4i32.v4i32.v4i1(ptr %base, <4 x i32> %offset, <4 x i32> %value, i32 32, i32 2, <4 x i1> %1)1972 ret void1973}1974 1975define arm_aapcs_vfpcc void @test_vstrwq_scatter_shifted_offset_p_u32(ptr %base, <4 x i32> %offset, <4 x i32> %value, i16 zeroext %p) {1976; CHECK-LABEL: test_vstrwq_scatter_shifted_offset_p_u32:1977; CHECK: @ %bb.0: @ %entry1978; CHECK-NEXT: vmsr p0, r11979; CHECK-NEXT: vpst1980; CHECK-NEXT: vstrwt.32 q1, [r0, q0, uxtw #2]1981; CHECK-NEXT: bx lr1982entry:1983 %0 = zext i16 %p to i321984 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1985 call void @llvm.arm.mve.vstr.scatter.offset.predicated.p0.v4i32.v4i32.v4i1(ptr %base, <4 x i32> %offset, <4 x i32> %value, i32 32, i32 2, <4 x i1> %1)1986 ret void1987}1988 1989define arm_aapcs_vfpcc void @test_vstrwq_scatter_shifted_offset_s32(ptr %base, <4 x i32> %offset, <4 x i32> %value) {1990; CHECK-LABEL: test_vstrwq_scatter_shifted_offset_s32:1991; CHECK: @ %bb.0: @ %entry1992; CHECK-NEXT: vstrw.32 q1, [r0, q0, uxtw #2]1993; CHECK-NEXT: bx lr1994entry:1995 call void @llvm.arm.mve.vstr.scatter.offset.p0.v4i32.v4i32(ptr %base, <4 x i32> %offset, <4 x i32> %value, i32 32, i32 2)1996 ret void1997}1998 1999define arm_aapcs_vfpcc void @test_vstrwq_scatter_shifted_offset_u32(ptr %base, <4 x i32> %offset, <4 x i32> %value) {2000; CHECK-LABEL: test_vstrwq_scatter_shifted_offset_u32:2001; CHECK: @ %bb.0: @ %entry2002; CHECK-NEXT: vstrw.32 q1, [r0, q0, uxtw #2]2003; CHECK-NEXT: bx lr2004entry:2005 call void @llvm.arm.mve.vstr.scatter.offset.p0.v4i32.v4i32(ptr %base, <4 x i32> %offset, <4 x i32> %value, i32 32, i32 2)2006 ret void2007}2008