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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s3 4define arm_aapcs_vfpcc <8 x half> @test_vfmaq_f16(<8 x half> %a, <8 x half> %b, <8 x half> %c) {5; CHECK-LABEL: test_vfmaq_f16:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vfma.f16 q0, q1, q28; CHECK-NEXT: bx lr9entry:10 %0 = tail call <8 x half> @llvm.fma.v8f16(<8 x half> %b, <8 x half> %c, <8 x half> %a)11 ret <8 x half> %012}13 14define arm_aapcs_vfpcc <4 x float> @test_vfmaq_f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) {15; CHECK-LABEL: test_vfmaq_f32:16; CHECK: @ %bb.0: @ %entry17; CHECK-NEXT: vfma.f32 q0, q1, q218; CHECK-NEXT: bx lr19entry:20 %0 = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %b, <4 x float> %c, <4 x float> %a)21 ret <4 x float> %022}23 24define arm_aapcs_vfpcc <8 x half> @test_vfmaq_n_f16(<8 x half> %a, <8 x half> %b, float %c.coerce) {25; CHECK-LABEL: test_vfmaq_n_f16:26; CHECK: @ %bb.0: @ %entry27; CHECK-NEXT: vmov r0, s828; CHECK-NEXT: vfma.f16 q0, q1, r029; CHECK-NEXT: bx lr30entry:31 %0 = bitcast float %c.coerce to i3232 %tmp.0.extract.trunc = trunc i32 %0 to i1633 %1 = bitcast i16 %tmp.0.extract.trunc to half34 %.splatinsert = insertelement <8 x half> undef, half %1, i32 035 %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> undef, <8 x i32> zeroinitializer36 %2 = tail call <8 x half> @llvm.fma.v8f16(<8 x half> %b, <8 x half> %.splat, <8 x half> %a)37 ret <8 x half> %238}39 40define arm_aapcs_vfpcc <4 x float> @test_vfmaq_n_f32(<4 x float> %a, <4 x float> %b, float %c) {41; CHECK-LABEL: test_vfmaq_n_f32:42; CHECK: @ %bb.0: @ %entry43; CHECK-NEXT: vmov r0, s844; CHECK-NEXT: vfma.f32 q0, q1, r045; CHECK-NEXT: bx lr46entry:47 %.splatinsert = insertelement <4 x float> undef, float %c, i32 048 %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer49 %0 = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %b, <4 x float> %.splat, <4 x float> %a)50 ret <4 x float> %051}52 53define arm_aapcs_vfpcc <8 x half> @test_vfmasq_n_f16(<8 x half> %a, <8 x half> %b, float %c.coerce) {54; CHECK-LABEL: test_vfmasq_n_f16:55; CHECK: @ %bb.0: @ %entry56; CHECK-NEXT: vmov r0, s857; CHECK-NEXT: vfmas.f16 q0, q1, r058; CHECK-NEXT: bx lr59entry:60 %0 = bitcast float %c.coerce to i3261 %tmp.0.extract.trunc = trunc i32 %0 to i1662 %1 = bitcast i16 %tmp.0.extract.trunc to half63 %.splatinsert = insertelement <8 x half> undef, half %1, i32 064 %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> undef, <8 x i32> zeroinitializer65 %2 = tail call <8 x half> @llvm.fma.v8f16(<8 x half> %a, <8 x half> %b, <8 x half> %.splat)66 ret <8 x half> %267}68 69define arm_aapcs_vfpcc <4 x float> @test_vfmasq_n_f32(<4 x float> %a, <4 x float> %b, float %c) {70; CHECK-LABEL: test_vfmasq_n_f32:71; CHECK: @ %bb.0: @ %entry72; CHECK-NEXT: vmov r0, s873; CHECK-NEXT: vfmas.f32 q0, q1, r074; CHECK-NEXT: bx lr75entry:76 %.splatinsert = insertelement <4 x float> undef, float %c, i32 077 %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer78 %0 = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %.splat)79 ret <4 x float> %080}81 82define arm_aapcs_vfpcc <8 x half> @test_vfmsq_f16(<8 x half> %a, <8 x half> %b, <8 x half> %c) {83; CHECK-LABEL: test_vfmsq_f16:84; CHECK: @ %bb.0: @ %entry85; CHECK-NEXT: vfms.f16 q0, q2, q186; CHECK-NEXT: bx lr87entry:88 %0 = fneg <8 x half> %c89 %1 = tail call <8 x half> @llvm.fma.v8f16(<8 x half> %b, <8 x half> %0, <8 x half> %a)90 ret <8 x half> %191}92 93define arm_aapcs_vfpcc <4 x float> @test_vfmsq_f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) {94; CHECK-LABEL: test_vfmsq_f32:95; CHECK: @ %bb.0: @ %entry96; CHECK-NEXT: vfms.f32 q0, q2, q197; CHECK-NEXT: bx lr98entry:99 %0 = fneg <4 x float> %c100 %1 = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %b, <4 x float> %0, <4 x float> %a)101 ret <4 x float> %1102}103 104define arm_aapcs_vfpcc <16 x i8> @test_vmlaq_n_s8(<16 x i8> %a, <16 x i8> %b, i8 signext %c) {105; CHECK-LABEL: test_vmlaq_n_s8:106; CHECK: @ %bb.0: @ %entry107; CHECK-NEXT: vmla.i8 q0, q1, r0108; CHECK-NEXT: bx lr109entry:110 %.splatinsert = insertelement <16 x i8> undef, i8 %c, i32 0111 %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer112 %0 = mul <16 x i8> %.splat, %b113 %1 = add <16 x i8> %0, %a114 ret <16 x i8> %1115}116 117define arm_aapcs_vfpcc <8 x i16> @test_vmlaq_n_s16(<8 x i16> %a, <8 x i16> %b, i16 signext %c) {118; CHECK-LABEL: test_vmlaq_n_s16:119; CHECK: @ %bb.0: @ %entry120; CHECK-NEXT: vmla.i16 q0, q1, r0121; CHECK-NEXT: bx lr122entry:123 %.splatinsert = insertelement <8 x i16> undef, i16 %c, i32 0124 %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer125 %0 = mul <8 x i16> %.splat, %b126 %1 = add <8 x i16> %0, %a127 ret <8 x i16> %1128}129 130define arm_aapcs_vfpcc <4 x i32> @test_vmlaq_n_s32(<4 x i32> %a, <4 x i32> %b, i32 %c) {131; CHECK-LABEL: test_vmlaq_n_s32:132; CHECK: @ %bb.0: @ %entry133; CHECK-NEXT: vmla.i32 q0, q1, r0134; CHECK-NEXT: bx lr135entry:136 %.splatinsert = insertelement <4 x i32> undef, i32 %c, i32 0137 %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer138 %0 = mul <4 x i32> %.splat, %b139 %1 = add <4 x i32> %0, %a140 ret <4 x i32> %1141}142 143define arm_aapcs_vfpcc <16 x i8> @test_vmlaq_n_u8(<16 x i8> %a, <16 x i8> %b, i8 zeroext %c) {144; CHECK-LABEL: test_vmlaq_n_u8:145; CHECK: @ %bb.0: @ %entry146; CHECK-NEXT: vmla.i8 q0, q1, r0147; CHECK-NEXT: bx lr148entry:149 %.splatinsert = insertelement <16 x i8> undef, i8 %c, i32 0150 %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer151 %0 = mul <16 x i8> %.splat, %b152 %1 = add <16 x i8> %0, %a153 ret <16 x i8> %1154}155 156define arm_aapcs_vfpcc <8 x i16> @test_vmlaq_n_u16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %c) {157; CHECK-LABEL: test_vmlaq_n_u16:158; CHECK: @ %bb.0: @ %entry159; CHECK-NEXT: vmla.i16 q0, q1, r0160; CHECK-NEXT: bx lr161entry:162 %.splatinsert = insertelement <8 x i16> undef, i16 %c, i32 0163 %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer164 %0 = mul <8 x i16> %.splat, %b165 %1 = add <8 x i16> %0, %a166 ret <8 x i16> %1167}168 169define arm_aapcs_vfpcc <4 x i32> @test_vmlaq_n_u32(<4 x i32> %a, <4 x i32> %b, i32 %c) {170; CHECK-LABEL: test_vmlaq_n_u32:171; CHECK: @ %bb.0: @ %entry172; CHECK-NEXT: vmla.i32 q0, q1, r0173; CHECK-NEXT: bx lr174entry:175 %.splatinsert = insertelement <4 x i32> undef, i32 %c, i32 0176 %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer177 %0 = mul <4 x i32> %.splat, %b178 %1 = add <4 x i32> %0, %a179 ret <4 x i32> %1180}181 182define arm_aapcs_vfpcc <16 x i8> @test_vmlasq_n_s8(<16 x i8> %a, <16 x i8> %b, i8 signext %c) {183; CHECK-LABEL: test_vmlasq_n_s8:184; CHECK: @ %bb.0: @ %entry185; CHECK-NEXT: vmlas.i8 q1, q0, r0186; CHECK-NEXT: vmov q0, q1187; CHECK-NEXT: bx lr188entry:189 %0 = mul <16 x i8> %b, %a190 %.splatinsert = insertelement <16 x i8> undef, i8 %c, i32 0191 %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer192 %1 = add <16 x i8> %.splat, %0193 ret <16 x i8> %1194}195 196define arm_aapcs_vfpcc <8 x i16> @test_vmlasq_n_s16(<8 x i16> %a, <8 x i16> %b, i16 signext %c) {197; CHECK-LABEL: test_vmlasq_n_s16:198; CHECK: @ %bb.0: @ %entry199; CHECK-NEXT: vmlas.i16 q1, q0, r0200; CHECK-NEXT: vmov q0, q1201; CHECK-NEXT: bx lr202entry:203 %0 = mul <8 x i16> %b, %a204 %.splatinsert = insertelement <8 x i16> undef, i16 %c, i32 0205 %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer206 %1 = add <8 x i16> %.splat, %0207 ret <8 x i16> %1208}209 210define arm_aapcs_vfpcc <4 x i32> @test_vmlasq_n_s32(<4 x i32> %a, <4 x i32> %b, i32 %c) {211; CHECK-LABEL: test_vmlasq_n_s32:212; CHECK: @ %bb.0: @ %entry213; CHECK-NEXT: vmlas.i32 q1, q0, r0214; CHECK-NEXT: vmov q0, q1215; CHECK-NEXT: bx lr216entry:217 %0 = mul <4 x i32> %b, %a218 %.splatinsert = insertelement <4 x i32> undef, i32 %c, i32 0219 %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer220 %1 = add <4 x i32> %.splat, %0221 ret <4 x i32> %1222}223 224define arm_aapcs_vfpcc <16 x i8> @test_vmlasq_n_u8(<16 x i8> %a, <16 x i8> %b, i8 zeroext %c) {225; CHECK-LABEL: test_vmlasq_n_u8:226; CHECK: @ %bb.0: @ %entry227; CHECK-NEXT: vmlas.i8 q1, q0, r0228; CHECK-NEXT: vmov q0, q1229; CHECK-NEXT: bx lr230entry:231 %0 = mul <16 x i8> %b, %a232 %.splatinsert = insertelement <16 x i8> undef, i8 %c, i32 0233 %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer234 %1 = add <16 x i8> %.splat, %0235 ret <16 x i8> %1236}237 238define arm_aapcs_vfpcc <8 x i16> @test_vmlasq_n_u16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %c) {239; CHECK-LABEL: test_vmlasq_n_u16:240; CHECK: @ %bb.0: @ %entry241; CHECK-NEXT: vmlas.i16 q1, q0, r0242; CHECK-NEXT: vmov q0, q1243; CHECK-NEXT: bx lr244entry:245 %0 = mul <8 x i16> %b, %a246 %.splatinsert = insertelement <8 x i16> undef, i16 %c, i32 0247 %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer248 %1 = add <8 x i16> %.splat, %0249 ret <8 x i16> %1250}251 252define arm_aapcs_vfpcc <4 x i32> @test_vmlasq_n_u32(<4 x i32> %a, <4 x i32> %b, i32 %c) {253; CHECK-LABEL: test_vmlasq_n_u32:254; CHECK: @ %bb.0: @ %entry255; CHECK-NEXT: vmlas.i32 q1, q0, r0256; CHECK-NEXT: vmov q0, q1257; CHECK-NEXT: bx lr258entry:259 %0 = mul <4 x i32> %b, %a260 %.splatinsert = insertelement <4 x i32> undef, i32 %c, i32 0261 %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer262 %1 = add <4 x i32> %.splat, %0263 ret <4 x i32> %1264}265 266define arm_aapcs_vfpcc <16 x i8> @test_vqdmlahq_n_s8(<16 x i8> %a, <16 x i8> %b, i8 signext %c) {267; CHECK-LABEL: test_vqdmlahq_n_s8:268; CHECK: @ %bb.0: @ %entry269; CHECK-NEXT: vqdmlah.s8 q0, q1, r0270; CHECK-NEXT: bx lr271entry:272 %0 = zext i8 %c to i32273 %1 = tail call <16 x i8> @llvm.arm.mve.vqdmlah.v16i8(<16 x i8> %a, <16 x i8> %b, i32 %0)274 ret <16 x i8> %1275}276 277define arm_aapcs_vfpcc <8 x i16> @test_vqdmlahq_n_s16(<8 x i16> %a, <8 x i16> %b, i16 signext %c) {278; CHECK-LABEL: test_vqdmlahq_n_s16:279; CHECK: @ %bb.0: @ %entry280; CHECK-NEXT: vqdmlah.s16 q0, q1, r0281; CHECK-NEXT: bx lr282entry:283 %0 = zext i16 %c to i32284 %1 = tail call <8 x i16> @llvm.arm.mve.vqdmlah.v8i16(<8 x i16> %a, <8 x i16> %b, i32 %0)285 ret <8 x i16> %1286}287 288define arm_aapcs_vfpcc <4 x i32> @test_vqdmlahq_n_s32(<4 x i32> %a, <4 x i32> %b, i32 %c) {289; CHECK-LABEL: test_vqdmlahq_n_s32:290; CHECK: @ %bb.0: @ %entry291; CHECK-NEXT: vqdmlah.s32 q0, q1, r0292; CHECK-NEXT: bx lr293entry:294 %0 = tail call <4 x i32> @llvm.arm.mve.vqdmlah.v4i32(<4 x i32> %a, <4 x i32> %b, i32 %c)295 ret <4 x i32> %0296}297 298define arm_aapcs_vfpcc <16 x i8> @test_vqdmlashq_n_s8(<16 x i8> %m1, <16 x i8> %m2, i8 signext %add) {299; CHECK-LABEL: test_vqdmlashq_n_s8:300; CHECK: @ %bb.0: @ %entry301; CHECK-NEXT: vqdmlash.s8 q0, q1, r0302; CHECK-NEXT: bx lr303entry:304 %0 = zext i8 %add to i32305 %1 = tail call <16 x i8> @llvm.arm.mve.vqdmlash.v16i8(<16 x i8> %m1, <16 x i8> %m2, i32 %0)306 ret <16 x i8> %1307}308 309define arm_aapcs_vfpcc <8 x i16> @test_vqdmlashq_n_s16(<8 x i16> %m1, <8 x i16> %m2, i16 signext %add) {310; CHECK-LABEL: test_vqdmlashq_n_s16:311; CHECK: @ %bb.0: @ %entry312; CHECK-NEXT: vqdmlash.s16 q0, q1, r0313; CHECK-NEXT: bx lr314entry:315 %0 = zext i16 %add to i32316 %1 = tail call <8 x i16> @llvm.arm.mve.vqdmlash.v8i16(<8 x i16> %m1, <8 x i16> %m2, i32 %0)317 ret <8 x i16> %1318}319 320define arm_aapcs_vfpcc <4 x i32> @test_vqdmlashq_n_s32(<4 x i32> %m1, <4 x i32> %m2, i32 %add) {321; CHECK-LABEL: test_vqdmlashq_n_s32:322; CHECK: @ %bb.0: @ %entry323; CHECK-NEXT: vqdmlash.s32 q0, q1, r0324; CHECK-NEXT: bx lr325entry:326 %0 = tail call <4 x i32> @llvm.arm.mve.vqdmlash.v4i32(<4 x i32> %m1, <4 x i32> %m2, i32 %add)327 ret <4 x i32> %0328}329 330define arm_aapcs_vfpcc <16 x i8> @test_vqrdmlahq_n_s8(<16 x i8> %a, <16 x i8> %b, i8 signext %c) {331; CHECK-LABEL: test_vqrdmlahq_n_s8:332; CHECK: @ %bb.0: @ %entry333; CHECK-NEXT: vqrdmlah.s8 q0, q1, r0334; CHECK-NEXT: bx lr335entry:336 %0 = zext i8 %c to i32337 %1 = tail call <16 x i8> @llvm.arm.mve.vqrdmlah.v16i8(<16 x i8> %a, <16 x i8> %b, i32 %0)338 ret <16 x i8> %1339}340 341define arm_aapcs_vfpcc <8 x i16> @test_vqrdmlahq_n_s16(<8 x i16> %a, <8 x i16> %b, i16 signext %c) {342; CHECK-LABEL: test_vqrdmlahq_n_s16:343; CHECK: @ %bb.0: @ %entry344; CHECK-NEXT: vqrdmlah.s16 q0, q1, r0345; CHECK-NEXT: bx lr346entry:347 %0 = zext i16 %c to i32348 %1 = tail call <8 x i16> @llvm.arm.mve.vqrdmlah.v8i16(<8 x i16> %a, <8 x i16> %b, i32 %0)349 ret <8 x i16> %1350}351 352define arm_aapcs_vfpcc <4 x i32> @test_vqrdmlahq_n_s32(<4 x i32> %a, <4 x i32> %b, i32 %c) {353; CHECK-LABEL: test_vqrdmlahq_n_s32:354; CHECK: @ %bb.0: @ %entry355; CHECK-NEXT: vqrdmlah.s32 q0, q1, r0356; CHECK-NEXT: bx lr357entry:358 %0 = tail call <4 x i32> @llvm.arm.mve.vqrdmlah.v4i32(<4 x i32> %a, <4 x i32> %b, i32 %c)359 ret <4 x i32> %0360}361 362define arm_aapcs_vfpcc <16 x i8> @test_vqrdmlashq_n_s8(<16 x i8> %a, <16 x i8> %b, i8 signext %c) {363; CHECK-LABEL: test_vqrdmlashq_n_s8:364; CHECK: @ %bb.0: @ %entry365; CHECK-NEXT: vqrdmlash.s8 q0, q1, r0366; CHECK-NEXT: bx lr367entry:368 %0 = zext i8 %c to i32369 %1 = tail call <16 x i8> @llvm.arm.mve.vqrdmlash.v16i8(<16 x i8> %a, <16 x i8> %b, i32 %0)370 ret <16 x i8> %1371}372 373define arm_aapcs_vfpcc <8 x i16> @test_vqrdmlashq_n_s16(<8 x i16> %a, <8 x i16> %b, i16 signext %c) {374; CHECK-LABEL: test_vqrdmlashq_n_s16:375; CHECK: @ %bb.0: @ %entry376; CHECK-NEXT: vqrdmlash.s16 q0, q1, r0377; CHECK-NEXT: bx lr378entry:379 %0 = zext i16 %c to i32380 %1 = tail call <8 x i16> @llvm.arm.mve.vqrdmlash.v8i16(<8 x i16> %a, <8 x i16> %b, i32 %0)381 ret <8 x i16> %1382}383 384define arm_aapcs_vfpcc <4 x i32> @test_vqrdmlashq_n_s32(<4 x i32> %a, <4 x i32> %b, i32 %c) {385; CHECK-LABEL: test_vqrdmlashq_n_s32:386; CHECK: @ %bb.0: @ %entry387; CHECK-NEXT: vqrdmlash.s32 q0, q1, r0388; CHECK-NEXT: bx lr389entry:390 %0 = tail call <4 x i32> @llvm.arm.mve.vqrdmlash.v4i32(<4 x i32> %a, <4 x i32> %b, i32 %c)391 ret <4 x i32> %0392}393 394define arm_aapcs_vfpcc <8 x half> @test_vfmaq_m_f16(<8 x half> %a, <8 x half> %b, <8 x half> %c, i16 zeroext %p) {395; CHECK-LABEL: test_vfmaq_m_f16:396; CHECK: @ %bb.0: @ %entry397; CHECK-NEXT: vmsr p0, r0398; CHECK-NEXT: vpst399; CHECK-NEXT: vfmat.f16 q0, q1, q2400; CHECK-NEXT: bx lr401entry:402 %0 = zext i16 %p to i32403 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)404 %2 = tail call <8 x half> @llvm.arm.mve.fma.predicated.v8f16.v8i1(<8 x half> %b, <8 x half> %c, <8 x half> %a, <8 x i1> %1)405 ret <8 x half> %2406}407 408define arm_aapcs_vfpcc <4 x float> @test_vfmaq_m_f32(<4 x float> %a, <4 x float> %b, <4 x float> %c, i16 zeroext %p) {409; CHECK-LABEL: test_vfmaq_m_f32:410; CHECK: @ %bb.0: @ %entry411; CHECK-NEXT: vmsr p0, r0412; CHECK-NEXT: vpst413; CHECK-NEXT: vfmat.f32 q0, q1, q2414; CHECK-NEXT: bx lr415entry:416 %0 = zext i16 %p to i32417 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)418 %2 = tail call <4 x float> @llvm.arm.mve.fma.predicated.v4f32.v4i1(<4 x float> %b, <4 x float> %c, <4 x float> %a, <4 x i1> %1)419 ret <4 x float> %2420}421 422define arm_aapcs_vfpcc <8 x half> @test_vfmaq_m_n_f16(<8 x half> %a, <8 x half> %b, float %c.coerce, i16 zeroext %p) {423; CHECK-LABEL: test_vfmaq_m_n_f16:424; CHECK: @ %bb.0: @ %entry425; CHECK-NEXT: vmov r1, s8426; CHECK-NEXT: vmsr p0, r0427; CHECK-NEXT: vpst428; CHECK-NEXT: vfmat.f16 q0, q1, r1429; CHECK-NEXT: bx lr430entry:431 %0 = bitcast float %c.coerce to i32432 %tmp.0.extract.trunc = trunc i32 %0 to i16433 %1 = bitcast i16 %tmp.0.extract.trunc to half434 %.splatinsert = insertelement <8 x half> undef, half %1, i32 0435 %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> undef, <8 x i32> zeroinitializer436 %2 = zext i16 %p to i32437 %3 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)438 %4 = tail call <8 x half> @llvm.arm.mve.fma.predicated.v8f16.v8i1(<8 x half> %b, <8 x half> %.splat, <8 x half> %a, <8 x i1> %3)439 ret <8 x half> %4440}441 442define arm_aapcs_vfpcc <4 x float> @test_vfmaq_m_n_f32(<4 x float> %a, <4 x float> %b, float %c, i16 zeroext %p) {443; CHECK-LABEL: test_vfmaq_m_n_f32:444; CHECK: @ %bb.0: @ %entry445; CHECK-NEXT: vmov r1, s8446; CHECK-NEXT: vmsr p0, r0447; CHECK-NEXT: vpst448; CHECK-NEXT: vfmat.f32 q0, q1, r1449; CHECK-NEXT: bx lr450entry:451 %.splatinsert = insertelement <4 x float> undef, float %c, i32 0452 %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer453 %0 = zext i16 %p to i32454 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)455 %2 = tail call <4 x float> @llvm.arm.mve.fma.predicated.v4f32.v4i1(<4 x float> %b, <4 x float> %.splat, <4 x float> %a, <4 x i1> %1)456 ret <4 x float> %2457}458 459define arm_aapcs_vfpcc <8 x half> @test_vfmasq_m_n_f16(<8 x half> %a, <8 x half> %b, float %c.coerce, i16 zeroext %p) {460; CHECK-LABEL: test_vfmasq_m_n_f16:461; CHECK: @ %bb.0: @ %entry462; CHECK-NEXT: vmov r1, s8463; CHECK-NEXT: vmsr p0, r0464; CHECK-NEXT: vdup.16 q2, r1465; CHECK-NEXT: vpst466; CHECK-NEXT: vfmat.f16 q2, q0, q1467; CHECK-NEXT: vmov q0, q2468; CHECK-NEXT: bx lr469entry:470 %0 = bitcast float %c.coerce to i32471 %tmp.0.extract.trunc = trunc i32 %0 to i16472 %1 = bitcast i16 %tmp.0.extract.trunc to half473 %.splatinsert = insertelement <8 x half> undef, half %1, i32 0474 %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> undef, <8 x i32> zeroinitializer475 %2 = zext i16 %p to i32476 %3 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)477 %4 = tail call <8 x half> @llvm.arm.mve.fma.predicated.v8f16.v8i1(<8 x half> %a, <8 x half> %b, <8 x half> %.splat, <8 x i1> %3)478 ret <8 x half> %4479}480 481define arm_aapcs_vfpcc <8 x half> @test_vfmasq_m_n_f16_select(<8 x half> %a, <8 x half> %b, float %c.coerce, i16 zeroext %p) {482; CHECK-LABEL: test_vfmasq_m_n_f16_select:483; CHECK: @ %bb.0: @ %entry484; CHECK-NEXT: vmov r1, s8485; CHECK-NEXT: vmsr p0, r0486; CHECK-NEXT: vpst487; CHECK-NEXT: vfmast.f16 q0, q1, r1488; CHECK-NEXT: bx lr489entry:490 %0 = bitcast float %c.coerce to i32491 %tmp.0.extract.trunc = trunc i32 %0 to i16492 %1 = bitcast i16 %tmp.0.extract.trunc to half493 %.splatinsert = insertelement <8 x half> undef, half %1, i32 0494 %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> undef, <8 x i32> zeroinitializer495 %2 = zext i16 %p to i32496 %3 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)497 %4 = tail call <8 x half> @llvm.fma.v8f16(<8 x half> %a, <8 x half> %b, <8 x half> %.splat)498 %5 = select <8 x i1> %3, <8 x half> %4, <8 x half> %a499 ret <8 x half> %5500}501 502define arm_aapcs_vfpcc <4 x float> @test_vfmasq_m_n_f32(<4 x float> %a, <4 x float> %b, float %c, i16 zeroext %p) {503; CHECK-LABEL: test_vfmasq_m_n_f32:504; CHECK: @ %bb.0: @ %entry505; CHECK-NEXT: vmov r1, s8506; CHECK-NEXT: vmsr p0, r0507; CHECK-NEXT: vdup.32 q2, r1508; CHECK-NEXT: vpst509; CHECK-NEXT: vfmat.f32 q2, q0, q1510; CHECK-NEXT: vmov q0, q2511; CHECK-NEXT: bx lr512entry:513 %.splatinsert = insertelement <4 x float> undef, float %c, i32 0514 %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer515 %0 = zext i16 %p to i32516 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)517 %2 = tail call <4 x float> @llvm.arm.mve.fma.predicated.v4f32.v4i1(<4 x float> %a, <4 x float> %b, <4 x float> %.splat, <4 x i1> %1)518 ret <4 x float> %2519}520 521define arm_aapcs_vfpcc <4 x float> @test_vfmasq_m_n_f32_select(<4 x float> %a, <4 x float> %b, float %c, i16 zeroext %p) {522; CHECK-LABEL: test_vfmasq_m_n_f32_select:523; CHECK: @ %bb.0: @ %entry524; CHECK-NEXT: vmov r1, s8525; CHECK-NEXT: vmsr p0, r0526; CHECK-NEXT: vpst527; CHECK-NEXT: vfmast.f32 q0, q1, r1528; CHECK-NEXT: bx lr529entry:530 %.splatinsert = insertelement <4 x float> undef, float %c, i32 0531 %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer532 %0 = zext i16 %p to i32533 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)534 %2 = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %.splat)535 %3 = select <4 x i1> %1, <4 x float> %2, <4 x float> %a536 ret <4 x float> %3537}538 539define arm_aapcs_vfpcc <8 x half> @test_vfmsq_m_f16(<8 x half> %a, <8 x half> %b, <8 x half> %c, i16 zeroext %p) {540; CHECK-LABEL: test_vfmsq_m_f16:541; CHECK: @ %bb.0: @ %entry542; CHECK-NEXT: vmsr p0, r0543; CHECK-NEXT: vpst544; CHECK-NEXT: vfmst.f16 q0, q1, q2545; CHECK-NEXT: bx lr546entry:547 %0 = fneg <8 x half> %c548 %1 = zext i16 %p to i32549 %2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)550 %3 = tail call <8 x half> @llvm.arm.mve.fma.predicated.v8f16.v8i1(<8 x half> %b, <8 x half> %0, <8 x half> %a, <8 x i1> %2)551 ret <8 x half> %3552}553 554define arm_aapcs_vfpcc <4 x float> @test_vfmsq_m_f32(<4 x float> %a, <4 x float> %b, <4 x float> %c, i16 zeroext %p) {555; CHECK-LABEL: test_vfmsq_m_f32:556; CHECK: @ %bb.0: @ %entry557; CHECK-NEXT: vmsr p0, r0558; CHECK-NEXT: vpst559; CHECK-NEXT: vfmst.f32 q0, q1, q2560; CHECK-NEXT: bx lr561entry:562 %0 = fneg <4 x float> %c563 %1 = zext i16 %p to i32564 %2 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)565 %3 = tail call <4 x float> @llvm.arm.mve.fma.predicated.v4f32.v4i1(<4 x float> %b, <4 x float> %0, <4 x float> %a, <4 x i1> %2)566 ret <4 x float> %3567}568 569define arm_aapcs_vfpcc <16 x i8> @test_vmlaq_m_n_s8(<16 x i8> %a, <16 x i8> %b, i8 signext %c, i16 zeroext %p) {570; CHECK-LABEL: test_vmlaq_m_n_s8:571; CHECK: @ %bb.0: @ %entry572; CHECK-NEXT: vmsr p0, r1573; CHECK-NEXT: vpst574; CHECK-NEXT: vmlat.i8 q0, q1, r0575; CHECK-NEXT: bx lr576entry:577 %0 = zext i8 %c to i32578 %1 = zext i16 %p to i32579 %2 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)580 %3 = tail call <16 x i8> @llvm.arm.mve.vmla.n.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 %0, <16 x i1> %2)581 ret <16 x i8> %3582}583 584define arm_aapcs_vfpcc <8 x i16> @test_vmlaq_m_n_s16(<8 x i16> %a, <8 x i16> %b, i16 signext %c, i16 zeroext %p) {585; CHECK-LABEL: test_vmlaq_m_n_s16:586; CHECK: @ %bb.0: @ %entry587; CHECK-NEXT: vmsr p0, r1588; CHECK-NEXT: vpst589; CHECK-NEXT: vmlat.i16 q0, q1, r0590; CHECK-NEXT: bx lr591entry:592 %0 = zext i16 %c to i32593 %1 = zext i16 %p to i32594 %2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)595 %3 = tail call <8 x i16> @llvm.arm.mve.vmla.n.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 %0, <8 x i1> %2)596 ret <8 x i16> %3597}598 599define arm_aapcs_vfpcc <4 x i32> @test_vmlaq_m_n_s32(<4 x i32> %a, <4 x i32> %b, i32 %c, i16 zeroext %p) {600; CHECK-LABEL: test_vmlaq_m_n_s32:601; CHECK: @ %bb.0: @ %entry602; CHECK-NEXT: vmsr p0, r1603; CHECK-NEXT: vpst604; CHECK-NEXT: vmlat.i32 q0, q1, r0605; CHECK-NEXT: bx lr606entry:607 %0 = zext i16 %p to i32608 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)609 %2 = tail call <4 x i32> @llvm.arm.mve.vmla.n.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c, <4 x i1> %1)610 ret <4 x i32> %2611}612 613define arm_aapcs_vfpcc <16 x i8> @test_vmlaq_m_n_u8(<16 x i8> %a, <16 x i8> %b, i8 zeroext %c, i16 zeroext %p) {614; CHECK-LABEL: test_vmlaq_m_n_u8:615; CHECK: @ %bb.0: @ %entry616; CHECK-NEXT: vmsr p0, r1617; CHECK-NEXT: vpst618; CHECK-NEXT: vmlat.i8 q0, q1, r0619; CHECK-NEXT: bx lr620entry:621 %0 = zext i8 %c to i32622 %1 = zext i16 %p to i32623 %2 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)624 %3 = tail call <16 x i8> @llvm.arm.mve.vmla.n.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 %0, <16 x i1> %2)625 ret <16 x i8> %3626}627 628define arm_aapcs_vfpcc <8 x i16> @test_vmlaq_m_n_u16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %c, i16 zeroext %p) {629; CHECK-LABEL: test_vmlaq_m_n_u16:630; CHECK: @ %bb.0: @ %entry631; CHECK-NEXT: vmsr p0, r1632; CHECK-NEXT: vpst633; CHECK-NEXT: vmlat.i16 q0, q1, r0634; CHECK-NEXT: bx lr635entry:636 %0 = zext i16 %c to i32637 %1 = zext i16 %p to i32638 %2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)639 %3 = tail call <8 x i16> @llvm.arm.mve.vmla.n.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 %0, <8 x i1> %2)640 ret <8 x i16> %3641}642 643define arm_aapcs_vfpcc <4 x i32> @test_vmlaq_m_n_u32(<4 x i32> %a, <4 x i32> %b, i32 %c, i16 zeroext %p) {644; CHECK-LABEL: test_vmlaq_m_n_u32:645; CHECK: @ %bb.0: @ %entry646; CHECK-NEXT: vmsr p0, r1647; CHECK-NEXT: vpst648; CHECK-NEXT: vmlat.i32 q0, q1, r0649; CHECK-NEXT: bx lr650entry:651 %0 = zext i16 %p to i32652 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)653 %2 = tail call <4 x i32> @llvm.arm.mve.vmla.n.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c, <4 x i1> %1)654 ret <4 x i32> %2655}656 657define arm_aapcs_vfpcc <16 x i8> @test_vmlasq_m_n_s8(<16 x i8> %a, <16 x i8> %b, i8 signext %c, i16 zeroext %p) {658; CHECK-LABEL: test_vmlasq_m_n_s8:659; CHECK: @ %bb.0: @ %entry660; CHECK-NEXT: vmsr p0, r1661; CHECK-NEXT: vpst662; CHECK-NEXT: vmlast.i8 q0, q1, r0663; CHECK-NEXT: bx lr664entry:665 %0 = zext i8 %c to i32666 %1 = zext i16 %p to i32667 %2 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)668 %3 = tail call <16 x i8> @llvm.arm.mve.vmlas.n.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 %0, <16 x i1> %2)669 ret <16 x i8> %3670}671 672define arm_aapcs_vfpcc <8 x i16> @test_vmlasq_m_n_s16(<8 x i16> %a, <8 x i16> %b, i16 signext %c, i16 zeroext %p) {673; CHECK-LABEL: test_vmlasq_m_n_s16:674; CHECK: @ %bb.0: @ %entry675; CHECK-NEXT: vmsr p0, r1676; CHECK-NEXT: vpst677; CHECK-NEXT: vmlast.i16 q0, q1, r0678; CHECK-NEXT: bx lr679entry:680 %0 = zext i16 %c to i32681 %1 = zext i16 %p to i32682 %2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)683 %3 = tail call <8 x i16> @llvm.arm.mve.vmlas.n.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 %0, <8 x i1> %2)684 ret <8 x i16> %3685}686 687define arm_aapcs_vfpcc <4 x i32> @test_vmlasq_m_n_s32(<4 x i32> %a, <4 x i32> %b, i32 %c, i16 zeroext %p) {688; CHECK-LABEL: test_vmlasq_m_n_s32:689; CHECK: @ %bb.0: @ %entry690; CHECK-NEXT: vmsr p0, r1691; CHECK-NEXT: vpst692; CHECK-NEXT: vmlast.i32 q0, q1, r0693; CHECK-NEXT: bx lr694entry:695 %0 = zext i16 %p to i32696 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)697 %2 = tail call <4 x i32> @llvm.arm.mve.vmlas.n.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c, <4 x i1> %1)698 ret <4 x i32> %2699}700 701define arm_aapcs_vfpcc <16 x i8> @test_vmlasq_m_n_u8(<16 x i8> %a, <16 x i8> %b, i8 zeroext %c, i16 zeroext %p) {702; CHECK-LABEL: test_vmlasq_m_n_u8:703; CHECK: @ %bb.0: @ %entry704; CHECK-NEXT: vmsr p0, r1705; CHECK-NEXT: vpst706; CHECK-NEXT: vmlast.i8 q0, q1, r0707; CHECK-NEXT: bx lr708entry:709 %0 = zext i8 %c to i32710 %1 = zext i16 %p to i32711 %2 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)712 %3 = tail call <16 x i8> @llvm.arm.mve.vmlas.n.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 %0, <16 x i1> %2)713 ret <16 x i8> %3714}715 716define arm_aapcs_vfpcc <8 x i16> @test_vmlasq_m_n_u16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %c, i16 zeroext %p) {717; CHECK-LABEL: test_vmlasq_m_n_u16:718; CHECK: @ %bb.0: @ %entry719; CHECK-NEXT: vmsr p0, r1720; CHECK-NEXT: vpst721; CHECK-NEXT: vmlast.i16 q0, q1, r0722; CHECK-NEXT: bx lr723entry:724 %0 = zext i16 %c to i32725 %1 = zext i16 %p to i32726 %2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)727 %3 = tail call <8 x i16> @llvm.arm.mve.vmlas.n.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 %0, <8 x i1> %2)728 ret <8 x i16> %3729}730 731define arm_aapcs_vfpcc <4 x i32> @test_vmlasq_m_n_u32(<4 x i32> %a, <4 x i32> %b, i32 %c, i16 zeroext %p) {732; CHECK-LABEL: test_vmlasq_m_n_u32:733; CHECK: @ %bb.0: @ %entry734; CHECK-NEXT: vmsr p0, r1735; CHECK-NEXT: vpst736; CHECK-NEXT: vmlast.i32 q0, q1, r0737; CHECK-NEXT: bx lr738entry:739 %0 = zext i16 %p to i32740 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)741 %2 = tail call <4 x i32> @llvm.arm.mve.vmlas.n.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c, <4 x i1> %1)742 ret <4 x i32> %2743}744 745define arm_aapcs_vfpcc <16 x i8> @test_vqdmlahq_m_n_s8(<16 x i8> %a, <16 x i8> %b, i8 signext %c, i16 zeroext %p) {746; CHECK-LABEL: test_vqdmlahq_m_n_s8:747; CHECK: @ %bb.0: @ %entry748; CHECK-NEXT: vmsr p0, r1749; CHECK-NEXT: vpst750; CHECK-NEXT: vqdmlaht.s8 q0, q1, r0751; CHECK-NEXT: bx lr752entry:753 %0 = zext i8 %c to i32754 %1 = zext i16 %p to i32755 %2 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)756 %3 = tail call <16 x i8> @llvm.arm.mve.vqdmlah.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 %0, <16 x i1> %2)757 ret <16 x i8> %3758}759 760define arm_aapcs_vfpcc <8 x i16> @test_vqdmlahq_m_n_s16(<8 x i16> %a, <8 x i16> %b, i16 signext %c, i16 zeroext %p) {761; CHECK-LABEL: test_vqdmlahq_m_n_s16:762; CHECK: @ %bb.0: @ %entry763; CHECK-NEXT: vmsr p0, r1764; CHECK-NEXT: vpst765; CHECK-NEXT: vqdmlaht.s16 q0, q1, r0766; CHECK-NEXT: bx lr767entry:768 %0 = zext i16 %c to i32769 %1 = zext i16 %p to i32770 %2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)771 %3 = tail call <8 x i16> @llvm.arm.mve.vqdmlah.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 %0, <8 x i1> %2)772 ret <8 x i16> %3773}774 775define arm_aapcs_vfpcc <4 x i32> @test_vqdmlahq_m_n_s32(<4 x i32> %a, <4 x i32> %b, i32 %c, i16 zeroext %p) {776; CHECK-LABEL: test_vqdmlahq_m_n_s32:777; CHECK: @ %bb.0: @ %entry778; CHECK-NEXT: vmsr p0, r1779; CHECK-NEXT: vpst780; CHECK-NEXT: vqdmlaht.s32 q0, q1, r0781; CHECK-NEXT: bx lr782entry:783 %0 = zext i16 %p to i32784 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)785 %2 = tail call <4 x i32> @llvm.arm.mve.vqdmlah.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c, <4 x i1> %1)786 ret <4 x i32> %2787}788 789define arm_aapcs_vfpcc <16 x i8> @test_vqdmlashq_m_n_s8(<16 x i8> %m1, <16 x i8> %m2, i8 signext %add, i16 zeroext %p) {790; CHECK-LABEL: test_vqdmlashq_m_n_s8:791; CHECK: @ %bb.0: @ %entry792; CHECK-NEXT: vmsr p0, r1793; CHECK-NEXT: vpst794; CHECK-NEXT: vqdmlasht.s8 q0, q1, r0795; CHECK-NEXT: bx lr796entry:797 %0 = zext i8 %add to i32798 %1 = zext i16 %p to i32799 %2 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)800 %3 = tail call <16 x i8> @llvm.arm.mve.vqdmlash.predicated.v16i8.v16i1(<16 x i8> %m1, <16 x i8> %m2, i32 %0, <16 x i1> %2)801 ret <16 x i8> %3802}803 804define arm_aapcs_vfpcc <8 x i16> @test_vqdmlashq_m_n_s16(<8 x i16> %m1, <8 x i16> %m2, i16 signext %add, i16 zeroext %p) {805; CHECK-LABEL: test_vqdmlashq_m_n_s16:806; CHECK: @ %bb.0: @ %entry807; CHECK-NEXT: vmsr p0, r1808; CHECK-NEXT: vpst809; CHECK-NEXT: vqdmlasht.s16 q0, q1, r0810; CHECK-NEXT: bx lr811entry:812 %0 = zext i16 %add to i32813 %1 = zext i16 %p to i32814 %2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)815 %3 = tail call <8 x i16> @llvm.arm.mve.vqdmlash.predicated.v8i16.v8i1(<8 x i16> %m1, <8 x i16> %m2, i32 %0, <8 x i1> %2)816 ret <8 x i16> %3817}818 819define arm_aapcs_vfpcc <4 x i32> @test_vqdmlashq_m_n_s32(<4 x i32> %m1, <4 x i32> %m2, i32 %add, i16 zeroext %p) {820; CHECK-LABEL: test_vqdmlashq_m_n_s32:821; CHECK: @ %bb.0: @ %entry822; CHECK-NEXT: vmsr p0, r1823; CHECK-NEXT: vpst824; CHECK-NEXT: vqdmlasht.s32 q0, q1, r0825; CHECK-NEXT: bx lr826entry:827 %0 = zext i16 %p to i32828 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)829 %2 = tail call <4 x i32> @llvm.arm.mve.vqdmlash.predicated.v4i32.v4i1(<4 x i32> %m1, <4 x i32> %m2, i32 %add, <4 x i1> %1)830 ret <4 x i32> %2831}832 833define arm_aapcs_vfpcc <16 x i8> @test_vqrdmlahq_m_n_s8(<16 x i8> %a, <16 x i8> %b, i8 signext %c, i16 zeroext %p) {834; CHECK-LABEL: test_vqrdmlahq_m_n_s8:835; CHECK: @ %bb.0: @ %entry836; CHECK-NEXT: vmsr p0, r1837; CHECK-NEXT: vpst838; CHECK-NEXT: vqrdmlaht.s8 q0, q1, r0839; CHECK-NEXT: bx lr840entry:841 %0 = zext i8 %c to i32842 %1 = zext i16 %p to i32843 %2 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)844 %3 = tail call <16 x i8> @llvm.arm.mve.vqrdmlah.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 %0, <16 x i1> %2)845 ret <16 x i8> %3846}847 848define arm_aapcs_vfpcc <8 x i16> @test_vqrdmlahq_m_n_s16(<8 x i16> %a, <8 x i16> %b, i16 signext %c, i16 zeroext %p) {849; CHECK-LABEL: test_vqrdmlahq_m_n_s16:850; CHECK: @ %bb.0: @ %entry851; CHECK-NEXT: vmsr p0, r1852; CHECK-NEXT: vpst853; CHECK-NEXT: vqrdmlaht.s16 q0, q1, r0854; CHECK-NEXT: bx lr855entry:856 %0 = zext i16 %c to i32857 %1 = zext i16 %p to i32858 %2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)859 %3 = tail call <8 x i16> @llvm.arm.mve.vqrdmlah.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 %0, <8 x i1> %2)860 ret <8 x i16> %3861}862 863define arm_aapcs_vfpcc <4 x i32> @test_vqrdmlahq_m_n_s32(<4 x i32> %a, <4 x i32> %b, i32 %c, i16 zeroext %p) {864; CHECK-LABEL: test_vqrdmlahq_m_n_s32:865; CHECK: @ %bb.0: @ %entry866; CHECK-NEXT: vmsr p0, r1867; CHECK-NEXT: vpst868; CHECK-NEXT: vqrdmlaht.s32 q0, q1, r0869; CHECK-NEXT: bx lr870entry:871 %0 = zext i16 %p to i32872 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)873 %2 = tail call <4 x i32> @llvm.arm.mve.vqrdmlah.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c, <4 x i1> %1)874 ret <4 x i32> %2875}876 877define arm_aapcs_vfpcc <16 x i8> @test_vqrdmlashq_m_n_s8(<16 x i8> %a, <16 x i8> %b, i8 signext %c, i16 zeroext %p) {878; CHECK-LABEL: test_vqrdmlashq_m_n_s8:879; CHECK: @ %bb.0: @ %entry880; CHECK-NEXT: vmsr p0, r1881; CHECK-NEXT: vpst882; CHECK-NEXT: vqrdmlasht.s8 q0, q1, r0883; CHECK-NEXT: bx lr884entry:885 %0 = zext i8 %c to i32886 %1 = zext i16 %p to i32887 %2 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)888 %3 = tail call <16 x i8> @llvm.arm.mve.vqrdmlash.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 %0, <16 x i1> %2)889 ret <16 x i8> %3890}891 892define arm_aapcs_vfpcc <8 x i16> @test_vqrdmlashq_m_n_s16(<8 x i16> %a, <8 x i16> %b, i16 signext %c, i16 zeroext %p) {893; CHECK-LABEL: test_vqrdmlashq_m_n_s16:894; CHECK: @ %bb.0: @ %entry895; CHECK-NEXT: vmsr p0, r1896; CHECK-NEXT: vpst897; CHECK-NEXT: vqrdmlasht.s16 q0, q1, r0898; CHECK-NEXT: bx lr899entry:900 %0 = zext i16 %c to i32901 %1 = zext i16 %p to i32902 %2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)903 %3 = tail call <8 x i16> @llvm.arm.mve.vqrdmlash.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 %0, <8 x i1> %2)904 ret <8 x i16> %3905}906 907define arm_aapcs_vfpcc <4 x i32> @test_vqrdmlashq_m_n_s32(<4 x i32> %a, <4 x i32> %b, i32 %c, i16 zeroext %p) {908; CHECK-LABEL: test_vqrdmlashq_m_n_s32:909; CHECK: @ %bb.0: @ %entry910; CHECK-NEXT: vmsr p0, r1911; CHECK-NEXT: vpst912; CHECK-NEXT: vqrdmlasht.s32 q0, q1, r0913; CHECK-NEXT: bx lr914entry:915 %0 = zext i16 %p to i32916 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)917 %2 = tail call <4 x i32> @llvm.arm.mve.vqrdmlash.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c, <4 x i1> %1)918 ret <4 x i32> %2919}920 921declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)922declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)923declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)924 925declare <8 x half> @llvm.fma.v8f16(<8 x half>, <8 x half>, <8 x half>)926declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>)927declare <8 x half> @llvm.arm.mve.fma.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x half>, <8 x i1>)928declare <4 x float> @llvm.arm.mve.fma.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x float>, <4 x i1>)929declare <16 x i8> @llvm.arm.mve.vmla.n.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>)930declare <8 x i16> @llvm.arm.mve.vmla.n.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>)931declare <4 x i32> @llvm.arm.mve.vmla.n.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>)932declare <16 x i8> @llvm.arm.mve.vmlas.n.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>)933declare <8 x i16> @llvm.arm.mve.vmlas.n.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>)934declare <4 x i32> @llvm.arm.mve.vmlas.n.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>)935declare <16 x i8> @llvm.arm.mve.vqdmlah.v16i8(<16 x i8>, <16 x i8>, i32)936declare <8 x i16> @llvm.arm.mve.vqdmlah.v8i16(<8 x i16>, <8 x i16>, i32)937declare <4 x i32> @llvm.arm.mve.vqdmlah.v4i32(<4 x i32>, <4 x i32>, i32)938declare <16 x i8> @llvm.arm.mve.vqdmlash.v16i8(<16 x i8>, <16 x i8>, i32)939declare <8 x i16> @llvm.arm.mve.vqdmlash.v8i16(<8 x i16>, <8 x i16>, i32)940declare <4 x i32> @llvm.arm.mve.vqdmlash.v4i32(<4 x i32>, <4 x i32>, i32)941declare <16 x i8> @llvm.arm.mve.vqrdmlah.v16i8(<16 x i8>, <16 x i8>, i32)942declare <8 x i16> @llvm.arm.mve.vqrdmlah.v8i16(<8 x i16>, <8 x i16>, i32)943declare <4 x i32> @llvm.arm.mve.vqrdmlah.v4i32(<4 x i32>, <4 x i32>, i32)944declare <16 x i8> @llvm.arm.mve.vqrdmlash.v16i8(<16 x i8>, <16 x i8>, i32)945declare <8 x i16> @llvm.arm.mve.vqrdmlash.v8i16(<8 x i16>, <8 x i16>, i32)946declare <4 x i32> @llvm.arm.mve.vqrdmlash.v4i32(<4 x i32>, <4 x i32>, i32)947declare <16 x i8> @llvm.arm.mve.vqdmlah.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>)948declare <8 x i16> @llvm.arm.mve.vqdmlah.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>)949declare <4 x i32> @llvm.arm.mve.vqdmlah.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>)950declare <16 x i8> @llvm.arm.mve.vqdmlash.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>)951declare <8 x i16> @llvm.arm.mve.vqdmlash.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>)952declare <4 x i32> @llvm.arm.mve.vqdmlash.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>)953declare <16 x i8> @llvm.arm.mve.vqrdmlah.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>)954declare <8 x i16> @llvm.arm.mve.vqrdmlah.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>)955declare <4 x i32> @llvm.arm.mve.vqrdmlah.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>)956declare <16 x i8> @llvm.arm.mve.vqrdmlash.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>)957declare <8 x i16> @llvm.arm.mve.vqrdmlash.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>)958declare <4 x i32> @llvm.arm.mve.vqrdmlash.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>)959