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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: opt -passes=instcombine -mtriple=thumbv8.1m.main -S %s | FileCheck --check-prefix=IR %s3; RUN: opt -passes=instcombine -mtriple=thumbv8.1m.main %s | llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -O3 -o - | FileCheck --check-prefix=ASM %s4 5%struct.foo = type { [2 x <4 x i32>] }6 7define arm_aapcs_vfpcc i32 @test_vadciq_multiple(%struct.foo %a, %struct.foo %b, i32 %carry) {8entry:9 %a.0 = extractvalue %struct.foo %a, 0, 010 %a.1 = extractvalue %struct.foo %a, 0, 111 %b.0 = extractvalue %struct.foo %b, 0, 012 %b.1 = extractvalue %struct.foo %b, 0, 113 14 %fpscr.in.0 = shl i32 %carry, 2915 %outpair.0 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32> %a.0, <4 x i32> %b.0, i32 %fpscr.in.0)16 %fpscr.out.0 = extractvalue { <4 x i32>, i32 } %outpair.0, 117 %shifted.out.0 = lshr i32 %fpscr.out.0, 2918 %carry.out.0 = and i32 1, %shifted.out.019 %fpscr.in.1 = shl i32 %carry.out.0, 2920 %outpair.1 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32> %a.1, <4 x i32> %b.1, i32 %fpscr.in.1)21 %fpscr.out.1 = extractvalue { <4 x i32>, i32 } %outpair.1, 122 %shifted.out.1 = lshr i32 %fpscr.out.1, 2923 %carry.out.1 = and i32 1, %shifted.out.124 ret i32 %carry.out.125}26 27define arm_aapcs_vfpcc i32 @test_vadciq_pred_multiple(%struct.foo %a, %struct.foo %b, i32 %ipred, i32 %carry) {28entry:29 %a.0 = extractvalue %struct.foo %a, 0, 030 %a.1 = extractvalue %struct.foo %a, 0, 131 %b.0 = extractvalue %struct.foo %b, 0, 032 %b.1 = extractvalue %struct.foo %b, 0, 133 34 %vpred = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %ipred)35 %fpscr.in.0 = shl i32 %carry, 2936 %outpair.0 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32> undef, <4 x i32> %a.0, <4 x i32> %b.0, i32 %fpscr.in.0, <4 x i1> %vpred)37 %fpscr.out.0 = extractvalue { <4 x i32>, i32 } %outpair.0, 138 %shifted.out.0 = lshr i32 %fpscr.out.0, 2939 %carry.out.0 = and i32 1, %shifted.out.040 %fpscr.in.1 = shl i32 %carry.out.0, 2941 %outpair.1 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32> undef, <4 x i32> %a.1, <4 x i32> %b.1, i32 %fpscr.in.1, <4 x i1> %vpred)42 %fpscr.out.1 = extractvalue { <4 x i32>, i32 } %outpair.1, 143 %shifted.out.1 = lshr i32 %fpscr.out.1, 2944 %carry.out.1 = and i32 1, %shifted.out.145 ret i32 %carry.out.146}47 48declare { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32>, <4 x i32>, i32)49declare { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i32>, i32, <4 x i1>)50declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)51 52; Expect the transformation in between the two intrinsics, where the53; fpscr-formatted output value is turned back into just the carry bit54; at bit 0 and then back again for the next call, to be optimized away55; completely in InstCombine, so that the FPSCR output from one56; intrinsic is passed straight on to the next:57 58; IR: %outpair.0 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32> %a.0, <4 x i32> %b.0, i32 %fpscr.in.0)59; IR: %fpscr.out.0 = extractvalue { <4 x i32>, i32 } %outpair.0, 160; IR: %outpair.1 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32> %a.1, <4 x i32> %b.1, i32 %fpscr.out.0)61 62; IR: %outpair.0 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32> undef, <4 x i32> %a.0, <4 x i32> %b.0, i32 %fpscr.in.0, <4 x i1> %vpred)63; IR: %fpscr.out.0 = extractvalue { <4 x i32>, i32 } %outpair.0, 164; IR: %outpair.1 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32> undef, <4 x i32> %a.1, <4 x i32> %b.1, i32 %fpscr.out.0, <4 x i1> %vpred)65 66; And this is the assembly language we expect at the end of it, with67; the two vadc.i32 instructions right next to each other, and the68; second one implicitly reusing the FPSCR written by the first.69 70; ASM: test_vadciq_multiple:71; ASM: lsls r0, r0, #2972; ASM-NEXT: vmsr fpscr_nzcvqc, r073; ASM-NEXT: vadc.i32 q0, q0, q274; ASM-NEXT: vadc.i32 q0, q1, q375; ASM-NEXT: vmrs r0, fpscr_nzcvqc76; ASM-NEXT: ubfx r0, r0, #29, #177; ASM-NEXT: bx lr78 79; ASM: test_vadciq_pred_multiple:80; ASM: lsls r1, r1, #2981; ASM-NEXT: vmsr p0, r082; ASM-NEXT: vmsr fpscr_nzcvqc, r183; ASM-NEXT: vpstt84; ASM-NEXT: vadct.i32 q0, q0, q285; ASM-NEXT: vadct.i32 q0, q1, q386; ASM-NEXT: vmrs r0, fpscr_nzcvqc87; ASM-NEXT: ubfx r0, r0, #29, #188; ASM-NEXT: bx lr89